CN104835720A - Semiconductor structure and method for forming same - Google Patents
Semiconductor structure and method for forming same Download PDFInfo
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- CN104835720A CN104835720A CN201510172229.8A CN201510172229A CN104835720A CN 104835720 A CN104835720 A CN 104835720A CN 201510172229 A CN201510172229 A CN 201510172229A CN 104835720 A CN104835720 A CN 104835720A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 145
- 238000000034 method Methods 0.000 title claims abstract description 74
- 239000000758 substrate Substances 0.000 claims abstract description 126
- 238000000407 epitaxy Methods 0.000 claims abstract description 10
- 230000015572 biosynthetic process Effects 0.000 claims description 23
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 239000003292 glue Substances 0.000 claims description 12
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 12
- 239000012535 impurity Substances 0.000 claims description 11
- 239000000463 material Substances 0.000 claims description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 229920005591 polysilicon Polymers 0.000 claims description 8
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- 235000012239 silicon dioxide Nutrition 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 5
- 150000001875 compounds Chemical class 0.000 claims description 5
- 229910021478 group 5 element Inorganic materials 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 3
- 229910000085 borane Inorganic materials 0.000 claims description 3
- 229910000073 phosphorus hydride Inorganic materials 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- UORVGPXVDQYIDP-UHFFFAOYSA-N trihydridoboron Substances B UORVGPXVDQYIDP-UHFFFAOYSA-N 0.000 claims description 3
- 230000007547 defect Effects 0.000 abstract description 9
- 239000013078 crystal Substances 0.000 abstract description 8
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 6
- 239000012634 fragment Substances 0.000 abstract description 5
- 238000004528 spin coating Methods 0.000 abstract 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 17
- 229910052710 silicon Inorganic materials 0.000 description 17
- 239000010703 silicon Substances 0.000 description 17
- 150000002500 ions Chemical class 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- 230000035882 stress Effects 0.000 description 6
- 230000002159 abnormal effect Effects 0.000 description 5
- 238000001259 photo etching Methods 0.000 description 4
- 238000005498 polishing Methods 0.000 description 4
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 3
- 235000011114 ammonium hydroxide Nutrition 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 238000005406 washing Methods 0.000 description 2
- 240000004859 Gamochaeta purpurea Species 0.000 description 1
- 239000000908 ammonium hydroxide Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 238000001534 heteroepitaxy Methods 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 239000011882 ultra-fine particle Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02455—Group 13/15 materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02082—Cleaning product to be cleaned
- H01L21/02087—Cleaning of wafer edges
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Recrystallisation Techniques (AREA)
Abstract
The invention provides a semiconductor structure and a method for forming the same. Through forming a stopping layer on the edge region of a semiconductor substrate, monocrystal cannot grow on the edge region of the semiconductor substrate in an epitaxial growth process, thereby ensuring crystal defects of the edge of the semiconductor substrate, caused by chamfering quality, would not be amplified to form gaps, cracks, edge breakage, and even fragments in epitaxy, and epitaxy crown and other abnormity would not occur, thereby solving problems of photoresist stacking, bad spin coating, breezing exposure and other photoresis abnormity in spin coating and exposure processes.
Description
Technical field
The invention belongs to semiconductor fabrication process technical field, relate to a kind of semiconductor structure and forming method thereof.
Background technology
The substrate that IC manufacturing uses, after cut into the silicon chip substrate with specific thicknesses from monocrystal rod, there is mechanical stress and thermal stress in the surface of silicon chip, is very easy to form damage and slip dislocation etc. abnormal, usually needs by just making moderate progress after strict last handling process.At silicon chip edge, the stress of silicon chip and the especially outstanding of impaired performance, need to use the silicon chip edge of grinder buffing through cutting with particular edge contouring, silicon chip edge is made to form specific angle and pattern, and then the mechanical stress of silicon chip edge is discharged, reduce damaged and defect, and make the stressed minimizing of silicon chip edge unit are, this process is called chamfering.Chamfer process is also the process of a mechanical wear, and after the quality in chamfer process and chamfering, the quality of process matched therewith determines the stress of silicon chip edge, defect and clean-up performance, plays an important role to the manufacturing of integrated circuit.
In the high-voltage products such as power device VDMOS, IGBT, thick epitaxy technique is the critical process realizing device withstand voltage.In actual epitaxial growth process, because silicon chip edge crystal orientation is different, have than single crystal surfaces growth rate faster in epitaxial process, thus the epitaxial thickness of silicon chip edge is larger than the epitaxial thickness of silicon chip center single-crystal surface, forms extension hat phenomenon.Simultaneously due to the stress of the not good existence of silicon chip edge quality, particle and out-of-flatness problem, in epitaxial process, form slip dislocation etc. through silicon chip edge of being everlasting abnormal." extension hat " that silicon chip edge occurs or the anomaly such as slip dislocation become more serious along with the increase of the thickness of extension.
Specifically as depicted in figs. 1 and 2, over the semiconductor substrate 10 after grown epitaxial layer 20, there is extension hat (silicon is protruding) A and slip dislocation B in Semiconductor substrate 10 edge (as shown in dotted line circle in Fig. 1 region).Wherein, the thickness of the epitaxial loayer 20 of Semiconductor substrate 10 center is Tepi, the thickness of the epitaxial loayer 20 of Semiconductor substrate 10 center is Tepi, epitaxial loayer 20 surface of Semiconductor substrate 10 center has a difference in height h1 with the epi-layer surface (extension hat top) of marginal position, epitaxial loayer 20 surface of Semiconductor substrate 10 center has a difference in height h2 with slip dislocation B top, and the epitaxial loayer gross thickness at whole Semiconductor substrate 10 edge is T.Due to extension hat and slip dislocation higher at epitaxial loayer rat, in even glue and exposure technology, easily occur that photoresist is piled up, even glue is bad, to expose the photoetching caused such as apprehensive abnormal, particularly have in the equipment of Mechanical Contact at needs and Semiconductor substrate 10 edge and easily occur breach, crack, collapse the limit even exception of fragment, simultaneously due to the existence of slip dislocation, in Semiconductor substrate 10 transfer process, edge is very easy to collide and causes breach and fragment.
Summary of the invention
The object of the invention is to, the crystal defect existed due to chamfer quality etc. can not be exaggerated formation breach, crack, collapse limit even fragment in Yanzhong outside, also can not there is extension hat etc. abnormal, solve in even glue and exposure technology the problem occurring that photoresist is piled up, even glue is bad, expose the photoetching exception such as apprehensive.
In order to solve the problem, the invention provides a kind of semiconductor structure, comprising:
There is the Semiconductor substrate of monocrystalline silicon surface;
Be formed at the trapping layer in described semiconductor substrate edge region; And
The first epitaxial loayer being simultaneously formed at the central area of described Semiconductor substrate by epitaxial growth technology and the second epitaxial loayer be formed at above described trapping layer.
Optionally, in described semiconductor structure, described Semiconductor substrate is monocrystalline substrate, SOI substrate, germanium silicon substrate, III-group Ⅴ element compound substrate, doped with N-type impurity ion or p type impurity ion in described Semiconductor substrate.
Optionally, in described semiconductor structure, the material of described trapping layer is silicon dioxide, silicon nitride or polysilicon.
Optionally, in described semiconductor structure, described trapping layer is circular.The width of described trapping layer is between 0.5 ~ 5mm.The thickness of described trapping layer exists
between.
The present invention also provides a kind of formation method of semiconductor structure, comprising:
The Semiconductor substrate that one has a monocrystalline silicon surface is provided;
Trapping layer is formed at the fringe region of described Semiconductor substrate; And
Carry out epitaxy technique growth, form the first epitaxial loayer at the zone line of described Semiconductor substrate, described trapping layer is formed the second epitaxial loayer.
Optionally, in the formation method of described semiconductor structure, described Semiconductor substrate is monocrystalline substrate, SOI substrate, germanium silicon substrate, III-group Ⅴ element compound substrate, doped with N-type impurity ion or p type impurity ion in described Semiconductor substrate.
Optionally, in the formation method of described semiconductor structure, the step forming trapping layer at the fringe region of described Semiconductor substrate comprises:
Described semiconductor substrate surface forms trapping layer;
By even glue, exposure, etching and degumming process, remove the trapping layer of described Semiconductor substrate zone line, only retain the trapping layer in described semiconductor substrate edge region.
Optionally, in the formation method of described semiconductor structure, adopt dry method anisotropic etching technics, remove the trapping layer of described Semiconductor substrate zone line.
Optionally, in the formation method of described semiconductor structure, the material of the trapping layer of the fringe region of described Semiconductor substrate is silicon dioxide, silicon nitride or polysilicon.The trapping layer of the fringe region of described Semiconductor substrate is circular, and width is between 0.5 ~ 5mm.
Optionally, in the formation method of described semiconductor structure, described epitaxial growth technology adopts SiCL4, SiHCL3, SiH2CL2 or SiH4 gas, adopts borine or phosphine as doped source, epitaxial growth temperature is between 950 ~ 1200 DEG C, and epitaxial growth rate is between 0.1 ~ 5 μm.
Optionally, in the formation method of described semiconductor structure, described first epitaxy layer thickness 10 ~ 200 μm.
Optionally, in the formation method of described semiconductor structure, before carrying out epitaxial growth technology, HCL gas is adopted to process described semiconductor substrate surface,
Optionally, in the formation method of described semiconductor structure, chemical mechanical polish process is carried out to described Semiconductor substrate.
The present invention forms trapping layer by the fringe region in Semiconductor substrate, to make in epitaxial process semiconductor substrate edge region cannot long monocrystalline, the defect existed due to chamfer quality etc. can not be exaggerated, also can not there is extension hat etc. abnormal, solve in even glue and exposure technology the problem occurring that photoresist is piled up, even glue is bad, expose the photoetching exception such as apprehensive.
Accompanying drawing explanation
With reference to accompanying drawing, according to detailed description below, clearly the present invention can be understood.For the sake of clarity, in figure, the relative thickness of each layer and the relative size of given zone are not drawn in proportion.In the accompanying drawings:
Fig. 1 is the schematic diagram that after traditional epitaxy technique, extension hat and slip dislocation appear in Semiconductor substrate fringe region;
Fig. 2 is the enlarged diagram of the fringe region of Semiconductor substrate in Fig. 1;
Fig. 3 is the schematic flow sheet of the formation method of semiconductor structure in one embodiment of the invention;
Fig. 4 is the cross-sectional view of Semiconductor substrate in one embodiment of the invention;
Fig. 5 is the cross-sectional view form trapping layer in one embodiment of the invention on semiconductor substrate surface after;
Fig. 6 is the cross-sectional view in one embodiment of the invention after semiconductor substrate edge region forms trapping layer;
Fig. 7 is the schematic top plan view in one embodiment of the invention after semiconductor substrate edge region forms trapping layer;
Fig. 8 is the cross-sectional view of the semiconductor structure formed after carrying out epitaxial growth technology in one embodiment of the invention;
Fig. 9 is the schematic top plan view of the semiconductor structure formed after carrying out epitaxial growth technology in one embodiment of the invention.
Embodiment
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.
As shown in Figure 8 and Figure 9, the invention provides a kind of semiconductor structure, comprising:
There is the Semiconductor substrate 30 of monocrystalline silicon surface;
Be formed at the trapping layer 31 of described Semiconductor substrate 30 fringe region;
The the first epitaxial loayer 33a being simultaneously formed at the central area of described Semiconductor substrate 30 by epitaxial growth technology and the second epitaxial loayer 33b be formed at above described trapping layer 31.
See Fig. 3, the present invention also provides a kind of formation method of semiconductor structure, comprises the steps:
S11, the Semiconductor substrate providing to have a monocrystalline silicon surface;
S12, described Semiconductor substrate fringe region formed trapping layer;
S13, carry out epitaxy technique growth, form the first epitaxial loayer at the zone line of described Semiconductor substrate, described trapping layer is formed the second epitaxial loayer.
Below in conjunction with generalized section, semiconductor structure of the present invention and forming method thereof is described in detail.Set forth a lot of detail in the following description so that fully understand the present invention.But the present invention can be much different from alternate manner described here to implement, those skilled in the art can when without prejudice to doing similar popularization when intension of the present invention, therefore the present invention is by the restriction of following public concrete enforcement.
Shown in composition graphs 3 and Fig. 4, perform step S11, the Semiconductor substrate 30 that has a monocrystalline silicon surface is provided.
Concrete, described Semiconductor substrate 30 can be monocrystalline substrate, SOI substrate, germanium silicon substrate, III-group Ⅴ element compound substrate, wherein can doped with N-type impurity ion or p type impurity ion.What adopt in the present embodiment is the Semiconductor substrate forming the N-type <100> crystal orientation that power device is commonly used.Certainly, the present invention does not limit the type of Semiconductor substrate 30, as long as have monocrystalline silicon surface so that carry out epitaxy technique grow on this monocrystalline silicon surface, can select corresponding Semiconductor substrate in actual growth according to part category.
Preferably, described Semiconductor substrate 30 has carried out chamfer angle technique, described chamfer angle technique refers to the edge adopting and have the grinder buffing Semiconductor substrate 30 of particular edge contouring, the edge of Semiconductor substrate 30 is made to form specific angle and pattern, and then the mechanical stress at the edge of Semiconductor substrate 30 is discharged, reduce damaged and defect, and make the stressed minimizing of Semiconductor substrate 30 edge unit are.As shown in Figure 3, after chamfering, the edge of Semiconductor substrate 30 has a radian.
Then, perform step S12, form trapping layer 31 at the fringe region of described Semiconductor substrate 30.
Specifically as shown in Figure 5 and Figure 6, first form certain thickness trapping layer 31 on the surface in Semiconductor substrate 30, then by even glue, exposure, etching and degumming process, remove the trapping layer 31 of Semiconductor substrate 30 zone line, form the first window district 32 of exposing semiconductor substrate 30, only retain the trapping layer 31 of Semiconductor substrate 30 fringe region.
Wherein, described trapping layer 31 can be the material different from described Semiconductor substrate 30 such as silicon dioxide, silicon nitride, polysilicon, certainly, the present invention does not limit its material, as long as the object that can realize selective epitaxial different from the material of Semiconductor substrate 30.
Before considering epitaxial growth, according to HCL gas, semiconductor substrate surface is processed, if trapping layer 31 thinner thickness is easily by HCL gas attack, do not have trapping layer effect; Meanwhile, trapping layer 31 thickness is also not suitable for too thick, too thick trapping layer and easily forms projection at its edge after epitaxial growth, therefore the thickness of trapping layer 31 described in the present embodiment preferably exists
between.
As shown in Figure 7, the trapping layer 31 of described Semiconductor substrate 30 fringe region is in circular, its width L1 is preferably between 0.5 ~ 5mm, if its width L1 is too little be unfavorable for the fringe region covering Semiconductor substrate 30 completely, if it is too large, can lose more die area.Certainly, in the present invention, the trapping layer 31 of Semiconductor substrate 30 fringe region is not limited to above-mentioned numerical value, can according to decisions such as Semiconductor substrate size and concrete production technology demands.
In the present embodiment, after spin processes, before exposure technology, do not carry out side washing technique.In prior art, in semiconductor fabrication, in order to reduce the phenomenon such as particle, white residue in semiconductor substrate edge region, before even glue post-exposure, the photoresist in usual removal semiconductor substrate edge region, general employing be EBR solution, make whole fringe region show as opened areas in a photolithographic process.But semiconductor substrate edge region needs to be protected by trapping layer in the present embodiment, so the region of described semiconductor substrate edge does not need to carry out side washing process.
In the present embodiment, adopt dry method anisotropic etching technics, remove the trapping layer of Semiconductor substrate 30 zone line, described dry method anisotropic is etched with to be beneficial to and makes trapping layer edge pattern precipitous, make heteroepitaxy process boundaries in subsequently epitaxial growing process more clear, reduce defect.
Before carrying out epitaxial growth technology, HCL gas can be adopted to process semiconductor substrate surface, described HCL gas has two effects: one is can clean epitaxial chamber, and two is the impurity can removing Semiconductor substrate 30 surface.
Then, perform step S13, carry out epitaxial growth technology, form the first epitaxial loayer 33a at the zone line of described Semiconductor substrate 30, form the second epitaxial loayer 33b at the fringe region with the Semiconductor substrate 30 that trapping layer 31 is protected.
In the application; described first epitaxial loayer 33a is identical with the material of described Semiconductor substrate 30; be monocrystalline silicon; and the fringe region of Semiconductor substrate 30 is protected by trapping layer 31; thus this region can not long monocrystalline, and the second epitaxial loayer 33b formed above trapping layer 31 in epitaxial process is polysilicon, thus; the defect that Semiconductor substrate 30 fringe region exists due to chamfer quality etc. can not be exaggerated in epitaxial process, also can not there is the exceptions such as extension hat.
Shown in composition graphs 8 and Fig. 9, carrying out in epitaxial process, trapping layer 31 direction that can retain along crystal orientation due to the silicon single crystal of the zone line of Semiconductor substrate 30 extends, thus the side of final the first epitaxial loayer 33a formed normally tilts, namely, first epitaxial loayer 33a is structure wide at the top and narrow at the bottom, and the second epitaxial loayer 33b is circular, and the second epitaxial loayer 33b is the structure (the width L2 at the second epitaxial loayer 33b top is less than the width bottom it) of upper narrow complimentary close.
Preferably, the thickness of described first epitaxial loayer 33a is between 10 ~ 200 μm, described epitaxial growth technology adopts SiCL4, SiHCL3, SiH2CL2 or SiH4 gas, borine or phosphine can be adopted as doped source, epitaxial growth temperature is between 950 ~ 1200 DEG C, and epitaxial growth rate is between 0.1 ~ 5 μm/min.
Find through experiment, after epitaxial growth technology, the height of the first epitaxial loayer 33a and the second epitaxial loayer 33b is basically identical, and the first epitaxial loayer 33a and the second epitaxial loayer 33b is comparatively smooth.Certainly, in order to obtain better profile pattern, after carrying out epitaxial growth, chemico-mechanical polishing (CMP) process also can be carried out.In the present embodiment, described CMP (Chemical Mechanical Polishing) process, employing can with the polishing fluid of polysilicon and monocrystalline silicon generation chemical reaction, the Selection radio of polysilicon and monocrystalline silicon elects 1:1 as, adopt grinding-material to be the alkaline silicon dioxide ultrafine particles containing ammonium hydroxide (NH4OH), the pH value of described NH4OH is 9 ~ 11, and its polishing disk rotating speed is 10 ~ 200 circles/Min, polish temperature is 20 ~ 50 degree, and polish pressure is 0.5 ~ 10 newton/cm
-2.
In sum, the present invention forms trapping layer by the fringe region in Semiconductor substrate, in epitaxial process, semiconductor substrate edge region cannot long monocrystalline, the defect existed due to chamfer quality etc. can not be exaggerated, also the exceptions such as extension hat can not be there is, solve in even glue and exposure technology the problem easily occurring that photoresist is piled up, even glue is bad, expose the photoetching exception such as apprehensive, reduce semiconductor substrate edge breach, crack that equipment contact and crash in process of production causes, collapse the limit even risk of fragment.
Although the embodiment of the present invention with preferred embodiment openly as above; but it is not for limiting claim; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible variation and amendment, the scope that therefore protection scope of the present invention should define with the claims in the present invention is as the criterion.
Claims (16)
1. a semiconductor structure, is characterized in that, comprising:
There is the Semiconductor substrate of monocrystalline silicon surface;
Be formed at the trapping layer in described semiconductor substrate edge region;
The first epitaxial loayer being simultaneously formed at the central area of described Semiconductor substrate by epitaxial growth technology and the second epitaxial loayer be formed at above described trapping layer.
2. semiconductor structure as claimed in claim 1, it is characterized in that, described Semiconductor substrate is monocrystalline substrate, SOI substrate, germanium silicon substrate, III-group Ⅴ element compound substrate, doped with N-type impurity ion or p type impurity ion in described Semiconductor substrate.
3. semiconductor structure as claimed in claim 1, it is characterized in that, the material of described trapping layer is silicon dioxide, silicon nitride or polysilicon.
4. semiconductor structure as claimed in claim 1, it is characterized in that, described trapping layer is circular.
5. semiconductor structure as claimed in claim 4, it is characterized in that, the width of described trapping layer is between 0.5 ~ 5mm.
6. a formation method for semiconductor structure, is characterized in that, comprising:
The Semiconductor substrate that one has a monocrystalline silicon surface is provided;
Trapping layer is formed at the fringe region of described Semiconductor substrate;
Carry out epitaxy technique growth, form the first epitaxial loayer at the zone line of described Semiconductor substrate, described trapping layer is formed the second epitaxial loayer.
7. the formation method of semiconductor structure as claimed in claim 6, it is characterized in that, described Semiconductor substrate is monocrystalline substrate, SOI substrate, germanium silicon substrate, III-group Ⅴ element compound substrate, doped with N-type impurity ion or p type impurity ion in described Semiconductor substrate.
8. the formation method of semiconductor structure as claimed in claim 6, is characterized in that, the step forming trapping layer at the fringe region of described Semiconductor substrate comprises:
Described semiconductor substrate surface forms trapping layer;
By even glue, exposure, etching and degumming process, remove the trapping layer of described Semiconductor substrate zone line, only retain the trapping layer in described semiconductor substrate edge region.
9. the formation method of semiconductor structure as claimed in claim 8, is characterized in that, adopts dry method anisotropic etching technics, removes the trapping layer of described Semiconductor substrate zone line.
10. the formation method of semiconductor structure as claimed in claim 6, it is characterized in that, the material of the trapping layer of the fringe region of described Semiconductor substrate is silicon dioxide, silicon nitride or polysilicon.
The formation method of 11. semiconductor structures as claimed in claim 6, it is characterized in that, the trapping layer of the fringe region of described Semiconductor substrate is circular.
The formation method of 12. semiconductor structures as claimed in claim 11, it is characterized in that, the width of the trapping layer of the fringe region of described Semiconductor substrate is between 0.5 ~ 5mm.
The formation method of 13. semiconductor structures as claimed in claim 6, it is characterized in that, described epitaxial growth technology adopts SiCL4, SiHCL3, SiH2CL2 or SiH4 gas, adopt borine or phosphine as doped source, epitaxial growth temperature is between 950 ~ 1200 DEG C, and epitaxial growth rate is between 0.1 ~ 5 μm.
The formation method of 14. semiconductor structures as claimed in claim 6, is characterized in that, described first epitaxy layer thickness 10 ~ 200 μm.
The formation method of 15. semiconductor structures as claimed in claim 6, is characterized in that, before carrying out epitaxial growth technology, adopts HCL gas to process described semiconductor substrate surface,
The formation method of 16. semiconductor structures as claimed in claim 6, is characterized in that, carry out chemical mechanical polish process to described Semiconductor substrate.
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| CN108646516A (en) * | 2017-08-28 | 2018-10-12 | 睿力集成电路有限公司 | Photoresist coating equipment |
| TWI861011B (en) * | 2018-09-26 | 2024-11-11 | 日商信越半導體股份有限公司 | Method for manufacturing epitaxial wafer, silicon substrate for epitaxial growth, and epitaxial wafer |
| CN111162040A (en) * | 2020-01-02 | 2020-05-15 | 长江存储科技有限责任公司 | Method for manufacturing semiconductor device |
| WO2022099635A1 (en) * | 2020-11-13 | 2022-05-19 | 苏州晶湛半导体有限公司 | Substrate and manufacturing method therefor |
| US20220375742A1 (en) * | 2021-05-21 | 2022-11-24 | Disco Corporation | Processing method of wafer |
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