CN108110043A - The optimization method of wafer bow - Google Patents

Abstract

A kind of optimization method of wafer bow, the described method comprises the following steps：Wafer is provided, the front of the wafer is formed with crystal face SiN, and the back side of the wafer is formed with the brilliant back of the body SiN, the crystal face SiN and brilliant back of the body SiN is formed in same furnace process；The front of the wafer is handled to form the protective layer of resistance to acid liquid corrosion in the front；Under the protection of the protective layer, at least a portion of the acid solution removal brilliant back of the body SiN is used.The present invention program can adjust the curvature of the wafer, and then contribute to by reducing the quality for adjusting wafer bow and improving the processing steps such as follow-up bonding.

Description

Optimizing Method for Wafer Bow

technical field

The invention relates to the field of semiconductor manufacturing, in particular to a method for optimizing wafer curvature.

Background technique

In the existing manufacturing technology of semiconductor devices, it is easy to appear the phenomenon of overall depression or protrusion on the surface of the wafer, which leads to the deterioration of the quality of the wafer in subsequent process steps such as bonding (Bonding).

Bending of Wafer (BOW) is usually used to evaluate the degree of concave or convex of a wafer, and the BOW of wafer is used to indicate the vertical distance between the highest point and the lowest point of the wafer surface.

There is an urgent need for a method for optimizing the curvature of the wafer to adjust the curvature of the wafer to improve the quality of subsequent bonding and other process steps.

Contents of the invention

The technical problem solved by the present invention is to provide a method for optimizing the curvature of a wafer, which can adjust the curvature of the wafer, thereby helping to improve the quality of subsequent bonding and other process steps by adjusting the curvature of the wafer.

In order to solve the above technical problems, an embodiment of the present invention provides a method for optimizing the curvature of a wafer, which includes the following steps: providing a wafer, the front side of the wafer is formed with a SiN crystal surface, and the back side of the wafer is formed with a crystal surface Back SiN, the crystal face SiN and the crystal back SiN are formed in the same furnace tube process; the front side of the wafer is processed to form a protective layer resistant to acid corrosion on the front side; Under protection, using the acid solution to remove at least a portion of the crystal back SiN.

Optionally, the crystal plane SiN is a hard mask layer for shallow trench isolation.

Optionally, processing the front side of the wafer to form a protective layer resistant to acid solution corrosion on the front side includes: patterning the hard mask layer of the shallow trench isolation, and using the patterned hard mask The film layer is a mask etching the front side of the wafer to obtain a shallow trench isolation trench; forming a shallow trench isolation filler, the shallow trench isolation filler fills the shallow trench isolation trench and covers the wafer The front side, wherein the shallow trench isolation filler serves as the protective layer.

Optionally, a gate dielectric layer and a polysilicon layer are formed on the front side of the wafer, and the crystal plane SiN is a hard mask layer of the polysilicon gate and is stacked on the surface of the polysilicon layer.

Optionally, processing the front side of the wafer to form a protective layer resistant to acid solution corrosion on the front side includes: patterning the hard mask layer of the polysilicon gate, and using the patterned hard mask The film layer is used as a mask to etch the polysilicon layer to form gate trenches and expose the gate dielectric layer; respectively form a front protection layer and a back protection layer on the front and back sides of the wafer; Under protection, the front protection layer and the hard mask layer are removed to expose the polysilicon layer, wherein the polysilicon layer and the gate dielectric layer serve as the protection layer.

Optionally, under the protection of the protection layer, using the acid solution to remove at least a part of the SiN on the crystal back includes: removing the back protection layer; under the protection of the protection layer, using the The acid solution removes at least a portion of the crystal back SiN.

Optionally, the materials of the front protection layer and the back protection layer include: silicon oxide.

Optionally, a gate structure is formed on the front side of the wafer, and the crystal plane SiN is a side wall of the gate structure.

Optionally, processing the front side of the wafer to form an acid solution corrosion-resistant protective layer on the front side includes: forming an interlayer dielectric layer on the front side of the wafer, and the interlayer dielectric layer covers the wafer. The round front surface, the gate structure and the sidewall, wherein the interlayer dielectric layer serves as the protection layer.

Optionally, using the acid solution to remove at least a part of the SiN on the crystal back includes: putting the entire wafer into the acid solution to remove at least a part of the SiN on the crystal back.

Compared with the prior art, the technical solutions of the embodiments of the present invention have the following beneficial effects:

In an embodiment of the present invention, a method for optimizing wafer curvature is provided, comprising the following steps: providing a wafer, the front side of the wafer is formed with crystal-face SiN, and the back side of the wafer is formed with crystal-back SiN, The crystal surface SiN and the crystal back SiN are formed in the same furnace tube process; the front side of the wafer is processed to form a protective layer resistant to acid corrosion on the front side; under the protection of the protective layer, Using the acid solution to remove at least a portion of the crystal-back SiN. With the above scheme, since the SiN formed by the furnace tube process is often formed on the front and back sides of the wafer, by removing at least a part of the SiN on the back of the crystal under the protection of the acid corrosion-resistant protective layer formed on the front side, the described The curvature of the wafer, which in turn helps to improve the quality of subsequent bonding and other process steps by adjusting the curvature of the wafer.

Further, in the embodiment of the present invention, the shallow trench isolation filler can be used as a protective layer, and when the crystal plane SiN is a hard mask layer for shallow trench isolation, at least a part of the crystal back SiN formed can be removed to adjust the crystal The curvature of the circle, which in turn helps to improve the quality of subsequent bonding and other process steps by adjusting the curvature of the wafer.

Further, in the embodiment of the present invention, the polysilicon layer and the gate dielectric layer can be used as protective layers, and at least a part of the SiN formed on the crystal back is removed when the SiN on the crystal plane is the hard mask layer of the polysilicon gate, so as to adjust the The curvature of the wafer can be adjusted, which in turn helps to improve the quality of subsequent bonding and other process steps by adjusting the curvature of the wafer.

Further, in the embodiment of the present invention, the interlayer dielectric layer covering the front surface of the wafer, the gate structure, and the sidewall can be used as a protective layer. At least a part of SiN is removed to adjust the curvature of the wafer, thereby helping to improve the quality of subsequent bonding and other process steps by adjusting the curvature of the wafer.

Description of drawings

Fig. 1 is a schematic cross-sectional structure diagram of a curved wafer in the prior art;

2 is a flow chart of a method for optimizing wafer curvature in an embodiment of the present invention;

3 to 6 are schematic cross-sectional structural diagrams of devices corresponding to each step in a method for optimizing wafer curvature in an embodiment of the present invention;

7 to 9 are schematic cross-sectional structural diagrams of devices corresponding to each step in another method for optimizing wafer curvature in an embodiment of the present invention;

10 to 14 are schematic cross-sectional structural diagrams of devices corresponding to each step in another method for optimizing wafer curvature in an embodiment of the present invention;

FIG. 15 to FIG. 16 are schematic cross-sectional structural diagrams of devices corresponding to each step in yet another wafer bow optimization method according to an embodiment of the present invention.

Detailed ways

In the existing semiconductor device manufacturing technology, it is easy to appear the phenomenon that the surface of the wafer forms an overall depression or protrusion, which leads to the deterioration of the quality of the wafer in subsequent process steps such as bonding.

FIG. 1 is a schematic cross-sectional structure diagram of a curved wafer in the prior art. As shown in FIG. 1 , the overall sinking of the wafer 100 occurs during the process, resulting in quality degradation in subsequent process steps such as bonding. Specifically, for example, when the device formed on the wafer 100 is a backside illumination-CMOS Image Sensors (BSI-CIS), the wafer 100 and the carrier wafer (Carrier Wafer) 101 need to be bonded , for other semiconductor devices, it may also be necessary to bond the wafer 100 to another device wafer (Device Wafer).

Wherein, the wafer 100 can be, for example, a device wafer, so that various semiconductor devices can be formed on the wafer 100 .

It should be pointed out that the purpose of adjusting the curvature of the wafer is to make the curvature of the two wafers close to improve the bonding quality. Therefore, the adjustment of the curvature of the wafer may include reducing the curvature or increasing the curvature. Spend.

Wafer curvature is generally used to evaluate the degree of wafer depression or protrusion, and the wafer curvature is used to represent the vertical distance between the highest point and the lowest point on the surface of the wafer 100 , for example, refer to L shown in FIG. 1 .

The inventors of the present invention have found through research that in the prior art, part of the reason for the higher or lower curvature of the wafer is that silicon nitride (SiN) 110 is formed on the back side of the wafer 100, and the SiN 110 has a The relatively high compressive stress or tensile stress causes the entire wafer 100 to sag or protrude.

In an embodiment of the present invention, a method for optimizing wafer curvature is provided, comprising the following steps: providing a wafer, the front side of the wafer is formed with crystal-face SiN, and the back side of the wafer is formed with crystal-back SiN, The crystal surface SiN and the crystal back SiN are formed in the same furnace tube process; the front side of the wafer is processed to form a protective layer resistant to acid corrosion on the front side; under the protection of the protective layer, Using the acid solution to remove at least a portion of the crystal-back SiN. With the above scheme, since the SiN formed by the furnace tube process is often formed on the front and back sides of the wafer, by removing at least a part of the SiN on the back of the crystal under the protection of the acid corrosion-resistant protective layer formed on the front side, the said wafer can be adjusted. The curvature of the wafer, which in turn helps to improve the quality of subsequent bonding and other process steps by adjusting the curvature of the wafer.

In order to make the above objects, features and beneficial effects of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

FIG. 2 is a flow chart of a wafer bow optimization method in an embodiment of the present invention. The method for optimizing wafer curvature may include step S21 to step S23:

Step S21: providing a wafer, the front side of the wafer is formed with SiN on the crystal plane, and the back side of the wafer is formed with SiN on the crystal back, and the SiN on the crystal plane and the SiN on the crystal back are formed in the same furnace tube process;

Step S22: processing the front side of the wafer to form an acid corrosion-resistant protective layer on the front side;

Step S23: under the protection of the protection layer, using the acid solution to remove at least a part of the SiN on the crystal back.

The above steps will be described below with reference to FIG. 3 to FIG. 6 .

3 to 6 are schematic cross-sectional structural diagrams of devices corresponding to each step in a method for optimizing wafer curvature in an embodiment of the present invention.

Referring to FIG. 3 , a wafer 200 is provided, the front side of the wafer 200 is formed with a crystal face SiN220, and the back side of the wafer is formed with a crystal back SiN210, and the crystal face SiN220 and the crystal back SiN210 are formed in the same furnace tube process Forming.

In a specific implementation, the wafer 200 may include a semiconductor substrate, such as a silicon substrate. In other specific implementation manners, the material of the semiconductor substrate can also be silicon, germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the semiconductor substrate can also be a silicon-on-insulator substrate Or a germanium-on-insulator substrate.

Specifically, crystal face SiN 220 is formed on the front side of the wafer 200 , and crystal back SiN 210 is formed on the back side of the wafer. The purpose of forming the crystal plane SiN 220 and the crystal back SiN 210 may be various, for example, to form a hard mask layer for shallow trench isolation, a hard mask layer for a polysilicon gate, or a sidewall of a gate structure.

Referring to FIG. 4 , the front side of the wafer 200 is processed to form an acid-resistant protective layer 230 on the front side.

Specifically, the protection layer 230 may be a material that needs to be formed in the manufacturing process of the semiconductor device, for example, may include a shallow trench isolation filler or an interlayer dielectric layer (Inter Layer Dielectric, ILD); the protection layer 230 may also be is additionally formed.

Wherein, the protective layer 230 should be resistant to acid corrosion, so as to protect the surface of the wafer when the acid solution is used to remove the SIN on the back of the wafer.

Referring to FIG. 5 , under the protection of the protection layer 230 , the acid solution is used to remove at least a part of the crystal back SiN 210 (refer to FIG. 4 ) to form a thinned crystal back SiN 211 .

Wherein, using the acid solution to remove at least a part of the crystal back SiN210 may include: putting the entire wafer 200 into the acid solution to remove at least a part of the crystal back SiN210.

It can be understood that when the entire wafer 200 is put into the acid solution, the SiN 220 on the crystal face and the SiN 210 on the back of the wafer 200 formed on the front and back of the wafer 200 are also put into the acid solution.

Specifically, in order to avoid damage to the semiconductor devices formed on the front side of the wafer 200, in the process of removing at least a part of the SiN210 on the back of the wafer, a wet etching (Wet-etch) method can be used, and the whole piece is placed in an acid solution To remove the wafer 200 , and try to avoid the method that needs to turn the wafer 200 upside down, such as chemical mechanical planarization (Chemical Mechanical Planarization, CMP) or dry etching (Dry-etch).

Wherein, the acid solution may include a conventional acid solution for removing SiN, such as hot phosphoric acid (H ₃ PO ₄ ). It should be pointed out that in specific implementation, any wet etching solution with a high etch ratio to SiN and the material of the protective layer can be used, that is, it has a removal effect on SiN and is difficult to remove the protective layer (such as silicon oxide, Amorphous silicon or polycrystalline silicon) solution. In the embodiment of the present invention, there is no limitation on the specific type of acid solution.

Referring to FIG. 6 , if the protection layer 230 is additionally formed, in order not to affect the manufacture of semiconductor devices, the protection layer 230 may be removed after removing an appropriate thickness of the crystal back SiN.

It should be pointed out that if the protective layer 230 is a material that needs to be formed in the manufacturing process of the semiconductor device, it may not be removed.

In the embodiment of the present invention, since the SiN formed by the furnace tube process is often formed on the front and back of the wafer 200, at least a part of the SiN 210 on the back of the crystal is removed under the protection of the acid corrosion-resistant protective layer 230 formed on the front. , the wafer curvature of the wafer 200 can be adjusted, thereby helping to improve the quality of subsequent bonding and other process steps by adjusting the wafer curvature.

7 to 9 are schematic cross-sectional structural diagrams of devices corresponding to each step in another method for optimizing wafer curvature in an embodiment of the present invention.

Wherein, the other method for optimizing the wafer curvature corresponds to the case where the crystal plane SiN is a hard mask layer for shallow trench isolation. As a non-limiting example, when forming the hard mask layer for shallow trench isolation, the thickness of the SiN on the crystal back is relatively thick (for example, 110 nanometers to 130 nanometers), and the stress generated has a greater impact on the wafer curvature. big.

Referring to FIG. 7 , a wafer 300 is provided, the front side of the wafer 300 is formed with crystal face SiN 320 , and the back side of the wafer is formed with crystal back SiN 310 .

Wherein, the crystal plane SiN320 is a hard mask layer for shallow trench isolation (Shadow Trench Isolation, STI), and the crystal plane SiN320 and the crystal back SiN310 are formed in the same furnace tube process.

In a specific implementation manner of the embodiment of the present invention, before forming the crystal surface SiN320 on the front surface of the wafer 300, a crystal surface oxide layer 304 can also be formed on the front surface of the wafer 300, and the crystal surface oxide layer 304 can be used for Form shallow trench isolation liner oxide layer (STI Pad Oxide); Surface oxide layer 304 may be formed in the same process.

Referring to FIG. 8 , the crystal plane SiN320 is patterned, that is, the hard mask layer for shallow trench isolation is patterned, and the wafer 300 is etched using the patterned hard mask layer as a mask. Front side to obtain shallow trench isolation trenches 306 .

In a specific implementation of the embodiment of the present invention, a patterned photoresist layer may be formed first, and the hard mask layer of the shallow trench isolation is etched using the patterned photoresist layer as a mask. etch, and then use the hard mask layer of the shallow trench isolation as a mask to etch the front side of the wafer 300 to obtain shallow trench isolation trenches 306 .

Referring to FIG. 9, a shallow trench isolation filler 330 is formed, and the shallow trench isolation filler 330 fills the shallow trench isolation trench 306 (refer to FIG. 8) and covers the front side of the wafer 300, wherein the shallow trench The isolation filler 330 serves as the protective layer.

In a specific implementation manner of the embodiment of the present invention, a relatively thick silicon oxide layer can be deposited by chemical vapor deposition (Chemical Vapor Deposition, CVD) to form the shallow trench isolation filler 330, for example, it can be used High Density Plasma (High Density Plasma) chemical vapor deposition method.

Further, under the protection of the shallow trench isolation filler 330 , acid solution is used to remove at least a part of the crystal back SiN 310 .

It should be pointed out that in the existing follow-up process, there is also a step of performing chemical mechanical polishing (CMP) on the shallow trench isolation filler 330 and then removing the crystal plane SiN320. In a preferred solution, the The crystal back SiN310 is protected to avoid affecting the thickness of the crystal back SiN310 when the crystal face SiN320 is subsequently removed.

Specifically, in a specific implementation manner of the embodiment of the present invention, before forming the shallow trench isolation filler 330, a front protection layer and a back protection layer may be respectively formed on the front and back of the wafer 300, and then all the protective layers are removed. The front protection layer is used to form shallow trench isolation fillers 330, and then under the protection of the back protection layer, STI CMP is performed, and then the crystal plane SiN320 is removed, and then the back protection layer is removed, and the shallow trench isolation fillers 330 and/or the crystal surface are removed. The other oxide layer on the front side of the circle 300 is a protective layer, which adjusts the thickness of the SiN310 on the crystal back.

In another specific implementation of the embodiment of the present invention, the shallow trench isolation filling 330 can also be formed, and under the protection of the shallow trench isolation filling 330, acid solution can be used to remove the crystal back SiN310 After at least a part, form a front protection layer and a back protection layer on the front and back sides of the wafer 300 respectively, then remove the front protection layer, perform STI CMP under the protection of the back protection layer, and then remove the crystal plane SiN320, and then remove the back protection layer.

It should be pointed out that in the prior art, it is difficult to form a protective layer only on the back of the wafer 300, so in the embodiment of the present invention, a front protective layer and a back protective layer are respectively formed on the front and back of the wafer 300. However, the embodiment of the present invention does not limit whether the front protective layer is formed at the same time as the back protective layer is formed.

In a specific implementation, please refer to the description in FIG. 5 for more detailed content of removing at least a part of the SiN 310 on the crystal back by using an acid solution, and details will not be repeated here.

In specific implementation, for more details about the other method for optimizing the curvature of the wafer, please refer to the description of the optimization method for the curvature of the wafer shown in FIGS. .

10 to 14 are schematic cross-sectional structural diagrams of devices corresponding to each step in yet another method for optimizing wafer curvature in an embodiment of the present invention.

Wherein, the yet another wafer curvature optimization method corresponds to the case where the crystal plane SiN is a hard mask layer of a polysilicon gate. Since the SiN on the crystal back has a certain thickness when forming the hard mask layer of the polysilicon gate, the stress generated has a certain influence on the curvature of the wafer.

Referring to FIG. 10 , a wafer 400 is provided, the front side of the wafer 400 is formed with crystal face SiN420 , and the back side of the wafer is formed with crystal back SiN410 .

Wherein, the crystal plane SiN420 is a hard mask layer of the polysilicon gate, and the crystal plane SiN420 and the crystal back SiN410 are formed in the same furnace tube process.

Specifically, before forming the crystal plane SiN420 on the front side of the wafer 400, a gate dielectric layer 402 and a crystal plane polysilicon layer 406 may also be formed on the front side of the wafer 400, so as to form a polysilicon gate in a subsequent process; Before forming the crystal back SiN 410 on the back, a crystal back SiN deposition film 401 and a crystal back polysilicon layer 404 can also be formed on the back of the wafer 400, wherein the crystal back polysilicon layer 404 and the crystal surface polysilicon layer 406 can be formed in the same process formed in.

Specifically, the crystal back SiN deposition film 401 may be formed in the same process when the crystal face SiN deposition film (not shown) is formed. More specifically, before forming the crystal plane SiN420 on the front side of the wafer 400, a silicon oxide film (such as SiO ₂ ) and a SiN deposition film formed by deposition can also be formed on the front side of the wafer 400 by thermal oxidation growth. The stress effects of the silicon oxide film and the SiN deposited film are opposite, which help to compensate each other, so as to reduce the stress on the semiconductor substrate. It should be pointed out that the SiN deposited film is often formed by depositing in a furnace tube process, so on the back side of the wafer 400 , a crystal-back SiN deposited film 401 is also formed.

Referring to FIG. 11, the crystal plane SiN420 is patterned, that is, the hard mask layer of the polysilicon gate is patterned, and the polysilicon layer 406 is etched using the patterned hard mask layer as a mask to form The gate trench 408 exposes the gate dielectric layer 402 .

In a specific implementation of the embodiment of the present invention, a patterned photoresist layer may be formed first, and the hard mask layer of the polysilicon gate is etched using the patterned photoresist layer as a mask. etch, and then use the hard mask layer of the polysilicon gate as a mask to etch the front side of the wafer 400 to obtain gate trenches 408 .

Referring to FIG. 12 , a front protection layer 432 and a back protection layer 431 are respectively formed on the front and back of the wafer 400 .

Wherein, the material of the front protection layer 432 and the back protection layer 431 may include: silicon oxide or other appropriate materials, so that by selecting an appropriate acid solution, the front side of the wafer 400 can be protected as much as possible when removing the SiN410 on the crystal back. Semiconductor devices are protected.

It should be noted that, in other methods for additionally forming the protective layer, amorphous silicon material or polysilicon material may also be used to form the protective layer.

It should be pointed out that, in another specific implementation manner of the embodiment of the present invention, before patterning the crystal plane SiN420 to form the gate trench 408, a front surface can be formed on the front surface and the back surface of the wafer 400 respectively. The protection layer 432 and the back protection layer 431 . That is, in the embodiment of the present invention, there is no limitation on the execution order of the steps shown in FIG. 11 and FIG. 12 .

It should be pointed out that in the prior art, it is difficult to form the back protective layer 431 only on the back of the wafer 400, so in the embodiment of the present invention, the front protective layer 432 and the back of the wafer 400 are respectively formed on the front and the back. The protection layer 431 is described as an example, but the embodiment of the present invention does not limit whether the front protection layer 432 is formed at the same time as the back protection layer 431 is formed.

Referring to FIG. 13 , under the protection of the back protection layer 431, the front protection layer 432 and the crystal plane SiN420 are removed to expose the polysilicon layer 406, wherein the polysilicon layer 406 and the gate dielectric layer 402 as the protective layer.

In a specific implementation manner of the embodiment of the present invention, the front protection layer 432 can be removed by using hydrofluoric acid (HF). Specifically, under the protection of the back protection layer 431, the wafer 400 can be An appropriate amount of hydrofluoric acid is sprayed on the front surface to remove the front protection layer 432 .

It should be pointed out that, in other additional methods for forming a protective layer, if an amorphous silicon material is used to form the protective layer, the protective layer can be removed by using hydrofluoric acid (HF) combined with nitric acid (HNO ₃ ), specifically , the protective layer can be removed by spraying an appropriate amount of hydrofluoric acid and nitric acid on the front surface of the wafer 400 .

Referring to FIG. 14 , under the protection of the polysilicon layer 406 and the gate dielectric layer 402 , the acid solution is used to remove at least a part of the crystal back SiN410 (refer to FIG. 13 ) to form a thinned crystal back SiN411.

In a specific implementation, please refer to the description in FIG. 5 for more detailed content of removing at least a part of the SiN410 on the crystal back by using an acid solution, and details will not be repeated here.

In specific implementation, for more detailed content about another optimization method of wafer curvature, please refer to the description of the optimization method of wafer curvature shown in FIGS. .

FIG. 15 to FIG. 16 are schematic cross-sectional structural diagrams of devices corresponding to each step in yet another wafer bow optimization method according to an embodiment of the present invention.

Wherein, the further method for optimizing wafer curvature corresponds to the case where the crystal plane SiN is a side wall of a gate structure. Since the SiN on the crystal back has a certain thickness when forming the sidewall of the gate structure, the stress generated has a certain influence on the curvature of the wafer.

Referring to FIG. 15 , a wafer 500 is provided, the front side of the wafer 500 is formed with crystal face SiN520 , and the back side of the wafer is formed with crystal back SiN510 .

Wherein, the crystal plane SiN520 is the side wall of the gate structure 506 , and the crystal plane SiN520 and the crystal back SiN510 are formed in the same furnace tube process.

Specifically, before forming the crystal plane SiN 520 on the front side of the wafer 500, a gate dielectric layer 502, a gate structure 506, and a crystal plane oxide spacer 508 may also be formed on the front side of the wafer 500; Before the back SiN 510 , a crystal back SiN deposition film 501 , a crystal back polysilicon layer 504 , and a crystal back oxide layer 507 may also be formed on the back of the wafer 500 .

Wherein, for more details about the deposited SiN film 501 on the crystal back, please refer to the description corresponding to FIG. 10 , which will not be repeated here.

The back polysilicon layer 504 may be formed in the same process of forming the polysilicon layer when the gate structure 506 is formed on the front side of the wafer 500 .

The crystal back oxide layer 507 may be formed in the same process of forming the oxide layer when the crystal plane oxide sidewall 508 is formed on the front side of the wafer 500 .

Referring to FIG. 15, an interlayer dielectric layer 530 is formed on the front surface of the wafer 500, and the interlayer dielectric layer 530 covers the front surface of the wafer 500, the gate structure 506, and the spacer 520, wherein , the interlayer dielectric layer 530 serves as the protective layer.

In a specific implementation manner of the embodiment of the present invention, a relatively thick silicon oxide layer may be deposited by chemical vapor deposition to form the interlayer dielectric layer 530 . Further, in order to improve the dielectric properties of the interlayer dielectric layer 530, the silicon oxide layer may also be lightly doped with phosphorous or boron.

Further, under the protection of the interlayer dielectric layer 530 , acid solution is used to remove at least a part of the crystal back SiN 510 .

In a specific implementation, please refer to the description in FIG. 5 for more detailed content of removing at least a part of the SiN510 on the crystal back by using an acid solution, and details will not be repeated here.

In specific implementation, for more detailed content about the optimization method of wafer curvature, please refer to the description of the optimization method of wafer curvature shown in FIGS. .

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims (10)

1. a method for optimizing wafer curvature, is characterized in that, comprises the following steps: Providing a wafer, the front side of the wafer is formed with SiN on the crystal face, and the back side of the wafer is formed with SiN on the crystal back, and the SiN on the crystal face and the SiN on the crystal back are formed in the same furnace tube process; processing the front side of the wafer to form an acid-resistant protective layer on the front side; Under the protection of the protection layer, at least a part of the crystal back SiN is removed by using the acid solution. 2. the optimization method of wafer curvature according to claim 1, is characterized in that, The crystal plane SiN is a hard mask layer for shallow trench isolation. 3. The method for optimizing wafer curvature according to claim 2, wherein processing the front side of the wafer to form an acid-resistant protective layer on the front side comprises: Patterning the hard mask layer of the shallow trench isolation, and etching the front side of the wafer with the patterned hard mask layer as a mask to obtain shallow trench isolation trenches; A shallow trench isolation filling is formed, the shallow trench isolation filling fills the shallow trench isolation trench and covers the front surface of the wafer, wherein the shallow trench isolation filling serves as the protection layer. 4. the optimization method of wafer curvature according to claim 1, is characterized in that, A gate dielectric layer and a polysilicon layer are formed on the front side of the wafer, and the crystal plane SiN is a hard mask layer of the polysilicon gate and is stacked on the surface of the polysilicon layer. 5. The method for optimizing wafer curvature according to claim 4, wherein processing the front side of the wafer to form an acid-resistant protective layer on the front side comprises: Patterning the hard mask layer of the polysilicon gate, and etching the polysilicon layer using the patterned hard mask layer as a mask to form gate trenches and expose the gate dielectric layer; Forming a front protective layer and a back protective layer on the front and back of the wafer respectively; Under the protection of the back protection layer, the front protection layer and the hard mask layer are removed to expose the polysilicon layer, wherein the polysilicon layer and the gate dielectric layer serve as the protection layer. 6. The method for optimizing wafer curvature according to claim 5, wherein, under the protection of the protective layer, using the acid solution to remove at least a part of the SiN on the crystal back comprises: removing the back protection layer; Under the protection of the protection layer, at least a part of the crystal back SiN is removed by using the acid solution. 7. The method for optimizing wafer curvature according to claim 6, wherein the material of the front protection layer and the back protection layer comprises: silicon oxide. 8 . The method for optimizing wafer curvature according to claim 1 , wherein a gate structure is formed on the front side of the wafer, and the crystal surface SiN is a side wall of the gate structure. 9. The method for optimizing wafer curvature according to claim 8, wherein processing the front side of the wafer to form an acid-resistant protective layer on the front side comprises: An interlayer dielectric layer is formed on the front surface of the wafer, and the interlayer dielectric layer covers the front surface of the wafer, the gate structure and the sidewall, wherein the interlayer dielectric layer serves as the The protective layer. 10. The method for optimizing wafer curvature according to any one of claims 1 to 9, wherein using the acid solution to remove at least a portion of the SiN on the crystal back comprises: Putting the entire wafer into the acid solution to remove at least a part of the SiN on the crystal back.