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CN104779224A - 一种功率器件的qfn封装结构 - Google Patents

一种功率器件的qfn封装结构 Download PDF

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CN104779224A
CN104779224A CN201510177211.7A CN201510177211A CN104779224A CN 104779224 A CN104779224 A CN 104779224A CN 201510177211 A CN201510177211 A CN 201510177211A CN 104779224 A CN104779224 A CN 104779224A
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groove
insulating cement
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semiconductor chip
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CN104779224B (zh
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卢涛
张小平
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Kunshan Juda Electronic Co., Ltd.
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JIANGSU SENCHIP MICROELECTRONICS CO Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

本发明公开了一种功率器件的QFN封装结构，包括双面半导体芯片、框架、第一引脚和第二引脚，所述第一引脚、第二引脚分别通过导线与双面半导体芯片电连接，所述双面半导体芯片和框架通过导电胶粘合，所述双面半导体芯片边缘对应位置的框架内侧依次设有绝缘胶槽和直角梯形溢胶槽，所述绝缘胶槽内涂满绝缘胶，所述直角梯形溢胶槽用于收集双面半导体芯片和框架压溢出的导电胶和绝缘胶，本发明的技术方案对双面半导体芯片无任何损伤，提供了绝缘隔离，确保导电胶无法与芯片短路，提高了产品成品率，使得加工生产更为简单方便。

Description

一种功率器件的QFN封装结构
技术领域
本发明涉及一种QFN封装结构，尤其涉及一种功率器件的QFN封装结构。
技术背景
随着电子电路设计趋于高度集成，对器件的封装体积要求也随之提高，传统的纽扣式封装、SMA/SMB/SMC等贴片式封装双面半导体器件逐渐无法满足高端电路设计PCB版的布图需要，更扁平、更小型的封装形式需求急迫，四周无引脚扁平式封装(QFN)为目前最为合适的芯片级封装形式，但该封装技术目前主要应用于集成电路封装，但固体放电管这样的功率器件无法适用，由于双面半导体器件在导电胶溢料时很容易与芯片形成短路。有些厂家针对这一问题做出了探讨，将半导体芯片做了边角损伤处理，通过溢流槽来处理溢出导电胶，但还存在着加工复杂，尤其是对半导体芯片形成了一定的伤害，而且成品率不高，导电胶可能逃逸出溢流槽外溢而引起的短路故障难以完全杜绝的不足之处。
发明内容
本发明克服了现有技术中的缺点，提供了一种功率器件的QFN封装结构。
为了解决上述技术问题，本发明是通过以下技术方案实现的：一种功率器件的QFN封装结构，包括双面半导体芯片、框架、第一引脚和第二引脚，所述第一引脚、第二引脚分别通过导线与双面半导体芯片电连接，所述双面半导体芯片和框架通过导电胶粘合，所述双面半导体芯片边缘对应的框架位置表面上向内按序设有绝缘胶槽和直角梯形溢胶槽，所述绝缘胶槽内涂满绝缘胶，所述直角梯形溢胶槽用于收集双面半导体芯片和框架压溢出的导电胶和绝缘胶。
作为优选，所述绝缘胶槽外围边距离双面半导体芯片边缘70～120μm，所述绝缘胶槽槽宽30～50μm，槽深20～30μm，所述绝缘胶槽内围边和直角梯形溢胶槽外围边之间的距离80～100μm，所述直角梯形溢胶槽的上边长170～220μm，下边长250～300μm，槽高为50～60μm。
作为优选，所述导电胶型号为京瓷2815A，所述绝缘胶型号为美国HumiSeal 1A34。
与现有技术相比，本发明的优点是：对双面半导体芯片无任何损伤；提供了绝缘隔离，确保导电胶无法与芯片短路；提高了产品成品率；使得加工生产更为简单方便。
附图说明
图1是本发明实施例的结构示意图。
具体实施方式
下面结合附图与具体实施方式对本发明作进一步详细描述。
如图1所示，一种功率器件的QFN封装结构，包括双面半导体芯片1、框架2、第一引脚5和第二引脚6，所述第一引脚5、第二引脚6分别通过导线与双面半导体芯片1电连接，所述双面半导体芯片1和框架2通过导电胶粘合，所述双面半导体芯片1边缘对应的框架2位置表面上向内按序设有绝缘胶槽4和直角梯形溢胶槽3，所述绝缘胶槽4内涂满绝缘胶，所述直角梯形溢胶槽3用于收集双面半导体芯片1和框架2压溢出的导电胶和绝缘胶。所述绝缘胶槽4外围边距离双面半导体芯片1边缘90μm，所述绝缘胶槽4槽宽40μm，槽深25μm，所述绝缘胶槽4内围边和直角梯形溢胶槽3外围边之间的距离90μm，所述直角梯形溢胶槽3的上边长180μm，下边长260μm，槽高为55μm。所述导电胶型号为京瓷2815A，所述绝缘胶型号为美国HumiSeal 1A34。
本发明使用时，由于绝缘胶槽4内涂满HumiSeal 1A34绝缘胶，在双面半导体芯片1下最外围形成了一道绝缘保护墙，而多余的HumiSeal 1A34绝缘胶和京瓷2815A导电胶可以汇集到直角梯形溢胶槽3内，保障多余的京瓷2815A导电胶不会逃逸出绝缘胶槽4的绝缘保护墙外，确保导电胶无法与双面半导体芯片1短路。采用这种方式，双面半导体芯片1无需进行额外加工处理，更有利于双面半导体芯片1的结构安全，而且加工生产更为简单方便，提高了产品成品率。
除了上述的实施例外，其他未述的实施方式也应在本发明的保护范围之内。本文所述的具体实施例仅仅是对本发明精神作举例说明，本发明所属技术领域的技术人员可以对所描述的具体实施例做各种各样的修改或补充或采用类似的方式替代，但并不会偏离本发明的精神或超越所附权利要求书所定义的范围。本文虽然透过特定的术语进行说明，但不排除使用其他术语的可能性，使用这些术语仅仅是为了方便地描述和解释本发明的本质，把它们解释成任何一种附加的限制都是与本发明精神相违背的。

Claims (3)

1.一种功率器件的QFN封装结构，包括双面半导体芯片、框架、第一引脚和第二引脚，所述第一引脚、第二引脚分别通过导线与双面半导体芯片电连接，所述双面半导体芯片和框架通过导电胶粘合，其特征在于，所述双面半导体芯片边缘对应的框架位置表面上向内按序设有绝缘胶槽和直角梯形溢胶槽，所述绝缘胶槽内涂满绝缘胶，所述直角梯形溢胶槽用于收集双面半导体芯片和框架压溢出的导电胶和绝缘胶。
2.根据权利要求1所述的一种功率器件的QFN封装结构，其特征在于，所述绝缘胶槽外围边距离双面半导体芯片边缘70～120μm，所述绝缘胶槽槽宽30～50μm，槽深20～30μm，所述绝缘胶槽内围边和直角梯形溢胶槽外围边之间的距离80～100μm，所述直角梯形溢胶槽的上边长170～220μm，下边长250～300μm，槽高为50～60μm。
3.根据权利要求2所述的一种功率器件的QFN封装结构，其特征在于，所述导电胶型号为京瓷2815A，所述绝缘胶型号为美国HumiSeal 1A34。
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Cited By (2)

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CN107833960A (zh) * 2017-10-23 2018-03-23 山东晶泰星光电科技有限公司 一种具有溢流通道和溢流槽的led支架及其制造方法
WO2023035101A1 (zh) * 2021-09-07 2023-03-16 华为技术有限公司 芯片封装结构和用于制备芯片封装结构的方法

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107833960A (zh) * 2017-10-23 2018-03-23 山东晶泰星光电科技有限公司 一种具有溢流通道和溢流槽的led支架及其制造方法
WO2023035101A1 (zh) * 2021-09-07 2023-03-16 华为技术有限公司 芯片封装结构和用于制备芯片封装结构的方法

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