CN104778288B - A kind of self the digraph type decomposition method of dummy pattern Multilayer stack unit - Google Patents
A kind of self the digraph type decomposition method of dummy pattern Multilayer stack unit Download PDFInfo
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Abstract
The present invention relates to a kind of self digraph type decomposition method of dummy pattern Multilayer stack unit and the domain digraph type decomposition process being consequently formed, methods described to include:Step(a)It is two new Multilayer stack unit A and B to decompose and define original virtual pattern Multilayer stack unit;Step(b)The filling starting point is defined first, A stack cells are filled since being filled starting point, obtains accounting for the first stack virtual pattern of whole dummy patterns 1/4;Step(c)The filling starting point is shifted to the right, with step(b)Filling be spaced in first dummy pattern side filling B stack cells;Step(d)The filling starting point is shifted upwards, and B stack cells are filled in the top that the first dummy pattern is spaced in identical filling;Step(e)Filling starting point is shifted to upper right side diagonal, with step(b)Filling be spaced in remaining space filling A stack cells.This method can realize digraph type(double pattern)Self is decomposed.
Description
Technical field
The present invention relates to semiconductor applications, in particular it relates to a kind of dummy pattern Multilayer stack unit self
Digraph type decomposition method and the domain digraph type decomposition process being consequently formed.
Background technology
Increasingly increase for the semiconductor storage demand of high power capacity, the integration density of these semiconductor storages
It is concerned by people, in order to increase the integration density of semiconductor storage, employs many different sides in the prior art
Method, such as multiple memory cell are formed on single wafer by reducing wafer size and/or changing inner structure unit, for
For the method for increasing integration density by changing cellular construction, carry out attempting horizontal layout of the ditch by changing active area
Or change cell layout and carry out reduction unit area.
In the preparation technology of semiconductor devices, with the continuous diminution of device size, and more advanced light is used
Etching system(Far ultraviolet, extreme ultra violet, EUV)Delay, cause in device fabrication process inevitable
To use digraph type(Double patterning, DP)Technology, in the digraph type technology, one of domain is set
Putting needs to decompose(decomposed)For two Multilayer stack units, such as according to two different features(features)Carry out
Split.
With the continuous diminution of semiconductor technology device size, when the dimensions of semiconductor devices is contracted to Nano grade,
Manufacturability design(Design for Manufacturing, DFM)In semi-conductor industry nano-engineer flow and method
Become more and more important.The DFM refer to by the production efficiency of fast lifting chip yield and reduce production cost for the purpose of,
Rule, tool and method in the design of Unify legislation chip, so as to better control over duplication of the integrated circuit to physics wafer, it is
The design of process variability in a kind of predictable manufacturing process so that reach and optimize from the whole process for being designed into wafer manufacture.
Dummy pattern is automatically added to during the DFM(dummy)Become more and more important, the dummy pattern can be with
The Density Distribution of target pattern is helped improve, makes the device performance more homogeneous, the technique such as increase planarization, photoetching, etching
Process capability.
Due to digraph type(Double patterning, DP)Technology needs to decompose all patterns in figure layer at two
On mask, therefore during data processing, it is automatically inserted into dummy pattern and is also required to decompose two differences as original pattern pattern
Subdata type on.Especially for the dummy pattern of Multilayer stack, the dummy pattern of the Multilayer stack includes one layer
Or multilayer needs the figure layer that digraph type decomposes, the decomposition is just more complicated and spends resource.The flow chart of the decomposition is such as
Shown in Fig. 1, pattern domain is obtained first in the method, dummy pattern is then inserted according to automatic dummy pattern formula, such as schemed
Shown in 2a.During the dummy pattern is inserted, it is stack cell to define original virtual pattern Multilayer stack unit first
A, required complete dummy pattern disposably then is formed to whole pattern domain insertion A stack cells.After filling dummy pattern,
Need to carry out digraph type decomposition together to the dummy pattern and original pattern domain, as shown in Figure 2 b, due in the process
Described in double decomposition be simultaneously for the original pattern domain and newly plus automatic dummy pattern, cause the decomposable process need
CPU run times, DP decomposition license and the hardware resource of many are taken, very big trouble is brought to whole process.
Therefore, how the decomposition to digraph type of the prior art is improved, during to eliminate and to mitigate above-mentioned operation
Between it is long, take the problem of the problem of many DP decompose license and hardware resource etc. turns into current urgent need to resolve.
The content of the invention
A series of concept of reduced forms is introduced in Summary, this will enter in specific embodiment part
One step describes in detail.The Summary of the present invention is not meant to attempt to limit technical scheme claimed
Key feature and essential features, the protection domain for attempting to determine technical scheme claimed is not meant that more.
The present invention is in order to solve problems of the prior art, there is provided a kind of dummy pattern Multilayer stack unit from
My digraph type decomposition method, methods described fill four dummy pattern stack cells to realize multilayer by shifting filling starting point
Digraph type decomposes the digraph type for requiring layer in stack cell(double pattern)Self splits, including:
Step(a)It is two new Multilayer stack unit A and B to decompose and define original virtual pattern Multilayer stack unit;
Step(b)The first filling step is performed, defines the filling starting point first, is filled out since the filling starting point
A stack cell dummy patterns are filled, obtain accounting for the first stack virtual pattern of whole dummy patterns 1/4;
Step(c)The second filling step is performed, the filling starting point is shifted to the right, with step(b)Filling be spaced in
The side filling B stack cells of first dummy pattern, obtain accounting for the second stack virtual pattern of whole dummy patterns 1/4;
Step(d)The 3rd filling step is performed, shifts the filling starting point upwards, described the is spaced in identical filling
The top filling B stack cells of one dummy pattern, obtain accounting for the 3rd stack virtual pattern of whole dummy patterns 1/4;
Step(e)The 4th filling step is performed, the filling starting point is shifted to upper right side diagonal, with step
(b)Filling be spaced in remaining space filling A stack cells, obtain the 4th stack virtual pattern.
Preferably, in the step(a)In, A stack cells include a certain digraph type and decompose the A subnumbers for requiring layer
According to type (Data Type);B stack cells include a certain digraph type decomposition and require layer(With the main GDS No. of A identicals)'s
B subdata types;Other designs of stack cell are identical.
Preferably, the step(b)In, the filling between stack cell is filled at intervals of for X and Y, fills starting point
Wherein, X=X1+2X2, Y=Y1+2Y2, the X1For the big of the original virtual pattern Multilayer stack unit length of side in the X-axis direction
It is small, the X2For the filling interval in the original virtual pattern Multilayer stack unit X-direction;The Y1For the original void
Intend the size of the pattern Multilayer stack unit length of side in the Y-axis direction, the Y2For the original virtual pattern Multilayer stack unit Y
Filling interval on direction of principal axis.
Preferably, in the step(c)With the step(d)In, the filling spacing of the B stack cells is X, Y;
In the step(e)The filling spacing of the A stack cells is X, Y.
Preferably, in the step(c)In, in the X-axis direction by the step(b)Filling starting point move right
X1+X2Distance, obtain the second filling starting point, since described second filling starting point position with and step(b)Identical
Filling interval X, Y insertion B stack cells, obtain accounting for the second stack virtual pattern of whole dummy patterns 1/4.
Preferably, in the step(d)In, in the Y-axis direction by the step(b)Filling starting point move up
Y1+Y2Distance, obtain the 3rd filling starting point, since the described 3rd filling starting point position with step(b)Identical is filled out
Interval X, Y insertion B stack cells are filled, obtain accounting for the 3rd stack virtual pattern of whole dummy patterns 1/4.
Preferably, in the step(e)In, first by the step(b)Filling starting point moved right along X-direction
Dynamic X1+X2Distance, then move up Y along Y direction1+Y2Distance, obtain the 4th filling starting point, filled out from the described 4th
The position for filling up initial point starts with step(b)Identical filling interval X, Y insertion A stack cells, obtain remaining accounting for whole void
Intend the 4th stack virtual pattern of pattern 1/4.
The present invention forms one by self digraph type decomposition method of above-described dummy pattern Multilayer stack unit
The new domain digraph type decomposition process of kind, the flow include:
Step(I)Pattern domain is provided;
Step(II)Using automatic dummy pattern filling formula insertion dummy pattern, in this step from above-mentioned virtual graph
Self digraph type decomposition method of case Multilayer stack unit, to realize, digraph type decomposes requirement in the Multilayer stack dummy pattern
The digraph type of layer(double pattern)Self is decomposed;
Step(III)The master pattern that need to be only directed in the pattern domain(drawing layout)Carry out traditional use
Electric design automation manufacturer software is permitted(EDA vendor license)Digraph type decompose;
Step(IV)Domain after output decomposition.
A kind of self digraph type decomposition method of dummy pattern Multilayer stack unit, methods described are provided in the present invention
Four dummy pattern stack cells are filled to realize digraph type decomposition requirement in Multilayer stack unit by shifting filling starting point
The digraph type of layer(double pattern)Self splits.
The invention provides a kind of independent digraph type decomposition method for the dummy pattern storehouse, in methods described
In by 4 filling steps, 1/4 dummy pattern is filled in each filling step, is realized and same double in the prior art
Pattern decomposition result.Methods described is direct and what is simplified requires that layer is filled out automatically to digraph type decomposition in a dummy pattern storehouse
Two new Multilayer stack unit A and B are filled, and do not need other special decomposition, save time and resource.
Brief description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, for explaining the device of the present invention and principle.In the accompanying drawings,
Fig. 1 is in the prior art to domain (including master pattern and dummy pattern stack cell pattern) progress digraph type decomposition
Method flow diagram;
Fig. 2 a-2b are the structural representation decomposed in the prior art to dummy pattern stack cell;
Fig. 3 a-3d are the structural representation that the present invention one is specifically decomposed in embodiment to dummy pattern stack cell
Figure;
Fig. 4 be the present invention one specifically in embodiment using the present invention dummy pattern Multilayer stack unit self is double
A kind of new domain digraph type decomposition process figure that pattern decomposition method is formed.
Embodiment
In the following description, a large amount of concrete details are given to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention can be able to without one or more of these details
Implement.In other examples, in order to avoid obscuring with the present invention, do not enter for some technical characteristics well known in the art
Row description.
It should give it is noted that term used herein above is merely to describe specific embodiment, and be not intended to restricted root
According to the exemplary embodiment of the present invention.As used herein, unless the context clearly indicates otherwise, otherwise singulative
Intention includes plural form.Additionally, it should be understood that when using term "comprising" and/or " comprising " in this manual
When, it, which is indicated, has the feature, entirety, step, operation, element and/or component, but does not preclude the presence or addition of one or more
Individual other features, entirety, step, operation, element, component and/or combinations thereof.
Now, the exemplary embodiment according to the present invention is more fully described with reference to the accompanying drawings.However, these exemplary realities
Applying example can be implemented with many different forms, and should not be construed to be limited solely to the embodiments set forth herein.Should
Understand be to provide these embodiments be in order that disclosure of the invention is thoroughly and complete, and by these exemplary implementations
The design of example is fully conveyed to those of ordinary skill in the art.In the accompanying drawings, for the sake of clarity, using identical reference
Identical element is represented, thus description of them will be omitted.
Need to take excessive CPU run times, DP to solve digraph type decomposable process in the prior art in the present invention
A kind of the problem of decomposing license and hardware resource, there is provided self digraph type decomposition side of dummy pattern Multilayer stack unit
Method, including:
Step(a)It is two new Multilayer stack unit A and B to decompose and define original virtual pattern Multilayer stack unit;
Step(b)The first filling step is performed, defines the filling starting point first, is filled out since the filling starting point
A stack cell dummy patterns are filled, obtain accounting for the first stack virtual pattern of whole dummy patterns 1/4;
Step(c)The second filling step is performed, the filling starting point is shifted to the right, with step(b)Filling be spaced in
The side filling B stack cells of first dummy pattern, obtain accounting for the second stack virtual pattern of whole dummy patterns 1/4;
Step(d)The 3rd filling step is performed, shifts the filling starting point upwards, is spaced in identical filling described
The top filling B stack cells of first dummy pattern, obtain accounting for the 3rd stack virtual pattern of whole dummy patterns 1/4;
Step(e)The 4th filling step is performed, the filling starting point is shifted to upper right side diagonal, with step
(b)Filling be spaced in remaining space filling A stack cells, obtain the 4th stack virtual pattern.
The present invention forms one by self digraph type decomposition method of above-described dummy pattern Multilayer stack unit
The new domain digraph type decomposition process of kind, as shown in figure 4, the flow includes:
Step(I)Pattern domain is provided;
Step(II)Using automatic dummy pattern filling formula insertion dummy pattern, in this step from above-mentioned virtual graph
Self digraph type decomposition method of case Multilayer stack unit, to realize, digraph type decomposes requirement in the Multilayer stack dummy pattern
The digraph type of layer(double pattern)Self is decomposed;
Step(III)The master pattern that need to be only directed in the pattern domain(drawing layout)Carry out traditional use
Electric design automation manufacturer software is permitted(EDA vendor license)Digraph type decompose;
Step(IV)Domain after output decomposition.
Wherein, the step(II)In self digraph type decomposition method of dummy pattern Multilayer stack unit is included:
Step(a)It is two new Multilayer stack unit A and B to decompose and define original virtual pattern Multilayer stack unit;
Step(b)The first filling step is performed, defines the filling starting point first, is filled out since the filling starting point
A stack cell dummy patterns are filled, obtain accounting for the first stack virtual pattern of whole dummy patterns 1/4;
Step(c)The second filling step is performed, the filling starting point is shifted to the right, with step(b)Filling be spaced in
The side filling B stack cells of first dummy pattern, obtain accounting for the second stack virtual pattern of whole dummy patterns 1/4;
Step(d)The 3rd filling step is performed, shifts the filling starting point upwards, is spaced in identical filling described
The top filling B stack cells of first dummy pattern, obtain accounting for the 3rd stack virtual pattern of whole dummy patterns 1/4;
Step(e)The 4th filling step is performed, the filling starting point is shifted to upper right side diagonal, with step
(b)Filling be spaced in remaining space filling A stack cells, obtain the 4th stack virtual pattern.
Below in conjunction with the accompanying drawings and embodiment is made to the method that a kind of dummy pattern stack cell of the invention self decomposes
Further instruction.
Embodiment 1
The invention provides a kind of domain digraph type decomposition method, methods described includes:
Step(I)Pattern domain is provided;
Step(II)Using automatic dummy pattern filling formula insertion dummy pattern, in this step to the Multilayer stack
Digraph type, which decomposes, in dummy pattern requires that layer carries out digraph type(double pattern)Self is decomposed;
Step(III)The master pattern that need to be only directed in the pattern domain(drawing layout)Carry out traditional use
Electric design automation manufacturer software is permitted(EDA vendor license)Digraph type decompose;
Step(IV)Domain after output decomposition.
The Multilayer stack dummy pattern self is decomposed into an independent step, and institute in subsequent step in the method
State pattern pattern self to decompose separately, be compared to the prior art two independent steps:Step(II)And step(III), from
And alleviate needs to take excessive CPU operations in dummy pattern in the prior art and original pattern pattern while decomposable process
The problem of time, DP decompose license and hardware resource, improves decomposition efficiency.
Below for step(II)It is further described in detail, the step(II)Including:
Step(a)It is two new Multilayer stack unit A and B to decompose and define original virtual pattern Multilayer stack unit;
In this step, A stack cells include the A subdata types (Data that a certain digraph type decomposition requires layer
Type);B stack cells include a certain digraph type decomposition and require layer(With the main GDS No. of A identicals)B subdata types;
Other designs of stack cell are identical.
Step(b)The first filling step is performed, defines the filling starting point, such as the signified place of arrow in Fig. 3 a first
For the filling starting point, A stack cells are filled since the filling starting point, obtain accounting for the of whole dummy patterns 1/4
One storehouse dummy pattern.
Preferably, the spacing between each A stack cells in the first stack virtual pattern is X, Y, wherein, X=
X1+2X2, Y=Y1+2Y2, the X1It is described for the size of the original virtual pattern Multilayer stack unit length of side in the X-axis direction
X2For the filling interval in the original virtual pattern Multilayer stack unit X-direction;The Y1It is more for the original virtual pattern
The size of the layer stack unit length of side in the Y-axis direction, the Y2For in the original virtual pattern Multilayer stack unit Y direction
Filling interval.
Preferably, the filling starting point is the place that the first dummy pattern starts filling, typically in the virtual graph
The case lower left corner, the signified round dot such as arrow in Fig. 3 a.Certainly described filling starting point can also be arranged on first virtual graph
The upper left corner of case, is not limited only to certain point, and inserting situation according to dummy pattern is selected, it should be understood that
For the first dummy pattern, the filling starting point must be unified, such as be respectively positioned on the lower-left of first dummy pattern
Angle or the upper left corner.
After A stack cells are inserted, in the A stack cells either above or below, side or every four first void
Intending the position of pattern center can further insert other stack cell.Such as in step(c)In, in the A storehouses
The side filling B stack cells of unit, obtain the second stack virtual pattern, as shown in Figure 3 b.
Step(c)The second filling step is performed, shifts the filling starting point to the right, with first dummy pattern
B stack cells are filled in side, obtain accounting for the second stack virtual pattern of whole dummy patterns 1/4.
In this step in the X-axis direction, the side filling B stack cells of the A stack cells dummy pattern, the A
The distance between dummy pattern of stack cell is X1+2X2, after the B stack cell dummy patterns that the length of side is X1 are inserted, institute
The space stated between A stack cells is filled, in the X-axis direction, because the A stack cells are arranged at intervals and the B storehouses
Unit interval is set, and is disposed adjacent the A stack cells and the B stack cells, distance between the two is X2, realize
A stack cells side is filled up completely with.
Specifically, in this step, in the X-axis direction by the filling starting point movement X1+X2Distance, obtain second
Fill starting point, as shown in the signified rectangular block of the arrow in Fig. 3 b, since the position of the described second filling starting point with
B stack cells are inserted away from X, Y, obtain the second stack virtual pattern.
In step(d)In, the 3rd filling step is performed, the filling starting point is shifted upwards, with virtual described first
The top filling B stack cells of pattern, obtain accounting for the 3rd stack virtual pattern of whole dummy patterns 1/4.
In this step in the Y-axis direction, B stack cells are inserted in the A stack cells either above or below, obtains the
The distance between three stack virtual patterns, the A stack cells are Y1+2Y2, when the insertion length of side is Y1B stack cells after,
The distance between the A stack cells described in the Y-axis direction and the B stack cells are Y2, realize above A stack cells
Be filled up completely with.
Specifically, in this step, in the Y-axis direction by the filling starting point movement Y1+Y2Distance, obtain the 3rd
Starting point is filled, as shown in the pattern of the signified triangle of arrow in Fig. 3 c, since the position of the described 3rd filling starting point
B stack cells are inserted with spacing X, Y, obtain the 3rd stack virtual pattern.
Step(e)The 4th filling step is performed, the filling starting point is shifted to upper right side diagonal, with step
(b)Filling be spaced in remaining space filling A stack cells, obtain the 4th stack virtual pattern.
Wherein, the first stack virtual pattern, the second stack virtual pattern and the 3rd heap are being inserted in this step
After stack dummy pattern, only above the B stack cells of the second stack virtual pattern, the 3rd stack virtual pattern
Space is left in B stack cells side, and the space is only capable of inserting a stack cell, enters A heap landing accounts in the spatial interpolation
Member, to realize the filling of all dummy patterns.
Specifically, first in the X-axis direction by the filling starting point movement X1+X2Distance, then continue in Y-axis
Mobile Y1+Y2Distance, the 4th filling starting point is obtained, as shown in the signified criss-cross pattern of arrow in Fig. 3 d, from described the
The position of four filling starting points starts to insert A stack cells with spacing X, Y, obtains the 4th stack virtual pattern.
As other implementations, other insertion methods can also be selected in this step, such as directly with described
Based on second filling starting point, the described second filling starting point is moved into Y in the Y-axis direction1+Y2Distance, obtain the 4th and fill out
Initial point is filled up, A stack cells is inserted in the position of the described 4th filling starting point, obtains the 4th stack virtual pattern.
Or directly based on the described 3rd filling starting point, by the described 3rd filling starting point in the X-axis direction
Mobile X1+X2Distance, obtain the 4th filling starting point, the described 4th filling starting point position insert A stack cells, obtain
To the 4th stack virtual pattern.
Preferably, in the process, the first stack virtual pattern, the second stack virtual pattern, the 3rd storehouse
The size of dummy pattern is the same in dummy pattern and the 4th stack virtual pattern, and its length of side is respectively X1And Y1, as entirety,
The distance between adjacent described dummy pattern is respectively X in X-axis and Y-axis2And Y2, wherein the X1、Y1、X2And Y2Value
A certain scope is not limited to, can be adjusted as needed.
The invention provides a kind of independent digraph type decomposition method for the dummy pattern storehouse, in methods described
In by 4 filling steps, 1/4 dummy pattern is filled in each filling step, is realized and same double in the prior art
Pattern decomposition result.Methods described is direct and what is simplified requires that layer is filled out automatically to digraph type decomposition in a dummy pattern storehouse
Two kinds of stack cells are filled, and do not need other special decomposition, save time and resource.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and the purpose of explanation, and be not intended to limit the invention in described scope of embodiments.In addition people in the art
Member can also make more kinds of it is understood that the invention is not limited in above-described embodiment according to the teachings of the present invention
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (8)
1. a kind of self digraph type decomposition method of dummy pattern Multilayer stack unit, methods described fills starting point by shifting
To realize, the decomposition of digraph type requires that the digraph type of layer is split self to four dummy pattern stack cells of filling in Multilayer stack unit,
Including:
It is two new Multilayer stack unit A and B that step (a), which is decomposed and defines original virtual pattern Multilayer stack unit,;
Step (b) performs the first filling step, defines the filling starting point first, and A is filled since the filling starting point
Stack cell, obtain accounting for the first stack virtual pattern of whole dummy patterns 1/4;
Step (c) performs the second filling step, shifts the filling starting point to the right, is spaced in the filling of the step (b)
The side filling B stack cells of the first stack virtual pattern, obtain accounting for the second stack virtual figure of whole dummy patterns 1/4
Case;
Step (d) performs the 3rd filling step, shifts the filling starting point upwards, is spaced in the filling of the step (b)
The top filling B stack cells of the first stack virtual pattern, obtain accounting for the 3rd stack virtual figure of whole dummy patterns 1/4
Case;
Step (e) performs the 4th filling step, the filling starting point is shifted to upper right side diagonal, with step (b)
Filling is spaced in filling A stack cells in remaining space, obtains the 4th stack virtual pattern.
2. according to the method for claim 1, it is characterised in that in the step (a), A stack cells include described double
Pattern decomposes the A subdata types for requiring layer;B stack cells include the digraph type and decompose the B subdata types for requiring layer;Institute
A stack cells and the B stack cells are stated in the A subdatas type and the B subdatas type Bu Tong outer remaining design
It is identical.
3. according to the method for claim 1, it is characterised in that in the step (b), fill the filling between stack cell
The distance at interval is X and Y, wherein, X=X1+2X2, Y=Y1+2Y2;
The X1For the size of the original virtual pattern Multilayer stack unit length of side in the X-axis direction, the X2To be described original
Filling interval in dummy pattern Multilayer stack unit X-direction;The Y1For the original virtual pattern Multilayer stack unit
The size of the length of side in the Y-axis direction, the Y2Between the filling in the original virtual pattern Multilayer stack unit Y direction
Every.
4. according to the method for claim 3, it is characterised in that in the step (c) and the step (d), the B heaps
The filling spacing of stack cell is X, Y;
It is X, Y in the filling spacing of the step (e) the A stack cells.
5. according to the method for claim 3, it is characterised in that in the step (c), in the X-axis direction by the step
Suddenly the filling starting point of (b) moves right X1+X2Distance, the second filling starting point is obtained, from the described second filling starting point
Position starts, to fill interval X, Y insertion B stack cells with step (b) identical, to obtain accounting for whole dummy patterns 1/4
The second stack virtual pattern.
6. according to the method for claim 3, it is characterised in that in the step (d), in the Y-axis direction by the step
Suddenly the filling starting point of (b) moves up Y1+Y2Distance, the 3rd filling starting point is obtained, from described 3rd filling starting point
Position starts to fill interval X, Y insertion B stack cells with step (b) identical, obtains accounting for described the of whole dummy patterns 1/4
Three stack virtual patterns.
7. according to the method for claim 3, it is characterised in that in the step (e), first by the step (b)
Filling starting point moves right X along X-direction1+X2Distance, then move up Y along Y direction1+Y2Distance, obtain
Four filling starting points, interval X, Y insertion A heaps are filled with step (b) identical since the position of the described 4th filling starting point
Stack cell, obtain remaining the 4th stack virtual pattern for accounting for whole dummy patterns 1/4.
A kind of 8. version of self digraph type decomposition method of the dummy pattern Multilayer stack unit based on described in claim 1 to 7
Figure digraph type decomposition method, methods described include:
Step (I) provides pattern domain;
Step (II) using automatic dummy pattern filling formula insertion dummy pattern, in this step from claim 1 to 7 it
Self digraph type decomposition method of the one dummy pattern Multilayer stack unit, it is double in the Multilayer stack dummy pattern to realize
Pattern, which decomposes, requires that the digraph type of layer self decomposes;
The master pattern that step (III) is directed in the pattern domain carries out digraph type decomposition;
Domain after step (IV) output decomposition.
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Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101178744A (en) * | 2006-11-06 | 2008-05-14 | 茂德科技股份有限公司(新加坡子公司) | Methods of automatically generating dummy fill having reduced storage size |
CN103035627A (en) * | 2011-10-05 | 2013-04-10 | 钜景科技股份有限公司 | Stack type semiconductor packaging structure |
CN103311102A (en) * | 2012-03-13 | 2013-09-18 | 格罗方德半导体公司 | Methods of making jogged layout routings double patterning compliant |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7475379B2 (en) * | 2004-06-23 | 2009-01-06 | International Business Machines Corporation | Methods and systems for layout and routing using alternating aperture phase shift masks |
US8826511B2 (en) * | 2011-11-15 | 2014-09-09 | Omnivision Technologies, Inc. | Spacer wafer for wafer-level camera and method of manufacturing same |
-
2014
- 2014-01-13 CN CN201410014615.XA patent/CN104778288B/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101178744A (en) * | 2006-11-06 | 2008-05-14 | 茂德科技股份有限公司(新加坡子公司) | Methods of automatically generating dummy fill having reduced storage size |
CN103035627A (en) * | 2011-10-05 | 2013-04-10 | 钜景科技股份有限公司 | Stack type semiconductor packaging structure |
CN103311102A (en) * | 2012-03-13 | 2013-09-18 | 格罗方德半导体公司 | Methods of making jogged layout routings double patterning compliant |
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