CN104733537B - Thin film transistor (TFT) and manufacturing method and its organic LED display device - Google Patents

Abstract

The invention provides a thin film transistor and its manufacturing method and its organic light emitting diode display device, comprising a first semiconductor layer, a second semiconductor layer deposited on the first semiconductor layer, a gate insulating layer on the second semiconductor layer, and a a gate metal layer above the gate insulating layer, the second semiconductor layer forms a source region, a drain region and a channel region between the source region and the drain region, and the first semiconductor layer is located in the source region or the drain region region, and extending out of the covering of the second semiconductor layer to form a body contact region, which can form an electrical connection with the source region or the gate metal layer. Such setting can effectively suppress the floating body effect.

Description

Thin film transistor and manufacturing method and organic light emitting diode display device thereof

technical field

The invention relates to the field of display technology, in particular to a thin film transistor, a manufacturing method and an organic light emitting diode display device thereof.

Background technique

Organic light-emitting diode (OLED) display device is an active light-emitting device. Compared with the current mainstream flat-panel display technology thin-film transistor liquid crystal display (TFT-LCD), OLED has the advantages of high contrast, wide viewing angle, low power consumption, and thinner volume. , is expected to become the next-generation flat panel display technology after LCD, and is one of the most concerned technologies in flat panel display technology, especially suitable for large-sized active matrix organic light emitting diode (Active Matrix OLED, AMOLED) display devices. Polycrystalline silicon (poly-Si) with higher mobility is widely used as thin film transistors due to the large demand for driving current in OLEDs and the low field-effect mobility of traditional amorphous silicon (a-Si) semiconductors. the semiconductor layer.

The neutral body region under the channel of the polysilicon (poly-Si) thin film transistor (TFT) used on the array substrate of the AMOLED display device is usually in an electrically floating state, which will produce a floating body effect (floating body effect), This leads to deterioration of TFT characteristics and affects the display effect of AMOLED.

In order to solve this problem, a body contact structure is a widely used method. T-shaped gate and H-shaped gate structures are commonly used, and a separate extended body contact region connected to the gate electrode is formed in the semiconductor layer. However, this technology will increase the area of thin film transistors, and the floating body effect cannot be effectively suppressed due to the existence of polysilicon (poly-Si) body resistance, and the wider the channel, the greater the body polysilicon (poly-Si) resistance, and the more significant the floating body effect .

Therefore, in view of the above problems, it is necessary to design an improved thin film transistor and its manufacturing method and its organic light emitting diode display device to overcome the above defects.

Contents of the invention

The object of the present invention is to provide a thin film transistor capable of effectively suppressing the floating body effect, a manufacturing method and an organic light emitting diode display device thereof.

To achieve the aforementioned object, the present invention adopts the following technical solutions:

A thin film transistor, comprising a first semiconductor layer, a second semiconductor layer partially overlapped with the first semiconductor layer, a gate insulating layer above the second semiconductor layer, and a gate metal layer above the gate insulating layer, the The second semiconductor layer forms a source region, a drain region, and a channel region between the source region and the drain region, and the first semiconductor layer is located below the source region or the drain region and extends out of the second semiconductor layer. Covering forms a body contact region, which can form an electrical connection with the source region or the gate metal layer.

As a further optimization, the first semiconductor layer is located under the source region, an interlayer insulating layer is formed on the gate metal layer, and the interlayer insulating layer covers the gate insulating layer at the same time, so The interlayer insulating layer is provided with contact holes respectively corresponding to the source region and the drain region, and a second metal layer filled in the contact holes and electrically connected to the source region and the drain region respectively.

As a further optimization, the body contact region is electrically connected to the source region through the second metal layer in the contact hole shared with the source region.

As a further optimization, an individual contact hole corresponding to the position of the body contact region and a second metal layer filled in the individual contact hole and electrically connected to the body contact region are provided on the interlayer insulating layer. The contact region is electrically connected to the gate metal layer through the second metal layer in the individual contact hole.

The present invention also can adopt following technical scheme:

A method for manufacturing a thin film transistor, comprising the steps of:

forming a first semiconductor layer;

Forming a second semiconductor layer on the first semiconductor layer and partially exposing the first semiconductor layer to form a body contact region, the second semiconductor layer includes a source region, a drain region, and a region between the source region and the drain region. The channel region, the source region is located above the body contact region, the body contact region extends along the length direction of the channel region, and the body contact region can form an electrical connection with the source region;

forming a gate insulating layer on the second semiconductor layer;

A gate metal layer is formed on a part of the gate insulating layer.

As a further optimization, the method also includes the following steps:

An interlayer insulating layer is formed on the gate metal layer, and the interlayer insulating layer covers the gate insulating layer at the same time, and the interlayer insulating layer respectively corresponding to the position of the source region and the drain region is arranged on the interlayer insulating layer. contact holes;

A second metal layer is further formed on the interlayer insulating layer, the second metal layer enters the contact hole and forms a source electrode and a drain electrode, and the body contact region extends along the length direction of the channel region.

As a further optimization, the body contact region is electrically connected to the source region through the second metal layer in the contact hole shared with the source region.

The present invention also can adopt following technical scheme:

An organic light emitting diode display device, comprising:

a first semiconductor layer;

A second semiconductor layer, the second semiconductor layer is arranged on the first semiconductor layer, and partially exposes the first semiconductor layer to form a body contact region, the second semiconductor layer includes a source region, a drain region, and a a channel region between a source region and a drain region, the source region being located above a body contact region, the body contact region being electrically connected to the source region;

a gate insulating layer disposed on the second semiconductor layer;

a gate metal layer arranged on the gate insulating layer;

a source electrode and a drain electrode, the source electrode and the drain electrode are respectively electrically connected to the source region and the drain region;

a first pixel electrode connected to one of the source electrode or the drain electrode;

an organic light emitting diode layer, the organic light emitting diode layer being arranged on the first pixel electrode;

The second pixel electrode is arranged on the organic light emitting diode layer.

As a further optimization, an interlayer insulating layer is also provided on the gate metal layer, and the interlayer insulating layer covers the gate insulating layer at the same time, and the interlayer insulating layer is respectively provided with the A contact hole corresponding to the source region and the drain region and a second metal layer filled in the contact hole and electrically connected to the source region and the drain region respectively.

As a further optimization, the body contact region is electrically connected to the source region through the second metal layer in the contact hole shared with the source region.

In the present invention, the first and second semiconductor layers are arranged on the thin film transistor, and a body contact structure is formed along the channel length direction, which can improve the electrical characteristics of the TFT, avoid the influence of poly-Si body resistance, and effectively The floating body effect is suppressed without significantly increasing the area of the TFT.

Description of drawings

Fig. 1 A is the plan view of the first step of the method for manufacturing TFT of the present invention;

Fig. 1 B is a sectional view taken along line I-I of Fig. 1A;

Fig. 2A is the plan view of the second step of the method for manufacturing TFT of the present invention;

Figure 2B is a sectional view taken along line II-II of Figure 2A;

Fig. 3 A is the plan view of the third step of the method for manufacturing TFT of the present invention;

Figure 3B is a cross-sectional view taken along line III-III of Figure 3A;

Fig. 4A is the plan view of the fourth step of the method for manufacturing TFT of the present invention;

Figure 4B is a sectional view taken along line IV-IV of Figure 4A;

Fig. 5 A is the plan view of the fifth step of the method for manufacturing TFT of the present invention;

Figure 5B is a cross-sectional view taken along the line V-V of Figure 5A;

FIG. 6 is a cross-sectional view of an OLED display device of the present invention.

Detailed ways

1A is a plan view illustrating a first step of a method of manufacturing a TFT according to an exemplary embodiment of the present invention, and FIG. 1B is a cross-sectional view taken along line I-I of FIG. 1A. 1A and 1B, a substrate 1 is provided, the substrate 1 is formed of glass or plastic, and a buffer layer 2 is formed on the substrate 1, and the buffer layer 2 is formed on the substrate 1 by chemical vapor deposition (CVD). The function of the buffer layer 2 is to prevent moisture or impurities in the substrate from diffusing into the semiconductor layer, or to control heat transfer efficiency during crystallization to make crystallization of the semiconductor layer easier, which will be formed in the following process. The buffer layer 2 can be a single layer, or can be composed of multi-layer films.

Subsequently, a first amorphous silicon layer is formed on the buffer layer 2 . Here, it can be formed by chemical vapor deposition (CVD), and impurity ions are doped during the deposition process, and the impurity concentration is preferably above the order of 1×10 ¹⁹ /cm ³ . Then the first amorphous silicon layer was patterned, thereby forming the first semiconductor layer 3 of 1×10 ¹⁹ /cm ³ . The thickness of the first semiconductor layer 3 is preferably between 50 nm and 100 nm.

2A is a plan view illustrating a second step of a method of manufacturing a TFT according to an exemplary embodiment of the present invention, and FIG. 2B is a cross-sectional view taken along line II-II of FIG. 2A. The second amorphous silicon layer is formed by chemical vapor deposition (CVD), preferably with a thickness between 50nm and 100nm. Here, the amorphous silicon can be dehydrogenated after it is formed to reduce the content of hydrogen atoms in the amorphous silicon film. The second amorphous silicon layer is then crystallized to convert it into a polysilicon layer. Crystallization methods include, but are not limited to, metal-induced crystallization (MIC), metal-induced lateral crystallization (MILC), supergrain silicon (SGS, Super GrainedSilicon) or excimer laser annealing (ELA, Excimer Laser Anneal) crystallization, etc. MIC is a method of inducing a phase transition from an amorphous silicon layer to a polysilicon layer by contacting a metal catalyst such as nickel, palladium or aluminum or by implanting a metal catalyst in the amorphous silicon layer. MI LC is a method of inducing the continuous crystallization of an amorphous silicon layer into a polysilicon layer through the lateral diffusion of silicide produced in the reaction of a metal catalyst with silicon. SGS is a method of layering amorphous silicon to have a large sized grain polysilicon layer method. ELA crystallization is a method of using high temperature generated by laser to rearrange silicon atoms after melting amorphous silicon to form polysilicon. The polysilicon formed by ELA crystallization has high mobility, which is a commonly used method at present. Polysilicon grains of different sizes can be formed by controlling the energy of the laser.

Next, the second semiconductor layer 4 is formed by patterning the polysilicon layer. The pattern of the second semiconductor layer 4 needs to partially expose the first semiconductor layer 3 to form an electrical connection of the body contact region 31 through a subsequent process. That is, the second semiconductor layer 4 is deposited partially overlapping with the first semiconductor layer 3 . Thereafter, impurities can be doped into the second semiconductor layer 4 to adjust the electrical characteristics of the TFT to meet design requirements. Doping can be achieved by means of ion implant or ion doping. The impurity ions can be N-type (such as P, As) or P-type (such as B, BF3), and the impurity concentration is about It is on the order of 1×10 ¹⁹ /cm ³ .

3A is a plan view illustrating a third step of a method of manufacturing a TFT according to an exemplary embodiment of the present invention, and FIG. 3B is a cross-sectional view taken along line III-III of FIG. 3A. The gate insulating layer 5 is formed on the substrate 1 and covers the entire surface of the substrate 1 . The gate insulating layer 5 may be formed of silicon dioxide or other insulating materials. A gate metal layer 6 is further formed on the gate insulating layer 5 . The gate metal layer 6 can be formed by physical vapor deposition (PVD), and the material can be aluminum (Al), molybdenum (Mo) or other metals or alloys. The gate metal layer 6 can be a single layer, or a stack of multiple layers of materials. The gate metal layer 6 is patterned by photolithography and etching, thereby forming gate electrodes, wires and other functional patterns. Then, the gate metal pattern can be used as a hard mask to form a source region 41, a drain region 42, and a channel region between the source region 41 and the drain region 42 in the second semiconductor layer 4 by ion doping or ion implantation. (not numbered). The connection line between the source region 41 and the drain region 42 is the width direction of the channel region, and the direction perpendicular to the connection line between the source region 41 and the drain region 42 is the length direction of the channel region. The first semiconductor layer 3 is located under the source region 41 or the drain region 42 and extends beyond the covering of the second semiconductor layer 4 to form a body contact region 31 . Such setting can improve the electrical characteristics of the TFT, avoid the influence of the poly-Si body resistance, and effectively suppress the floating body effect without significantly increasing the area of the TFT. In this embodiment, the body contact region 31 is located below the source region 41 . That is, the first semiconductor layer 3 and the second semiconductor layer 4 are partially overlapped and deposited at the location of the source region 41. In other implementation manners, the body contact region 31 formed by the first semiconductor layer 3 may also be located below the drain region 42, And extend the coverage of the second semiconductor layer 4 . Through the corresponding structural design, for example, an electrical connection is formed between the body contact region 31 and the gate metal layer 6, which can also avoid the influence of poly-Si body resistance, effectively suppress the floating body effect, and at the same time not significantly increase the area of the TFT. . The ion concentration doped in the source region 41 and the drain region 42 can be appropriately lower than the impurity concentration in the body contact region 31, and the impurity ions doped in the source region 41 and the drain region 42 are mixed with the first semiconductor layer 3 during the deposition process. There are different types of impurity ions. Specifically, the first semiconductor layer 3 extends along the length direction of the channel region, the first semiconductor layer 3 is located below the source region 41 or the drain region 42 and is away from the channel region along the width direction of the channel region. The covering of the second semiconductor layer 4 extends. In this way, the body contact region 31 can extend along the length direction of the channel region. Compared with extending the body contact region 31 along the width direction of the channel region, it can better improve the electrical characteristics of the TFT and avoid poly-Si body Resistive influence, suppress floating body effect, and will not significantly increase the area of TFT at the same time.

4A is a plan view illustrating a fourth step of a method of manufacturing a TFT according to an exemplary embodiment of the present invention, and FIG. 4B is a cross-sectional view taken along line IV-IV of FIG. 4A. An interlayer insulating layer 7 is further formed on the substrate 1, and the interlayer insulating layer 7 may be composed of silicon dioxide or other insulating materials. Through photolithography and etching process, the contact hole 70 is formed at a predetermined position in the interlayer insulating layer 7, thereby exposing the electrode area of TFT or other functional elements, so as to form an electrical connection to the outside. In addition, in order to reduce defects at the interface between the second semiconductor layer 4 and the gate insulating layer 5, the substrate may be subjected to high-temperature annealing (anneal) treatment. The annealing temperature is between 400°C and 600°C, and the time can be 30 minutes or longer.

5A is a plan view illustrating a fifth step of a method of manufacturing a TFT according to an exemplary embodiment of the present invention, and FIG. 5B is a cross-sectional view taken along line V-V of FIG. 5A. A second metal layer 8 is further formed on the substrate 1, and the material of the second metal layer 8 may be (Al), molybdenum (Mo) or other metals or alloys. The second metal layer 8 can be a single layer, or a stack of multiple layers of materials. Then, the second metal layer 8 is patterned by photolithography and etching process, and the second metal layer 8 is filled into the contact hole to form a source electrode and a drain electrode respectively connected to the source region 41 and the drain region 42 . In addition, the body contact region 31 can be electrically connected to the source region 41 through the common contact hole 70 and the second metal layer 8 to be filled therein. In other implementation manners, the second metal layer 8 may also be electrically connected to the gate electrode through a separate contact hole (not shown) that does not communicate with the contact hole 70 . That is, the interlayer insulating layer 7 is provided with an individual contact hole corresponding to the body contact region 31 and a second metal layer 8 filled in the individual contact hole and electrically connected to the body contact region 31. The contact region 31 is electrically connected to the gate metal layer 6 through the second metal layer 8 in the individual contact hole. 6 is a cross-sectional view of an organic light emitting diode (OLED) display device having the above TFT according to an exemplary embodiment of the present invention. Referring to FIG. 6 , a planarization layer 91 is formed on the substrate 1 having the TFT in FIG. 5 . A via hole 911 is formed in the planarization layer 91 to expose one of the source electrode or the drain electrode. A first pixel electrode 92 connected to one of the source electrode and the drain electrode through a via hole 911 is formed on the planarization layer 91 . Subsequently, a pixel defining layer 93 having a surface exposing a portion of the first pixel electrode 92 is formed on the first pixel electrode 92 and exposes a portion of the first pixel electrode 92 . An organic light emitting diode layer, that is, an OLED layer 94 is formed on the exposed portion of the first pixel electrode 92, and the OLED layer 94 may further include a hole injection layer, a hole transport layer, an electron injection layer, an electron transport layer, an organic light emitting layer, etc., But not limited to this. A second pixel electrode 95 is then formed on the OLED layer 94 . This completes the OLED display device according to the exemplary embodiment of the present invention.

According to the thin film transistor, the method for manufacturing the thin film transistor and the OLED display device having the thin film transistor of the present invention, two layers of semiconductor layers, the first and the second semiconductor layer 3, 4, are formed along the channel length direction to form a The thin film transistor with the contact structure saves area compared with the traditional TFT with the body contact structure extending separately in the semiconductor layer region, and can better suppress the floating body effect.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to the preferred embodiments, any person with ordinary knowledge in the technical field will not depart from the present invention. Within the spirit and scope of the present invention, some changes and modifications can be made, so the protection scope of the present invention should be defined by the scope of claims.

Claims (10)

1. A kind of thin film transistor, it is characterized in that: comprise first semiconductor layer (3), the second semiconductor layer (4) that overlaps deposition with first semiconductor layer (3) part, be positioned at the second semiconductor layer (4) top A gate insulating layer (5) and a gate metal layer (6) located above the gate insulating layer (5), the second semiconductor layer (4) forming a source region (41), a drain region (42) and a source region (42) located at the source A channel region between the region (41) and the drain region (42), the first semiconductor layer (3) is located below the source region (41) or the drain region (42), and extends out of the second semiconductor layer The covering of (4) forms a body contact region (31), which can form an electrical connection with the source region (41) or the gate metal layer (6). 2. The thin film transistor according to claim 1, characterized in that: the first semiconductor layer (3) is located below the source region (41), and an interlayer insulating layer is formed on the gate metal layer (6) layer (7), the interlayer insulating layer (7) covers the gate insulating layer (5) at the same time, and the interlayer insulating layer (7) is respectively provided with the source region (41) and the A contact hole (70) corresponding to the drain region (42) and a second metal layer (8) filled in the contact hole (70) and electrically connected to the source region (41) and the drain region (42) respectively. 3. The thin film transistor according to claim 2, characterized in that: the body contact region (31) is connected to the source region through the second metal layer (8) in the contact hole (70) shared with the source region (41). (41) Forming an electrical connection. 4. The thin film transistor according to claim 2, characterized in that: the interlayer insulating layer (7) is provided with a separate contact hole corresponding to the position of the body contact region (31) and filled in the separate contact hole A second metal layer (8) electrically connected to the body contact region (31) in the hole, and the body contact region (31) is connected to the gate metal layer (6) through the second metal layer (8) in the separate contact hole ) electrical connection. 5. A method for manufacturing a thin film transistor, characterized in that: comprising the steps of: forming a first semiconductor layer (3); Forming a second semiconductor layer (4) on the first semiconductor layer (3), and partially exposing the first semiconductor layer (3) to form a body contact region (31), the second semiconductor layer (4) including a source region (41), a drain region (42) and a channel region between the source region (41) and the drain region (42), the source region (41) is located above the body contact region (31), the The body contact region (31) can form an electrical connection with the source region (41); forming a gate insulating layer (5) on the second semiconductor layer (4); A gate metal layer (6) is formed on a part of the gate insulating layer (5). 6. The manufacturing method of a thin film transistor according to claim 5, characterized in that: said method further comprises the following steps: An interlayer insulating layer (7) is formed on the gate metal layer (6), and the interlayer insulating layer (7) covers the gate insulating layer (5) at the same time, and the interlayer insulating layer (7) ) are provided with contact holes (70) respectively corresponding to the positions of the source region (41) and the drain region (42); A second metal layer (8) is further formed on the interlayer insulating layer (7), the second metal layer (8) enters the contact hole (70) and forms a source electrode and a drain electrode, and the body contact region (31) extending along the length direction of the channel region. 7. The manufacturing method of a thin film transistor according to claim 6, characterized in that: the body contact region (31) passes through the second metal layer (8) in the contact hole (70) shared with the source region (41) An electrical connection is made to the source region (41). 8. An organic light emitting diode display device, characterized in that it comprises: A first semiconductor layer (3) deposited integrally in sheet form; A second semiconductor layer (4), the second semiconductor layer (4) is partially deposited on the first semiconductor layer (3), and partially exposes the first semiconductor layer (3) to form a body contact region (31 ), the second semiconductor layer (4) includes a source region (41), a drain region (42) and a channel region between the source region (41) and the drain region (42), the source region (41) located above a body contact region (31) capable of forming an electrical connection with a source region (41); a gate insulating layer (5), arranged on the second semiconductor layer (4); a gate metal layer (6), arranged on the gate insulating layer (5); a source electrode and a drain electrode, the source electrode and the drain electrode are respectively electrically connected to the source region (41) and the drain region (42); a first pixel electrode (92), the first pixel electrode (92) being connected to one of the source electrode or the drain electrode; an organic light emitting diode layer (94), the organic light emitting diode layer (94) being arranged on the first pixel electrode (92); The second pixel electrode (95) is arranged on the organic light emitting diode layer (94). 9. The organic light emitting diode display device according to claim 8, characterized in that: the gate metal layer (6) is also provided with an interlayer insulating layer (7), and the interlayer insulating layer (7) is simultaneously Covering the gate insulating layer (5), the interlayer insulating layer (7) is provided with contact holes (70) respectively corresponding to the source region (41) and the drain region (42) and filled in The second metal layer (8) in the contact hole (70) is electrically connected with the source region (41) and the drain region (42) respectively. 10. The organic light emitting diode display device according to claim 9, characterized in that: the body contact region (31) passes through the second metal layer (8) in the contact hole (70) shared with the source region (41) An electrical connection is made to the source region (41).