CN104716201A - Thin film transistor and production method of thin film transistor, array substrate and display equipment - Google Patents
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- 239000000758 substrate Substances 0.000 title claims abstract description 76
- 239000010409 thin film Substances 0.000 title claims abstract description 42
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 25
- 238000000034 method Methods 0.000 claims abstract description 22
- 238000012545 processing Methods 0.000 claims abstract description 10
- 238000009832 plasma treatment Methods 0.000 claims description 42
- 238000011282 treatment Methods 0.000 claims description 16
- 239000010949 copper Substances 0.000 claims description 11
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 9
- 238000002161 passivation Methods 0.000 claims description 9
- 229910052802 copper Inorganic materials 0.000 claims description 8
- 229910001873 dinitrogen Inorganic materials 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 3
- 238000009413 insulation Methods 0.000 abstract 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000010408 film Substances 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 230000008961 swelling Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 229910004205 SiNX Inorganic materials 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
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Abstract
Description
技术领域technical field
本发明涉及显示器技术领域，尤其涉及一种薄膜晶体管及其制作方法、阵列基板、显示设备。The invention relates to the technical field of displays, in particular to a thin film transistor, a manufacturing method thereof, an array substrate, and a display device.
背景技术Background technique
在显示器件的生产中，薄膜晶体管(Thin-film Transistor，TFT)起到具有十分重要的作用，主要利用薄膜晶体管的开态对显示器件的像素电容快速充电，利用薄膜晶体管的关态来保持像素电容的电压，从而实现快速响应和良好存储的统一。薄膜晶体管由于具有非常高的开态电流(Ion)和关态电流(Ioff)之比和陡峭的转移特性，因而作为非线性开关元件被广泛地应用于大面积液晶显示器以及接触型图像传感器等领域。In the production of display devices, thin-film transistors (Thin-film Transistor, TFT) play a very important role, mainly using the on-state of the thin-film transistor to quickly charge the pixel capacitance of the display device, and using the off-state of the thin-film transistor to maintain the pixel Capacitor voltage, which achieves unity of fast response and good storage. Thin film transistors are widely used as nonlinear switching elements in large-area liquid crystal displays and contact image sensors due to their very high ratio of on-state current (Ion) to off-state current (Ioff) and steep transfer characteristics. .
目前常规底栅反堆栈型非晶硅薄膜晶体管的具体结构如图1所示，包括：衬底基板01，以及设置在衬底基板01上的栅极02、设置在栅极02上且与栅极02绝缘的有源层03、相对而置且分别与有源层03电性连接的源极04和漏极05，当通过安装在衬底基板01中的电路将电流施加到栅极02时，加载到源极04的电流通过有源层03传输到漏极05，驱动显示器件的像素单元，从而显示图像。栅极02与有源层03之间设置有栅绝缘层06，在源极04和漏极05之上设置有钝化层07，其中，栅绝缘层06通常采用a-SiNx薄膜，有源层03通常采用a-Si:H薄膜，钝化层07通常采用a-SiNx薄膜，栅极02、源极04和漏极05通常采用金属材料，例如铜(Cu)。为了改善源极04、漏极05与a-Si:H薄膜的接触特性，在其间插入了薄的n+型a-Si:H薄膜作为欧姆接触层08。The specific structure of the current conventional bottom-gate anti-stacked amorphous silicon thin film transistor is shown in Figure 1, including: a substrate 01, a gate 02 arranged on the substrate 01, and a The active layer 03 that is insulated from the pole 02, the source 04 and the drain 05 that are opposite and electrically connected to the active layer 03, when the current is applied to the gate 02 through the circuit installed in the base substrate 01 , the current loaded to the source 04 is transferred to the drain 05 through the active layer 03 to drive the pixel units of the display device, thereby displaying images. A gate insulating layer 06 is arranged between the gate 02 and the active layer 03, and a passivation layer 07 is arranged on the source 04 and the drain 05, wherein the gate insulating layer 06 is usually made of a-SiNx film, and the active layer 03 usually uses a-Si:H thin film, passivation layer 07 usually uses a-SiNx thin film, gate 02, source 04 and drain 05 usually use metal materials, such as copper (Cu). In order to improve the contact characteristics between the source 04 , the drain 05 and the a-Si:H film, a thin n+ type a-Si:H film is inserted between them as the ohmic contact layer 08 .
如今高分辨率及高画质的平板显示装置普遍受人们青睐。图像信号的延迟成为制约高分辨率及高画质平板显示装置的关键因素之一。然而，图像信号的延迟主要由阵列基板上的栅极和栅极线决定的信号电阻和相关电容决定。目前采用电阻较低的金属Cu制作栅极和栅极线，从而实现降低栅极和栅极线的电阻。但是，在栅绝缘层高温沉积的制作环境中，铜导线极其容易形成鼓包，造成铜导线的电阻存在差异。从而，在栅极扫描线打开时，像素充电，由于栅极扫描线的电阻存在差异，某些像素充电不充分，导致图像显示画面的亮度不均匀，严重影响图像的显示质量。此外，由于栅绝缘层存在膜层脱落的特性，一般采用较长的预热(pre heat)时间并通过氮气等离子化(N2Plasma)处理改善栅绝缘层的这一特性。然而，较长时间的预热以及氮气等离子化处理均将加重铜导线鼓包的问题。Nowadays, flat panel display devices with high resolution and high image quality are generally favored by people. Image signal delay becomes one of the key factors restricting high resolution and high image quality flat panel display devices. However, the delay of the image signal is mainly determined by the signal resistance and related capacitance determined by the gate and gate lines on the array substrate. At present, metal Cu with low resistance is used to make the gate and the gate lines, so as to reduce the resistance of the gate and the gate lines. However, in the manufacturing environment where the gate insulating layer is deposited at high temperature, the copper wires are extremely easy to form bulges, resulting in differences in the resistance of the copper wires. Therefore, when the gate scanning lines are turned on, the pixels are charged, and due to the difference in the resistance of the gate scanning lines, some pixels are not fully charged, resulting in uneven brightness of the image display screen, which seriously affects the display quality of the image. In addition, because the gate insulating layer has the property of film peeling, generally a longer preheat time is adopted and nitrogen plasma (N2Plasma) treatment is used to improve this property of the gate insulating layer. However, longer preheating and nitrogen plasma treatment will aggravate the problem of copper wire bulging.
其中，N2Plasma处理具体指在栅绝缘层(GI)沉积之前，采用预设功率(power)激发氮气(N2)形成等离子体轰击Cu和基板表面，改善GI沉积表面特性，N2plasma处理是一种通过等离子体处理膜面的工艺手段。Among them, N2Plasma treatment specifically refers to the use of preset power (power) to excite nitrogen gas (N2) before the deposition of the gate insulating layer (GI) to form plasma bombardment of Cu and the surface of the substrate to improve the surface characteristics of GI deposition. The process means of bulk treatment of membrane surface.
综上所述，现有技术在生产薄膜晶体管的过程中，容易出现栅极线鼓包的问题，使得栅极线的电阻不均匀，进而导致显示器显示不均匀，显示器的显示品质差。To sum up, in the prior art, in the process of producing thin film transistors, the problem of bulging gate lines is prone to occur, which makes the resistance of the gate lines uneven, which in turn leads to uneven display of the display and poor display quality of the display.
发明内容Contents of the invention
本发明实施例提供了一种薄膜晶体管及其制作方法、阵列基板、显示设备，用以减缓甚至避免薄膜晶体管的制作过程出现的栅极线鼓包的问题，使得栅极线的电阻均匀，进而使得显示器显示均匀，提高显示器的显示品质。Embodiments of the present invention provide a thin film transistor and its manufacturing method, an array substrate, and a display device, which are used to slow down or even avoid the problem of gate line bulging in the manufacturing process of the thin film transistor, so that the resistance of the gate line is uniform, and thus the The display is uniform, and the display quality of the display is improved.
本发明实施例提供的一种薄膜晶体管的制作方法包括：A method for manufacturing a thin film transistor provided in an embodiment of the present invention includes:
在衬底基板上形成栅极线；forming gate lines on the base substrate;
对形成有栅极线的衬底基板进行用于减缓栅极线鼓包的处理，并在处理后的衬底基板上形成栅绝缘层。The base substrate formed with the gate lines is treated for alleviating the bulging of the gate lines, and a gate insulating layer is formed on the treated base substrate.
通过该方法，对形成有栅极线的衬底基板进行用于减缓栅极线鼓包的处理，并在处理后的衬底基板上形成栅绝缘层，减缓甚至避免薄膜晶体管的制作过程出现的栅极线鼓包的问题，使得栅极线的电阻均匀，进而使得显示器显示均匀，提高显示器的显示品质。Through this method, the base substrate formed with the gate lines is treated to reduce the bulging of the gate lines, and a gate insulating layer is formed on the treated base substrate, so as to slow down or even avoid the gate line bulging in the manufacturing process of the thin film transistor. The problem of bulging pole lines makes the resistance of the gate lines uniform, thereby making the display uniform and improving the display quality of the display.
较佳地，该方法还包括：Preferably, the method also includes:
在形成有所述栅绝缘层的衬底基板上，分别形成有源层、源极、漏极、钝化层、公共电极以及像素电极。An active layer, a source electrode, a drain electrode, a passivation layer, a common electrode and a pixel electrode are respectively formed on the base substrate on which the gate insulating layer is formed.
较佳地，对形成有栅极线的衬底基板进行用于减缓栅极线鼓包的处理，并在处理后的衬底基板上形成栅绝缘层，具体包括：Preferably, the base substrate formed with the gate lines is treated to reduce the bulging of the gate lines, and a gate insulating layer is formed on the processed base substrate, which specifically includes:
在形成有栅极线的衬底基板上直接形成栅绝缘层；或者，directly forming a gate insulating layer on the base substrate on which the gate line is formed; or,
利用预设的等离子处理功率对所述栅极线进行等离子处理，并在等离子处理处理后的形成有栅极线的衬底基板上形成栅绝缘层，其中，所述预设的等离子处理功率小于8千瓦；或者，Perform plasma treatment on the gate line with a preset plasma treatment power, and form a gate insulating layer on the base substrate on which the gate line is formed after the plasma treatment, wherein the preset plasma treatment power is less than 8 kW; or,
按照预设的预热时间，对形成有栅极线的衬底基板进行预热处理，并在预热处理后的形成有栅极线的衬底基板上形成栅绝缘层，其中，所述预设的预热时间小于60秒；或者，According to the preset preheating time, preheating is performed on the base substrate formed with the gate lines, and a gate insulating layer is formed on the preheated base substrate formed with the gate lines, wherein the preheating Set the warm-up time to less than 60 seconds; or,
按照预设的预热时间对形成有栅极线的衬底基板进行预热处理，并且，利用预设的等离子处理功率对所述栅极线进行等离子处理，在所述预热处理后以及所述等离子处理后的形成有栅极线的衬底基板上形成栅绝缘层，其中，所述预设的等离子处理功率小于8千瓦，和/或，所述预设的预热时间小于60秒。Perform preheating treatment on the base substrate on which the gate lines are formed according to a preset preheating time, and perform plasma treatment on the gate lines with a preset plasma processing power, after the preheating treatment and the A gate insulating layer is formed on the base substrate on which the gate lines are formed after the plasma treatment, wherein the preset plasma processing power is less than 8 kW, and/or the preset preheating time is less than 60 seconds.
较佳地，所述预热时间大于或等于10秒，且小于或等于20秒。Preferably, the preheating time is greater than or equal to 10 seconds and less than or equal to 20 seconds.
较佳地，所述预设的等离子处理功率大于或等于5千瓦，且小于或等于7千瓦。Preferably, the preset plasma processing power is greater than or equal to 5 kilowatts and less than or equal to 7 kilowatts.
较佳地，对所述栅极线进行等离子处理，具体为采用氮气对所述栅极线进行等离子处理。Preferably, plasma treatment is performed on the gate lines, specifically, nitrogen gas is used to perform plasma treatment on the gate lines.
较佳地，所述的栅极线的材料包括铜。Preferably, the material of the gate line includes copper.
本发明实施例提供的一种薄膜晶体管，该薄膜晶体管是采用本发明实施例提供的所述的方法制成的薄膜晶体管。An embodiment of the present invention provides a thin film transistor, which is manufactured by using the method provided in the embodiment of the present invention.
本发明实施例提供的一种阵列基板，包括本发明实施例提供的所述的薄膜晶体管。An array substrate provided in an embodiment of the present invention includes the thin film transistor provided in the embodiment of the present invention.
本发明实施例提供的一种显示设备，包括本发明实施例提供的所述的阵列基板。A display device provided in an embodiment of the present invention includes the array substrate provided in the embodiment of the present invention.
附图说明Description of drawings
图1为现有底栅反堆栈型非晶硅薄膜晶体管结构示意图；FIG. 1 is a schematic structural diagram of an existing bottom-gate anti-stacked amorphous silicon thin film transistor;
图2为本发明实施例提供的一种薄膜晶体管的制作方法的总体流程示意图；FIG. 2 is a schematic overall flow diagram of a manufacturing method of a thin film transistor provided by an embodiment of the present invention;
图3为本发明实施例提供的第一种薄膜晶体管的制作方法的具体流程示意图；FIG. 3 is a schematic flow chart of the first manufacturing method of the thin film transistor provided by the embodiment of the present invention;
图4为本发明实施例提供的第二种薄膜晶体管的制作方法的具体流程示意图；FIG. 4 is a schematic flow chart of a second manufacturing method of a thin film transistor provided by an embodiment of the present invention;
图5为本发明实施例提供的第三种薄膜晶体管的制作方法的具体流程示意图；FIG. 5 is a schematic flow chart of a third manufacturing method of a thin film transistor provided by an embodiment of the present invention;
图6为本发明实施例提供的第四种薄膜晶体管的制作方法的具体流程示意图。FIG. 6 is a schematic flowchart of a fourth manufacturing method of a thin film transistor provided by an embodiment of the present invention.
具体实施方式Detailed ways
本发明实施例提供了一种薄膜晶体管及其制作方法、阵列基板、显示设备，用以减缓甚至避免薄膜晶体管的制作过程出现的栅极线鼓包的问题，使得栅极线的电阻均匀，进而使得显示器显示均匀，提高显示器的显示品质。Embodiments of the present invention provide a thin film transistor and its manufacturing method, an array substrate, and a display device, which are used to slow down or even avoid the problem of gate line bulging in the manufacturing process of the thin film transistor, so that the resistance of the gate line is uniform, and thus the The display is uniform, and the display quality of the display is improved.
参见图2，本发明实施例提供的一种薄膜晶体管的制作方法包括步骤：Referring to FIG. 2, a method for manufacturing a thin film transistor provided by an embodiment of the present invention includes steps:
S101、在衬底基板上形成栅极线；S101, forming a gate line on a base substrate;
S102、对形成有栅极线的衬底基板进行用于减缓栅极线鼓包的处理，并在处理后的衬底基板上形成栅绝缘层。S102 , performing treatment on the base substrate on which the gate lines are formed to reduce swelling of the gate lines, and forming a gate insulating layer on the treated base substrate.
通过该方法，对形成有栅极线的衬底基板进行用于减缓栅极线鼓包的处理，并在处理后的衬底基板上形成栅绝缘层，减缓甚至避免薄膜晶体管的制作过程出现的栅极线鼓包的问题，使得栅极线的电阻均匀，进而使得显示器显示均匀，提高显示器的显示品质。Through this method, the base substrate formed with the gate lines is treated to reduce the bulging of the gate lines, and a gate insulating layer is formed on the treated base substrate, so as to slow down or even avoid the gate line bulging in the manufacturing process of the thin film transistor. The problem of bulging pole lines makes the resistance of the gate lines uniform, thereby making the display uniform and improving the display quality of the display.
较佳地，该方法还包括：Preferably, the method also includes:
在形成有所述栅绝缘层的衬底基板上，分别形成有源层、源极、漏极、钝化层、公共电极以及像素电极。An active layer, a source electrode, a drain electrode, a passivation layer, a common electrode and a pixel electrode are respectively formed on the base substrate on which the gate insulating layer is formed.
较佳地，对形成有栅极线的衬底基板进行用于减缓栅极线鼓包的处理，并在处理后的衬底基板上形成栅绝缘层，具体包括：Preferably, the base substrate formed with the gate lines is treated to reduce the bulging of the gate lines, and a gate insulating layer is formed on the processed base substrate, which specifically includes:
在形成有栅极线的衬底基板上直接形成栅绝缘层；或者，directly forming a gate insulating layer on the base substrate on which the gate line is formed; or,
利用预设的等离子处理功率对所述栅极线进行等离子处理，并在等离子处理处理后的形成有栅极线的衬底基板上形成栅绝缘层，其中，所述预设的等离子处理功率小于8千瓦；或者，Perform plasma treatment on the gate line with a preset plasma treatment power, and form a gate insulating layer on the base substrate on which the gate line is formed after the plasma treatment, wherein the preset plasma treatment power is less than 8 kW; or,
按照预设的预热时间，对形成有栅极线的衬底基板进行预热处理，并在预热处理后的形成有栅极线的衬底基板上形成栅绝缘层，其中，所述预设的预热时间小于60秒；或者，According to the preset preheating time, preheating is performed on the base substrate formed with the gate lines, and a gate insulating layer is formed on the preheated base substrate formed with the gate lines, wherein the preheating Set the warm-up time to less than 60 seconds; or,
按照预设的预热时间对形成有栅极线的衬底基板进行预热处理，并且，利用预设的等离子处理功率对所述栅极线进行等离子处理，在所述预热处理后以及所述等离子处理后的形成有栅极线的衬底基板上形成栅绝缘层，其中，所述预设的等离子处理功率小于8千瓦，和/或，所述预设的预热时间小于60秒。Perform preheating treatment on the base substrate on which the gate lines are formed according to a preset preheating time, and perform plasma treatment on the gate lines with a preset plasma processing power, after the preheating treatment and the A gate insulating layer is formed on the base substrate on which the gate lines are formed after the plasma treatment, wherein the preset plasma processing power is less than 8 kW, and/or the preset preheating time is less than 60 seconds.
较佳地，所述预热时间大于或等于10秒，且小于或等于20秒。Preferably, the preheating time is greater than or equal to 10 seconds and less than or equal to 20 seconds.
较佳地，所述预设的等离子处理功率大于或等于5千瓦，且小于或等于7千瓦。Preferably, the preset plasma processing power is greater than or equal to 5 kilowatts and less than or equal to 7 kilowatts.
较佳地，对所述栅极线进行等离子处理，具体为采用氮气对所述栅极线进行等离子处理。Preferably, plasma treatment is performed on the gate lines, specifically, nitrogen gas is used to perform plasma treatment on the gate lines.
较佳地，所述的栅极线的材料包括铜。例如，本发明实施例中所述的栅极线可以完全是由铜制成的栅极线，也可以是由铜和其他金属组成的合金制成的栅极线，或者，也可以是由其他金属制成的栅极线，例如可以是由铬制成的栅极线。总之，涉及到容易出现鼓包的金属线，都可以适用本发明实施例提供的技术方案进行消除。Preferably, the material of the gate line includes copper. For example, the gate lines described in the embodiments of the present invention may be entirely made of copper, or may be made of an alloy composed of copper and other metals, or may be made of other metals. The gate lines made of metal, for example, may be gate lines made of chrome. In a word, the technical solutions provided by the embodiments of the present invention can be applied to eliminate the metal wires that are prone to bulging.
实施例一：Embodiment one:
参见图3，本发明实施例提供的一种薄膜晶体管的制作方法包括：Referring to FIG. 3, a manufacturing method of a thin film transistor provided by an embodiment of the present invention includes:
S201、在衬底基板上形成栅极线；S201, forming a gate line on the base substrate;
S202、在形成有栅极线的衬底基板上直接形成栅绝缘层；S202, directly forming a gate insulating layer on the base substrate on which the gate lines are formed;
本实施例在形成有栅极线的衬底基板上直接形成栅绝缘层，即省略N2plasma处理步骤，由于等离子处理为通过加热得到等离子进行轰击处理，因此略去此步骤将会很大程度的减低所述栅极线受热的温度，从而降低了栅极线受热的温度，避免栅极线鼓包。In this embodiment, the gate insulating layer is directly formed on the base substrate on which the gate line is formed, that is, the N2 plasma treatment step is omitted. Since the plasma treatment is to obtain plasma by heating for bombardment treatment, omitting this step will greatly reduce the The temperature at which the gate lines are heated reduces the temperature at which the gate lines are heated and prevents the grid lines from bulging.
S203、在形成有所述栅绝缘层的衬底基板上，分别形成有源层、源极、漏极、钝化层、公共电极以及像素电极。S203 , respectively forming an active layer, a source electrode, a drain electrode, a passivation layer, a common electrode, and a pixel electrode on the base substrate on which the gate insulating layer is formed.
实施例二：Embodiment two:
参见图4，本发明实施例提供的一种薄膜晶体管的制作方法包括：Referring to FIG. 4, a manufacturing method of a thin film transistor provided by an embodiment of the present invention includes:
S301、在衬底基板上形成栅极线；S301, forming a gate line on the base substrate;
S302、利用预设的等离子处理功率对所述栅极线进行等离子处理，并在等离子处理处理后的形成有栅极线的衬底基板上形成栅绝缘层，其中，所述预设的等离子处理功率小于8千瓦。S302. Perform plasma treatment on the gate lines with a preset plasma treatment power, and form a gate insulating layer on the base substrate on which the gate lines are formed after the plasma treatment, wherein the preset plasma treatment The power is less than 8 kW.
本实施例降低了等离子处理的功率，由于等离子处理是通过加热得到的等离子进行轰击处理，因此减低等离子处理的功率也就减低了等离子处理的温度，从而降低了栅极线受热的温度，避免栅极线鼓包。In this embodiment, the power of the plasma treatment is reduced. Since the plasma treatment is bombarded by heated plasma, reducing the power of the plasma treatment also reduces the temperature of the plasma treatment, thereby reducing the heating temperature of the grid line and avoiding the grid line. Extreme line drum kit.
S303、在形成有所述栅绝缘层的衬底基板上，分别形成有源层、源极、漏极、钝化层、公共电极以及像素电极。S303 , respectively forming an active layer, a source electrode, a drain electrode, a passivation layer, a common electrode, and a pixel electrode on the base substrate on which the gate insulating layer is formed.
实施例三：Embodiment three:
参见图5，本发明实施例提供的一种薄膜晶体管的制作方法包括：Referring to FIG. 5, a manufacturing method of a thin film transistor provided by an embodiment of the present invention includes:
S401、在衬底基板上形成栅极线；S401, forming a gate line on the base substrate;
S402、按照预设的预热时间，对形成有栅极线的衬底基板进行预热处理，并在预热处理后的形成有栅极线的衬底基板上形成栅绝缘层，其中，所述预设的预热时间小于60秒；S402. According to the preset preheating time, perform preheating treatment on the base substrate formed with the gate lines, and form a gate insulating layer on the preheated base substrate formed with the gate lines, wherein the The preset warm-up time mentioned above is less than 60 seconds;
本实施例通过减少预热时间，缩短了栅极线的受热时间，从而降低了栅极线受热的温度，避免栅极线鼓包。In this embodiment, by reducing the preheating time, the heating time of the gate lines is shortened, thereby reducing the temperature at which the gate lines are heated, and avoiding the swelling of the gate lines.
通过具体实验，可得知当预热时间在10秒与20秒的范围内时，将最大程度的减缓栅极线的鼓包问题，且减缓了栅极线的氧化程度。Through specific experiments, it can be known that when the preheating time is within the range of 10 seconds and 20 seconds, the swelling problem of the gate lines will be alleviated to the greatest extent, and the oxidation degree of the gate lines will be slowed down.
S403、在形成有所述栅绝缘层的衬底基板上，分别形成有源层、源极、漏极、钝化层、公共电极以及像素电极。S403 , respectively forming an active layer, a source electrode, a drain electrode, a passivation layer, a common electrode, and a pixel electrode on the base substrate on which the gate insulating layer is formed.
实施例四：Embodiment four:
参见图6，本发明实施例提供的一种薄膜晶体管的制作方法包括：Referring to FIG. 6, a manufacturing method of a thin film transistor provided by an embodiment of the present invention includes:
S501、在衬底基板上形成栅极线；S501, forming a gate line on the base substrate;
S502、按照预设的预热时间对形成有栅极线的衬底基板进行预热处理，并且，利用预设的等离子处理功率对所述栅极线进行等离子处理，在所述预热处理后以及所述等离子处理后的形成有栅极线的衬底基板上形成栅绝缘层，其中，所述预设的等离子处理功率小于8千瓦，和/或，所述预设的预热时间小于60秒。S502. Perform preheating treatment on the base substrate on which the gate lines are formed according to the preset preheating time, and perform plasma treatment on the gate lines with the preset plasma treatment power, after the preheating treatment And a gate insulating layer is formed on the base substrate on which the gate lines are formed after the plasma treatment, wherein the preset plasma treatment power is less than 8 kW, and/or the preset preheating time is less than 60 Second.
本步骤可以先预热后等离子处理，也可以先等离子处理后预热。In this step, plasma treatment may be performed after preheating, or preheating may be performed after plasma treatment.
本实施例中将预热和等离子处理相结合，只要其中任一处理与现有技术相比，降低了栅极线的受热温度，就可以减缓或避免栅极线鼓包。In this embodiment, preheating and plasma treatment are combined, as long as any one of the treatments lowers the heating temperature of the gate lines compared with the prior art, the bulging of the gate lines can be slowed down or avoided.
S503、在形成有所述栅绝缘层的衬底基板上，分别形成有源层、源极、漏极、钝化层、公共电极以及像素电极。S503 , respectively forming an active layer, a source electrode, a drain electrode, a passivation layer, a common electrode, and a pixel electrode on the base substrate on which the gate insulating layer is formed.
本发明实施例提供的一种薄膜晶体管，该薄膜晶体管是采用本发明实施例提供的所述的方法制成的薄膜晶体管。An embodiment of the present invention provides a thin film transistor, which is manufactured by using the method provided in the embodiment of the present invention.
本发明实施例提供的一种阵列基板，包括本发明实施例提供的所述的薄膜晶体管。An array substrate provided in an embodiment of the present invention includes the thin film transistor provided in the embodiment of the present invention.
本发明实施例提供的一种显示设备，包括本发明实施例提供的所述的阵列基板。A display device provided in an embodiment of the present invention includes the array substrate provided in the embodiment of the present invention.
综上所述，本发明实施例，对形成有栅极线的衬底基板进行用于减缓栅极线鼓包的处理，并在处理后的衬底基板上形成栅绝缘层，减缓甚至避免薄膜晶体管的制作过程出现的栅极线鼓包的问题，使得栅极线的电阻均匀，进而使得显示器显示均匀，提高显示器的显示品质。To sum up, in the embodiment of the present invention, the base substrate formed with the gate lines is treated to reduce the swelling of the gate lines, and a gate insulating layer is formed on the processed base substrate, so as to slow down or even avoid the thin film transistors. The problem of bulging of the grid lines in the manufacturing process makes the resistance of the grid lines uniform, thereby making the display uniform and improving the display quality of the display.
显然，本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention also intends to include these modifications and variations.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108598174A (en) * | 2018-05-09 | 2018-09-28 | 深圳市华星光电半导体显示技术有限公司 | The production method of array substrate |
| WO2019214413A1 (en) * | 2018-05-09 | 2019-11-14 | 深圳市华星光电半导体显示技术有限公司 | Method for manufacturing array substrate |
| CN109616418A (en) * | 2018-12-06 | 2019-04-12 | 合肥鑫晟光电科技有限公司 | Thin film transistor, display substrate, method for making the same, and display device |
| WO2020114101A1 (en) * | 2018-12-06 | 2020-06-11 | 京东方科技集团股份有限公司 | Thin film transistor, display substrate and preparation methods therefor, and display device |
| US11239264B2 (en) | 2018-12-06 | 2022-02-01 | Hefei Xinsheng Optoelectronics Technology Co., Ltd. | Thin film transistor, display substrate, method for preparing the same, and display device |
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|---|---|
| US20160293636A1 (en) | 2016-10-06 |
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