CN104715089B - Determine resistance value wiring implementation method in a kind of flat-panel monitor design - Google Patents
Determine resistance value wiring implementation method in a kind of flat-panel monitor design Download PDFInfo
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- CN104715089B CN104715089B CN201310686150.8A CN201310686150A CN104715089B CN 104715089 B CN104715089 B CN 104715089B CN 201310686150 A CN201310686150 A CN 201310686150A CN 104715089 B CN104715089 B CN 104715089B
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Abstract
The present invention, which is disclosed in a kind of flat-panel monitor design, determines resistance value wiring method.This method chooses two groups of IC ports for treating line, and provides three kinds of modes and load primary route admissible region, provides the edit to primary route admissible region polygon, to finely tune the Routing constraints range for determining resistance value wiring.Next to every turn line being linked to be in primary route admissible region polygon, inverse proportion distribution turn line length is carried out according to resistance binding occurrence.Hereafter using the geometry of a kind of real-time dynamic regulation preview line and providing calculate in real time resistance variations reach dynamic adjustment wiring effect mode line profile is finely adjusted to it is final rationally until.The target that fine tuning line profile finally wishes to reach is that the width of every line has to be larger than the minimum widith threshold value that can be set and the spacing of every adjacent two lines has to be larger than the minimum spacing threshold value that can be set；The resistance value of all lines is all necessarily less than or equal to the corresponding maximum resistance binding occurrence that can be set.
Description
Technical field
A kind of resistance value wiring implementation method of determining in flat-panel monitor design belongs in FPD (flat-panel monitor design) tool
Self routing design field.
Background technology
FPD（FPD）The mainstream for having become future television is trend of the times, but at present in the world still without tight
The definition of lattice, general this thickness of displays are relatively thin, it appears that just as a tablet, there are many type of FPD, by display
Medium and operation principle point, there is liquid crystal display（LCD）, plasma shows（PDP）, electroluminance display（ELD）, organic electroluminescence hair
Light is shown（OLED）, field emission display（FED）, Projection Display etc..
Self routing occupies very big workload in slab design, and answers different demands, and there are many plant again in practice
Different wiring methods, for example resistance wiring is waited, based on side wiring on pel array, etc..Wherein have a kind of important
Demand is exactly to determine resistance value wiring.This wiring method is used to utilize the remaining space of panel corner or connection panel periphery
The IC ends of adjacent both sides or the parallel IC ends of one group of panel periphery.Often have in the TV screen design of large-size screen monitors and determine resistance value wiring
Demand.
Invention content
In flat-panel monitor design process, the connection between the IC ports of panel periphery sides adjacent is connected, usually to not
Distribution of resistance with line requires, and to achieve the purpose that different current signals, this is just needed on panel to two groups of differences
IC ports between carry out specified resistance line.Traditional resistance value wiring of determining has method outmoded, needs a large amount of manual operation,
Inefficiency is routed to the shortcomings such as power is low.The present invention, which is disclosed in a kind of flat-panel monitor design, determines resistance value wiring method,
Wiring effect is shown in attached drawing 1.This method chooses two groups of IC ports for treating line first, and provides three kinds of modes and load primary route appearance
Perhaps attached drawing 2 is seen in region.Then edit is provided to primary route admissible region polygon, determines resistance value wiring to finely tune
Routing constraints range.Next to every turn line being linked to be in primary route admissible region polygon, (term turn line refers to
The line segment on the corresponding vertex of line primary route admissible region polygon, as shown in the dotted line in attached drawing 3.) constrained according to resistance
Value carries out inverse proportion distribution turn line length, sees attached drawing 3.Hereafter the line profile of inverse proportion distribution gained is finely adjusted to most
Until end is reasonable.But, the possibility of the point after inverse proportion distribution on connection line profile allows to have a little not necessarily on turn line
Deviate.The target that fine tuning line profile finally wishes to reach is that the width of every line has to be larger than the minimum widith threshold that can be set
Value and the spacing of every adjacent two lines have to be larger than the minimum spacing threshold value that can be set；The resistance value of all lines all must be small
In or equal to the corresponding maximum resistance binding occurrence that can set.
It simultaneously can live preview resistance variations invention additionally discloses a kind of geometry of real-time dynamic regulation preview line
Resistance table is shown in attached drawing 5 in a manner of dynamically adjusting wiring effect.It either select line profile a certain vertex or certain
On one side or then certain side of line profile pulls to adjust, while follow real-time display near cursor in form in real time
The prompting frame of current link information (including resistance information).
Disclosed by the invention to determine resistance value wiring method to primary route admissible region three kinds of modes of offer, they are：1, choosing
It selects a wiring entity and provides primary route admissible region with its profile；2, to load the primary route admissible region number preserved
It is believed that the file of breath provides primary route admissible region；3, according to two groups of port location information intelligence operations to be connected up to provide
Primary route admissible region.
Description of the drawings
Fig. 1 determines resistance value wiring effect
Fig. 2 determines resistance value wiring primary route admissible region presentation mode
Fig. 3 carries out by resistance binding occurrence inverse proportion allocated length primary route admissible region polygon turn line
The possibility of point after the distribution of Fig. 4 inverse proportions on connection line profile not necessarily on turn line, allows have a little deviation
Fig. 5 determines the dynamic regulation line shapes of resistance value wiring to change resistance effect
Specific implementation step：
Determine resistance value wiring implementation method in a kind of flat-panel monitor design, disclose a kind of FPD self routings field and determine
The method of resistance value wiring, implementation step are as follows：
1）It chooses the maximum resistance unbound document for determining resistance value wiring and loads；
2）The port figure of two groups of cablings is chosen, to carry out determining resistance value wiring between two groups of ports；
3）Any one mode that primary route admissible region is provided is chosen, imports primary route admissible region；
4）Calling determine resistance value connect up application program preview wiring effect, if bad, dynamic regulation preview line profile with
Its resistance is adjusted, until finally meeting the resistance restriction of maximum resistance unbound document；
Generate wiring：Calling determine resistance value wiring application program, a key intelligently generation finally determine resistance value wiring scheme.
Claims (7)
1. determining resistance value Wiring design method in a kind of flat-panel monitor design, include the following steps：
A) it chooses the maximum resistance unbound document for determining resistance value wiring and loads；
B) the port figure of two groups of cablings is chosen, to carry out determining resistance value wiring between two groups of ports；
C) any one mode that primary route admissible region is provided is chosen, imports primary route admissible region；
D) to primary route admissible region polygon into edlin, the Routing constraints range of resistance value wiring is determined in adjustment；To initial
The each turn line being linked to be in wiring admissible region polygon carries out inverse proportion distribution turn line length according to resistance binding occurrence；
Calling determine resistance value connect up application program preview wiring effect, if bad, dynamic regulation preview line profile to adjust its resistance,
Until finally meet the resistance restriction of maximum resistance unbound document；
The turn line refers to the line segment on the corresponding vertex of line primary route admissible region polygon；
E) generation wiring：Calling determine resistance value wiring application program, a key intelligently generation finally determine resistance value wiring scheme.
2. determine resistance value Wiring design method in flat-panel monitor design according to claim 1, which is characterized in that final
The width of every line of generation has to be larger than the minimum widith threshold value that can be set and the spacing of every adjacent two lines must be big
In the minimum spacing threshold value that can be set.
3. determine resistance value Wiring design method in flat-panel monitor design according to claim 1, which is characterized in that final
The resistance value of all lines of generation is all necessarily less than or equal to the corresponding maximum resistance binding occurrence that can be set, and all companies
Occupying for line geometry width must be scattered in certain relationship distribution with the resistance constraint that can be set.
4. determine resistance value Wiring design method in flat-panel monitor design according to claim 1, which is characterized in that provide
A kind of geometry of real-time dynamic regulation preview line and the real-time calculating resistance variations of offer reach dynamic adjustment and connect up effect
Mode；Either a certain vertex of selection line profile either selects certain one side of line profile or selects line profile
Then certain side is pulled to adjust in real time, can pop up the list of a reflection resistance variations situation near form immediately at this time,
The prompting frame of the current link information to be edited of one performance of real-time display near cursor is followed in form simultaneously.
5. determine resistance value Wiring design method in flat-panel monitor design according to claim 1, which is characterized in that described
The mode of primary route admissible region, by the way that a wiring entity is selected to provide primary route admissible region with its profile.
6. determine resistance value Wiring design method in flat-panel monitor design according to claim 1, which is characterized in that described
The mode of primary route admissible region can be provided just by loading the file of the primary route admissible region data information preserved
Begin wiring admissible region.
7. determine resistance value Wiring design method in flat-panel monitor design according to claim 1, which is characterized in that described
The mode of primary route admissible region can automatically provide initial cloth according to two groups of port location information intelligence operations to be connected up
Line admissible region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310686150.8A CN104715089B (en) | 2013-12-16 | 2013-12-16 | Determine resistance value wiring implementation method in a kind of flat-panel monitor design |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310686150.8A CN104715089B (en) | 2013-12-16 | 2013-12-16 | Determine resistance value wiring implementation method in a kind of flat-panel monitor design |
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| Publication Number | Publication Date |
|---|---|
| CN104715089A CN104715089A (en) | 2015-06-17 |
| CN104715089B true CN104715089B (en) | 2018-06-22 |
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| CN201310686150.8A Active CN104715089B (en) | 2013-12-16 | 2013-12-16 | Determine resistance value wiring implementation method in a kind of flat-panel monitor design |
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Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106844801A (en) * | 2015-12-03 | 2017-06-13 | 北京华大九天软件有限公司 | Between a kind of vertical port with port it is wide and 90 degree turn round connection wiring methods |
| CN114386356A (en) * | 2020-10-16 | 2022-04-22 | Oppo广东移动通信有限公司 | Wiring method, device, equipment and storage medium for chip design |
| CN115952761B (en) * | 2023-01-10 | 2024-07-23 | 深圳华大九天科技有限公司 | Method, device and storage medium for carrying out resistance compensation on wiring among multiple groups of parallel ports |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1622703A (en) * | 2003-11-27 | 2005-06-01 | 三星Sdi株式会社 | Flat panel display device |
| CN1963827A (en) * | 2006-12-08 | 2007-05-16 | 清华大学 | Automatic wiring method of analog integrated circuit based on multiple step length labyrinth algorithm |
| CN1983287A (en) * | 2006-04-13 | 2007-06-20 | 华为技术有限公司 | Method and device for automatically adjusting Fanout design line width |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8572523B2 (en) * | 2006-07-21 | 2013-10-29 | Synopsys, Inc. | Lithography aware leakage analysis |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1622703A (en) * | 2003-11-27 | 2005-06-01 | 三星Sdi株式会社 | Flat panel display device |
| CN1983287A (en) * | 2006-04-13 | 2007-06-20 | 华为技术有限公司 | Method and device for automatically adjusting Fanout design line width |
| CN1963827A (en) * | 2006-12-08 | 2007-05-16 | 清华大学 | Automatic wiring method of analog integrated circuit based on multiple step length labyrinth algorithm |
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| CN104715089A (en) | 2015-06-17 |
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Address after: 100102 Second Floor, Block A, No. 2, Lize Middle Road, Chaoyang District, Beijing Patentee after: Beijing Huada Jiutian Technology Co.,Ltd. Address before: 100102 Second Floor, Block A, No. 2, Lize Middle Road, Chaoyang District, Beijing Patentee before: HUADA EMPYREAN SOFTWARE Co.,Ltd. |
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