CN104715089A - Implementation method of set resistance value wiring in flat-panel display design - Google Patents
Implementation method of set resistance value wiring in flat-panel display design Download PDFInfo
- Publication number
- CN104715089A CN104715089A CN201310686150.8A CN201310686150A CN104715089A CN 104715089 A CN104715089 A CN 104715089A CN 201310686150 A CN201310686150 A CN 201310686150A CN 104715089 A CN104715089 A CN 104715089A
- Authority
- CN
- China
- Prior art keywords
- resistance
- wiring
- flat
- implementation method
- admissible region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
The invention discloses an implementation method of a set resistance value wiring in a flat-panel display design. According to the implementation method, two groups of IC ports to be ligatured are selected, three ways are provided to load an initial wiring admissible region, and an editing method on a polygon in the initial wiring admissible region is provided for the trimming of the wiring restrain range of the set resistance value wiring; then, inverse-proportion allocation of the tuning wire length is conducted on each tuning wire formed in the polygon in the initial wiring admissible region according to a resistance constrain value; finally, trimming is conducted on a ligature outline until the outline reaches a reasonable standard by using a real-time dynamic regulation preview ligature geometrical shape and a mode that real-time computing that the resistance variation reaches a dynamic regulation wiring effect. The final goal trying to achieve of the trimming ligature outline is that the width of each ligature must be greater than a settable minimum width threshold value and the space between two adjacent ligatures must be greater than a settable minimum spacing threshold value; the resistance values of all the ligatures must less than or equal to a settable corresponding maximum resistance constraint value.
Description
Technical field
Resistance wiring implementation method of determining in a kind of flat-panel monitor design belongs to self routing design field in FPD (flat-panel monitor design) instrument.
Background technology
The main flow that flat pannel display (FPD) has become future television is trend of the times, but still there is no strict definition in the world at present, general this thickness of displays is thinner, look just as a flat board, the kind of flat pannel display is a lot, divide by display medium and principle of work, have liquid crystal display (LCD), plasma display (PDP), electroluminance display (ELD), ORGANIC ELECTROLUMINESCENCE DISPLAYS (OLED), Field Emission Display (FED), Projection Display etc.
Self routing occupies very large workload in slab design, and demand that should be different, there is again the wiring method that many kinds are different in reality, such as wait resistance wiring, based on the side wiring on pel array, etc.A kind of important demand is wherein had to be exactly determine resistance wiring.This wiring method for utilizing the remaining space of panel corner, or connects the IC end of the adjacent both sides of panel periphery, or the IC end that panel periphery one group is parallel.The demand of determining resistance wiring is often had in the TV screen design of large-size screen monitors.
Summary of the invention
In flat-panel monitor design process, connection between the IC port of connection panel periphery sides adjacent, usually have requirement to the distribution of resistance of different line, to reach the object of different current signal, this carries out appointment resistance line between two groups of different IC ports with regard to needing on panel.Traditional determine resistance wiring to have method outmoded, need a large amount of manual operations, inefficiency, be routed to the shortcomings such as power is low.The present invention disclose a kind of flat-panel monitor design in determine resistance wiring method, its wiring effect see accompanying drawing 1.First the method chooses the IC port that two groups are treated line, and provides three kinds of modes to load primary route admissible region, sees accompanying drawing 2.Then edit is provided to primary route admissible region polygon, in order to finely tune the Routing constraints scope of determining resistance wiring.Next turning round to the every bar be linked to be in primary route admissible region polygon, (the term line that turns round refers to the line segment on the corresponding summit of line primary route admissible region polygon to line, sees shown in the dotted line in accompanying drawing 3.) carry out inverse proportion according to resistance binding occurrence and distribute and to turn round line length, see accompanying drawing 3.After this distribute the line profile of gained to inverse proportion and carry out fine setting to finally reasonable.But, the point after inverse proportion distributes on connection line profile may not necessarily turn round on line, allowed a little departing from.Fine setting line profile finally wishes that the target reached is that the spacing that the width of every root line must be greater than the minimum widith threshold value that can set and every adjacent two lines must be greater than the minimum spacing threshold value that can set; The resistance value of all lines all must be less than or equal to the corresponding maximum resistance binding occurrence that can set.
The present invention also discloses the mode of a kind of geometric configuration of real-time dynamic adjustments preview line effect and the resistance form of energy live preview resistance variations connects up with dynamic conditioning, sees accompanying drawing 5.It or select a certain summit of line profile, or certain, or then certain side of line profile pulls to adjust in real time, follows the prompting frame showing current link information (comprising resistance information) near cursor in real time in form simultaneously.
Disclosed by the inventionly determine resistance wiring method and provide three kinds of modes to primary route admissible region, they are: 1, select the entity that connects up to provide primary route admissible region with its profile; 2, provide primary route admissible region with the file loading the primary route admissible region data message preserved; 3, according to the computing of to be connected up two groups of port location information intelligence to provide primary route admissible region.
Accompanying drawing explanation
Fig. 1 determines resistance wiring effect
Fig. 2 determines resistance wiring primary route admissible region presentation mode
Fig. 3 carries out by resistance binding occurrence inverse proportion allocated length the primary route admissible region polygon line that turns round
Point after Fig. 4 inverse proportion distributes on connection line profile may not necessarily turn round on line, allowed a little departing from
Fig. 5 determines the dynamic adjustments line shapes of resistance wiring to change resistance effect
concrete implementation step:
Flat-panel monitor design in determine resistance wiring an implementation method, disclose a kind of FPD self routing field determine resistance connect up method, implementation step is as follows:
1) choose the maximum resistance unbound document determining resistance wiring and load;
2) the port figure of two groups of cablings is chosen, to carry out determining resistance wiring between two groups of ports;
3) choose the mode that any one provides primary route admissible region, import primary route admissible region;
4) call and determine resistance wiring application program preview distribution effect, if not good, dynamic adjustments preview line profile to regulate its resistance, until finally meet the resistance restriction of maximum resistance unbound document;
Generate distribution: call and determine resistance wiring application program, what a key intelligence generation was final determines resistance wiring scheme.
Claims (7)
1. the present invention discloses and determines resistance Wiring design method in a kind of FPD (flat-panel monitor design), and its operating process feature is as follows:
A) choose the maximum resistance unbound document determining resistance wiring and load;
B) the port figure of two groups of cablings is chosen, to carry out determining resistance wiring between two groups of ports;
C) choose the mode that any one provides primary route admissible region, import primary route admissible region;
D) call and determine resistance wiring application program preview distribution effect, if not good, dynamic adjustments preview line profile to regulate its resistance, until finally meet the resistance restriction of maximum resistance unbound document;
E) generate wiring: call and determine resistance wiring application program, what a key intelligence generation was final determines resistance wiring scheme.
2. determine a resistance wiring implementation method in flat-panel monitor design, it is characterized in that the spacing that the width of the final every root line generated must be greater than the minimum widith threshold value that can set and every adjacent two lines must be greater than the minimum spacing threshold value that can set.
3. in flat-panel monitor design, determine resistance wiring implementation method, it is characterized in that the resistance value of the final all lines generated all must be less than or equal to the corresponding maximum resistance binding occurrence that can set, and the taking to retrain to distribute with the resistance that can set and substantially become certain relation to distribute of all line geometric widths.
4. determine a resistance wiring implementation method in flat-panel monitor design, it is characterized in that providing a kind of geometric configuration of real-time dynamic adjustments preview line and provide and calculate in real time the mode that resistance variations reaches dynamic conditioning wiring effect; It or select a certain summit of line profile, or certain on one side, or then certain side of line profile pulls to adjust in real time, now can eject the list of a reflected resistance situation of change immediately near form, in form, follow display one performance in real time near cursor current by the prompting frame of link information (comprising resistance information) edited simultaneously.
5. flat-panel monitor design in determine resistance wiring an implementation method, it is characterized in that by select one connect up entity provide primary route admissible region with its profile.
6. determining a resistance wiring implementation method in flat-panel monitor design, it is characterized in that providing primary route admissible region by loading the file of primary route admissible region data message preserved.
7. determine a resistance wiring implementation method in flat-panel monitor design, it is characterized in that can according to two groups of port location information intelligence to be connected up computing to provide primary route admissible region automatically.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310686150.8A CN104715089B (en) | 2013-12-16 | 2013-12-16 | Determine resistance value wiring implementation method in a kind of flat-panel monitor design |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310686150.8A CN104715089B (en) | 2013-12-16 | 2013-12-16 | Determine resistance value wiring implementation method in a kind of flat-panel monitor design |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104715089A true CN104715089A (en) | 2015-06-17 |
| CN104715089B CN104715089B (en) | 2018-06-22 |
Family
ID=53414415
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310686150.8A Active CN104715089B (en) | 2013-12-16 | 2013-12-16 | Determine resistance value wiring implementation method in a kind of flat-panel monitor design |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104715089B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106844801A (en) * | 2015-12-03 | 2017-06-13 | 北京华大九天软件有限公司 | Between a kind of vertical port with port it is wide and 90 degree turn round connection wiring methods |
| CN114386356A (en) * | 2020-10-16 | 2022-04-22 | Oppo广东移动通信有限公司 | Wiring method, device, equipment and storage medium for chip design |
| CN115952761A (en) * | 2023-01-10 | 2023-04-11 | 深圳华大九天科技有限公司 | Method and device for performing resistance compensation on wiring among multiple groups of parallel ports and storage medium |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1622703A (en) * | 2003-11-27 | 2005-06-01 | 三星Sdi株式会社 | Flat panel display device |
| CN1963827A (en) * | 2006-12-08 | 2007-05-16 | 清华大学 | Automatic wiring method of analog integrated circuit based on multiple step length labyrinth algorithm |
| CN1983287A (en) * | 2006-04-13 | 2007-06-20 | 华为技术有限公司 | Method and device for automatically adjusting Fanout design line width |
| US20080052646A1 (en) * | 2006-07-21 | 2008-02-28 | Magma Design Automation, Inc. | Lithography aware leakage analysis |
-
2013
- 2013-12-16 CN CN201310686150.8A patent/CN104715089B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1622703A (en) * | 2003-11-27 | 2005-06-01 | 三星Sdi株式会社 | Flat panel display device |
| CN1983287A (en) * | 2006-04-13 | 2007-06-20 | 华为技术有限公司 | Method and device for automatically adjusting Fanout design line width |
| US20080052646A1 (en) * | 2006-07-21 | 2008-02-28 | Magma Design Automation, Inc. | Lithography aware leakage analysis |
| CN1963827A (en) * | 2006-12-08 | 2007-05-16 | 清华大学 | Automatic wiring method of analog integrated circuit based on multiple step length labyrinth algorithm |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106844801A (en) * | 2015-12-03 | 2017-06-13 | 北京华大九天软件有限公司 | Between a kind of vertical port with port it is wide and 90 degree turn round connection wiring methods |
| CN114386356A (en) * | 2020-10-16 | 2022-04-22 | Oppo广东移动通信有限公司 | Wiring method, device, equipment and storage medium for chip design |
| CN115952761A (en) * | 2023-01-10 | 2023-04-11 | 深圳华大九天科技有限公司 | Method and device for performing resistance compensation on wiring among multiple groups of parallel ports and storage medium |
| CN115952761B (en) * | 2023-01-10 | 2024-07-23 | 深圳华大九天科技有限公司 | Method, device and storage medium for carrying out resistance compensation on wiring among multiple groups of parallel ports |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104715089B (en) | 2018-06-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP6305050B2 (en) | Image processing apparatus, image processing method, and program | |
| CN103069820B (en) | Display device, display control method | |
| US20150138040A1 (en) | Multivision display control device and multivision system | |
| CN108364567A (en) | Display panel and display device | |
| CN104715089A (en) | Implementation method of set resistance value wiring in flat-panel display design | |
| CN104299592A (en) | Liquid crystal panel and driving method thereof | |
| CN105719611A (en) | Display uniformity adjusting method and device for liquid crystal display equipment | |
| US20110235286A1 (en) | Display panel module and display apparatus | |
| CN107680556A (en) | A kind of display power-economizing method, device and display | |
| WO2015008696A1 (en) | Display panel and display device | |
| CN108988400B (en) | Power distribution method for multi-machine parallel power electronic transformer and electronic equipment | |
| JP2016535311A (en) | Liquid crystal display device and display control method thereof | |
| CN105118420A (en) | Drive method, drive circuit and display device of display panel | |
| CN104485077A (en) | Liquid crystal display panel and driving method thereof | |
| JP2016541220A (en) | How to display dot-by-dot on tiled display of input video | |
| JP6157106B2 (en) | Image processing apparatus and image processing method | |
| CN104765897A (en) | Equal-resistance wiring method for bidirectionally increasing wiring length | |
| CN105845077A (en) | Data compensator and display device including the same | |
| US9997916B2 (en) | Continuously balancing multiple phases of a power grid | |
| CN106157901B (en) | A kind of control system and method for bielectron ink screen | |
| CN106920502A (en) | A kind of control method of display device and display device | |
| CN104715088A (en) | Turning connection implementation method of wing-shaped narrow frame wiring in flat-panel display design | |
| CN205810348U (en) | A kind of mosaic screen control system | |
| JP6065167B2 (en) | Energy management support device and energy management support program | |
| US10038430B2 (en) | System for controlliing gatings of a multi-core processor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 100102 Second Floor, Block A, No. 2, Lize Middle Road, Chaoyang District, Beijing Patentee after: Beijing Huada Jiutian Technology Co.,Ltd. Address before: 100102 Second Floor, Block A, No. 2, Lize Middle Road, Chaoyang District, Beijing Patentee before: HUADA EMPYREAN SOFTWARE Co.,Ltd. |
|
| CP01 | Change in the name or title of a patent holder |