CN104659090A - LDMOS (Lateral Double-diffused Metal Oxide Semiconductor Field Effect Transistor) device and manufacturing method - Google Patents
LDMOS (Lateral Double-diffused Metal Oxide Semiconductor Field Effect Transistor) device and manufacturing method Download PDFInfo
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Abstract
The invention discloses an LDMOS (Lateral Double-diffused Metal Oxide Semiconductor Field Effect Transistor) device. An N-type injection layer formed by high-dose N-type impurity injection is additionally arranged in a drift region consisting of an N-type epitaxial layer; a P-type auxiliary depletion layer formed by high-dose P-type impurity injection is formed below one side, close to a source end, of the N-type injection layer; and a P-type diffusion layer formed by diffusing impurities of a P+ buried layer in the N-type epitaxial layer is formed on one side, close to the source end, of the N-type injection layer. The invention further discloses a manufacturing method of the LDMOS device. According to the device and the manufacturing method, the breakover resistance of the device can be reduced; the breakover current of the device can be increased; the electric field intensity of the surface of the drift region can be reduced; the breakdown voltage of the device can be increased; a BCD (Bipolar-CMOS-DMOS) technology can be integrated; and no additional technology cost is increased.
Description
Technical field
The present invention relates to semiconductor integrated circuit and manufacture field, particularly relate to a kind of lateral double diffusion metal oxide semiconductor field effect transistor (lateral double-dif fused MOSFET, LDMOS) device, the invention still further relates to this LDMOS device manufacture method.
Background technology
Double-diffusion metal-oxide-semiconductor field effect transistor (DMOS) is high pressure resistant owing to having, and the feature such as high current drive capability and extremely low power dissipation, is widely adopted at present in electric power management circuit.In LDMOS device, conducting resistance is an important index.At BCD (Bipolar-CMOS-DMOS, bipolar-complementary metal oxide semiconductors (CMOS)-dual diffused metal oxide emiconductor) in technique, although DMOS with CMOS is integrated in same chip, but and requirement of low on-resistance withstand voltage due to height, under the prerequisite that the condition of DMOS in background region and drift region and the existing process conditions of CMOS are shared, its conducting resistance is higher, often cannot meet the requirement of switching tube application.Therefore, in order to make high performance LDMOS, need the conducting resistance adopting various method optimised devices.Usual needs increase by one extra N-type injection in the drift region of device, make device have lower conducting resistance, and adopt the puncture voltage that can reduce device in this way.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of LDMOS device, the conducting resistance of device can be reduced, increase the On current of device, the surface field intensity of drift region can be reduced simultaneously, increase the puncture voltage of device, can be integrated in BCD technique, not need to increase additional technology cost.For this reason, present invention also offers the manufacture method of LDMOS device.
For solving the problems of the technologies described above, LDMOS device provided by the invention comprises:
N+ buried regions, is formed in P-type silicon substrate.
P+ buried regions, above the subregion being formed at described N+ buried regions, the bottom of described P+ buried regions contacts with described N+ buried regions.
N-type epitaxy layer, is formed at described surface of silicon, and after the bottom difference of described N-type epitaxy layer, described N+ buried regions contacts with described P+ buried regions.
P type diffused layer, be formed in the described N-type epitaxy layer at described P+ buried regions top, the p type impurity of described p type diffused layer is diffuseed to form in described N-type epitaxy layer by described P+ buried regions.
Shallow trench field oxygen layer (STI), to be formed in described N-type epitaxy layer and for the isolation of active area.
P trap, is formed in described N-type epitaxy layer, and described P trap and described p type diffused layer are separated by a segment distance.
N trap, is formed in described p type diffused layer; Between described N trap and described P trap, isolation has a described shallow trench field oxygen layer, makes this shallow trench field oxygen layer be the first shallow trench field oxygen layer, described N trap and described first shallow trench field oxygen layer autoregistration.
N-type implanted layer, is formed in described N-type epitaxy layer, the contacts side surfaces of described N-type implanted layer first side and described P trap, and the second side of described N-type implanted layer extends in described p type diffused layer and also described first shallow trench field oxygen layer and described N trap surrounded.
P type assisted depletion layer, be formed at below described N-type implanted layer, described first side of P type assisted depletion layer and the contacts side surfaces of described P trap, described second side of P type assisted depletion layer and the contacts side surfaces of described p type diffused layer, the top of described P trap assisted depletion layer contacts with described N-type implanted layer.
Grid structure, be made up of the gate dielectric layer and polysilicon gate that are formed at described N-type epitaxy layer surface, P trap surface described in described grid structure cover part also extends transverse to described N-type implanted layer surface and described first shallow trench field oxygen layer on the surface, the described P trap surface that covers by described grid structure for the formation of raceway groove.
Source region, forms by being formed at described P trap Zhong N+ district, the first side autoregistration of described source region and described grid structure.
Drain region, forms by being formed at described N trap Zhong N+ district, described drain region and described first shallow trench field oxygen layer autoregistration.
P type substrate draw-out area, forms, for drawing described P trap by being formed at described P trap Zhong P+ district.
The drift region of LDMOS device is made up of the described N-type implanted layer between described N trap and described P trap, described P type assisted depletion layer, described p type diffused layer and described N-type epitaxy layer; The doping content of described N-type implanted layer is higher, and the conducting resistance of described LDMOS device is lower; Described P type assisted depletion layer and described p type diffused layer are used for exhausting from bottom to described N-type implanted layer, and it is smooth that the doping content that the doping content of described P type assisted depletion layer is greater than described p type diffused layer makes described N-type implanted layer exhaust rear surface electric field.
Further improvement is, the implanted dopant of the ion implantation of described N-type implanted layer is phosphorus or arsenic, and Implantation Energy is 50KeV ~ 600KeV, and implantation dosage scope is 1e11cm
-2~ 1e13cm
-2.
Further improvement is, the implanted dopant of the ion implantation of described P type assisted depletion layer is boron, and Implantation Energy is 800KeV ~ 1500KeV, and implantation dosage scope is 1e11cm
-2~ 1e13cm
-2.
For solving the problems of the technologies described above, the manufacture method of LDMOS device provided by the invention comprises the steps:
Step one, employing ion implantation technology form N+ buried regions in P-type silicon substrate.
Step 2, employing ion implantation technology form P+ buried regions above the subregion of described N+ buried regions, and the ion implanted regions of described P+ buried regions is defined by photoetching process.
Step 3, form N-type epitaxy layer in the described surface of silicon being formed with described N+ buried regions and described P+ buried regions, the bottom of described N-type epitaxy layer respectively after described N+ buried regions contact with described P+ buried regions.
Step 4, carry out picking and into technique the p type impurity of described P+ buried regions to be spread in the described N-type epitaxy layer at described P+ buried regions top and to form p type diffused layer.
Step 5, in described N-type epitaxy layer, form shallow trench field oxygen layer, described shallow trench field oxygen layer is used for isolating active area.
Step 6, photoetching are opened P trap injection zone and are carried out P type ion implantation in this region and form P trap in described N-type epitaxy layer, and described P trap and described p type diffused layer are separated by a segment distance; Photoetching is opened N trap injection zone and is carried out N-type ion implantation in this region and form N trap in described p type diffused layer, between described N trap and described P trap, isolation has a described shallow trench field oxygen layer, this shallow trench field oxygen layer is made to be the first shallow trench field oxygen layer, described N trap and described first shallow trench field oxygen layer autoregistration.
Step 7, photoetching are opened N-type implanted layer region and are carried out N-type ion implantation in this region and form N-type implanted layer in described N-type epitaxy layer, the contacts side surfaces of described N-type implanted layer first side and described P trap, the second side of described N-type implanted layer extends in described p type diffused layer and also described first shallow trench field oxygen layer and described N trap is surrounded.
Step 8, photoetching are opened P type assisted depletion layer region and are carried out P type ion implantation in this region in described N-type epitaxy layer, form P type assisted depletion layer, described P type assisted depletion layer is positioned at below described N-type implanted layer, described first side of P type assisted depletion layer and the contacts side surfaces of described P trap, described second side of P type assisted depletion layer and the contacts side surfaces of described p type diffused layer, the top of described P trap assisted depletion layer contacts with described N-type implanted layer.
Step 9, on described N-type epitaxy layer surface successively deposit gate dielectric layer and polysilicon gate, chemical wet etching is carried out to described polysilicon gate and described gate dielectric layer and forms grid structure, P trap surface described in described grid structure cover part also extends transverse to described N-type implanted layer surface and described first shallow trench field oxygen layer on the surface, the described P trap surface that covers by described grid structure for the formation of raceway groove.
Step 10, carry out N+ source and drain ion implantation and form source region and drain region, described source region is arranged in described P trap, the first side autoregistration of described source region and described grid structure; Described drain region is arranged in described N trap, described drain region and described first shallow trench field oxygen layer autoregistration; Carry out P+ ion implantation and form P type substrate draw-out area, described P type substrate draw-out area is arranged in described P trap, for drawing described P trap.
The drift region of LDMOS device is made up of the described N-type implanted layer between described N trap and described P trap, described P type assisted depletion layer, described p type diffused layer and described N-type epitaxy layer; The doping content of described N-type implanted layer is higher, and the conducting resistance of described LDMOS device is lower; Described P type assisted depletion layer and described p type diffused layer are used for exhausting from bottom to described N-type implanted layer, and it is smooth that the doping content that the doping content of described P type assisted depletion layer is greater than described p type diffused layer makes described N-type implanted layer exhaust rear surface electric field.
Further improvement is, the implanted dopant of the ion implantation of the implanted layer of N-type described in step 7 is phosphorus or arsenic, and Implantation Energy is 50KeV ~ 600KeV, and implantation dosage scope is 1e11cm
-2~ 1e13cm
-2.
Further improvement is, the implanted dopant of the ion implantation of the type of P described in step 8 assisted depletion layer is boron, and Implantation Energy is 800KeV ~ 1500KeV, and implantation dosage scope is 1e11cm
-2~ 1e13cm
-2.
Further improvement is, the resistivity of described P-type silicon substrate is 0.007 ohmcm ~ 0.013 ohmcm.
Further improvement is, the manufacturing process of described LDMOS device is integrated in BCD technique, described P trap in the manufacturing process of described LDMOS device is identical with the P trap technique of the cmos device in described BCD technique and synchronously formed, described N trap in the manufacturing process of described LDMOS device is identical with the N-well process of the cmos device in described BCD technique and synchronously formed, described N+ source and drain ion implantation in the manufacturing process of described LDMOS device is identical with the N+ source and drain ion implantation of the cmos device in described BCD technique and synchronously formed, the described P+ source and drain ion implantation of the described P type substrate draw-out area in the manufacturing process of described LDMOS device is identical with the P+ source and drain ion implantation of the cmos device in described BCD technique and synchronously formed, the formation process of the described grid structure in the manufacturing process of described LDMOS device is identical with the formation process of the grid structure of the cmos device in described BCD technique and synchronously formed.
The present invention has following beneficial effect:
1, LDMOS device of the present invention is injected by the doping of adjusting device, and the N-type impurity increasing high dose in drift region injects the conducting resistance that formation N-type implanted layer effectively can reduce device.
2, the present invention is injected by the p type impurity increasing high dose in the below of the close source side of N-type implanted layer and forms P type assisted depletion layer and utilize the below formation p type diffused layer being diffused in the close drain region of N-type implanted layer of p type buried layer, can realize utilizing P type assisted depletion layer and p type diffused layer to exhaust from bottom to N-type implanted layer, thus the puncture voltage of device can be increased; It is smooth that the doping content that the doping content of P type assisted depletion layer is also greater than described p type diffused layer by the present invention can make N-type implanted layer exhaust rear surface electric field, thus further can improve the puncture voltage of device.
3, the present invention can be integrated in BCD technique, and not needing increases additional technology cost.As the common process in P+ buried regions technique of the present invention originally BCD technique, only need the reticle to P+ buried regions injects to modify, do not need to increase extra reticle; As all process conditions of the present invention as source and drain injection technology can share with the CMOS technology in BCD technique platform.
4, have higher puncture voltage because device of the present invention has larger conducting resistance, all devices of the present invention can meet the operating characteristic of switching device and analogue device simultaneously simultaneously.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:
Fig. 1 is the structural representation of embodiment of the present invention LDMOS device;
Fig. 2 is the ionization by collision distribution map of existing LDMOS device;
Fig. 3 is the ionization by collision distribution map of embodiment of the present invention LDMOS device;
Fig. 4 is embodiment of the present invention LDMOS device and the electric field strength profile comparison diagram of existing LDMOS device below the oxygen layer of shallow trench field;
Device architecture schematic diagram in each step of the manufacture method of Fig. 5 A-Fig. 5 I embodiment of the present invention LDMOS device.
Embodiment
Fig. 1 is the structural representation of embodiment of the present invention LDMOS device; Embodiment of the present invention LDMOS device is N-type LDMOS device, comprising:
N+ buried regions 102, is formed in P-type silicon substrate 101.
P+ buried regions 103, above the subregion being formed at described N+ buried regions 102, the bottom of described P+ buried regions 103 contacts with described N+ buried regions 102.
N-type epitaxy layer 104, is formed at described silicon substrate 101 surface, the bottom of described N-type epitaxy layer 104 respectively after described N+ buried regions 102 contact with described P+ buried regions 103.
P type diffused layer 105, be formed in the described N-type epitaxy layer 104 at described P+ buried regions 103 top, the p type impurity of described p type diffused layer 105 is diffuseed to form in described N-type epitaxy layer 104 by described P+ buried regions 103.
Shallow trench field oxygen layer 106, to be formed in described N-type epitaxy layer 104 and for the isolation of active area 114a.
P trap 108, is formed in described N-type epitaxy layer 104, and described P trap 108 and described p type diffused layer 105 are separated by a segment distance.
N trap 107, is formed in described p type diffused layer 105; Between described N trap 107 and described P trap 108, isolation has a described shallow trench field oxygen layer 106, makes this shallow trench field oxygen layer 106 be the first shallow trench field oxygen layer 106, described N trap 107 and described first shallow trench field oxygen layer 106 autoregistration.
N-type implanted layer 109, be formed in described N-type epitaxy layer 104, the contacts side surfaces of described N-type implanted layer 109 first side and described P trap 108, the second side of described N-type implanted layer 109 to extend in described p type diffused layer 105 and described first shallow trench field oxygen layer 106 and described N trap 107 is surrounded.Be preferably, the implanted dopant of the ion implantation of described N-type implanted layer 109 is phosphorus or arsenic, and Implantation Energy is 50KeV ~ 600KeV, and implantation dosage scope is 1e11cm
-2~ 1e13cm
-2.
P type assisted depletion layer 110, be formed at below described N-type implanted layer 109, described first side of P type assisted depletion layer 110 and the contacts side surfaces of described P trap 108, described second side of P type assisted depletion layer 110 and the contacts side surfaces of described p type diffused layer 105, the top of described P trap 108 assisted depletion layer contacts with described N-type implanted layer 109.Be preferably, the implanted dopant of the ion implantation of described P type assisted depletion layer 110 is boron, and Implantation Energy is 800KeV ~ 1500KeV, and implantation dosage scope is 1e11cm
-2~ 1e13cm
-2.
Grid structure, is made up of the gate dielectric layer 111 and polysilicon gate 112 being formed at described N-type epitaxy layer 104 surface; Be preferably, described gate dielectric layer 111 is gate oxide, and the side of described polysilicon gate 112 is formed with side wall 113.P trap 108 surface described in described grid structure cover part also extends transverse to described N-type implanted layer 109 surface and described first shallow trench field oxygen layer 106 on the surface, described P trap 108 surface that covers by described grid structure for the formation of raceway groove.
Source region 114a, forms by being formed at described P trap 108 Zhong N+ district, the first side autoregistration of described source region 114a and described grid structure.
Drain region 114b, forms by being formed at described N trap 107 Zhong N+ district, described drain region 114b and described first shallow trench field oxygen layer 106 autoregistration.
P type substrate draw-out area 115, forms, for drawing described P trap 108 by being formed at described P trap 108 Zhong P+ district.
The drift region of LDMOS device is made up of the described N-type implanted layer 109 between described N trap 107 and described P trap 108, described P type assisted depletion layer 110, described p type diffused layer 105 and described N-type epitaxy layer 104; The doping content of described N-type implanted layer 109 is higher, and the conducting resistance of described LDMOS device is lower; Described P type assisted depletion layer 110 and described p type diffused layer 105 are for exhausting from bottom to described N-type implanted layer 109, and it is smooth that the doping content that the doping content of described P type assisted depletion layer 110 is greater than described P trap 108 diffusion layer makes described N-type implanted layer 109 exhaust rear surface electric field.
Described source region 114a, described drain region 114b, described P type substrate draw-out area 115 and described polysilicon gate 112 are connected respectively by contact hole 116 and top metal lead-in wire 117 and realize the extraction of source electrode, drain electrode, P type substrate extraction electrode and grid respectively.
Embodiment of the present invention LDMOS device is not injected by means of only the N-type impurity increasing high dose in drift region and is formed the conducting resistance that N-type implanted layer effectively reduces device; Also formed respectively by the bottom at N-type implanted layer and be optimized near the P type assisted depletion layer of source and the surface electric field distribution of p type diffused layer to drift region of close drain terminal, thus the puncture voltage of device can be improved, so the problem that the puncture voltage caused when the embodiment of the present invention can avoid the N-type impurity of simple increase drift region in prior art to inject reduces.In order to the above-mentioned advantage of the embodiment of the present invention is described intuitively, please refer to Fig. 2-Fig. 4:
As shown in Figure 2, be the ionization by collision distribution map of existing LDMOS device, existing LDMOS device is injected by the doping of adjusting device, although the N-type impurity increasing high dose in N-type drift region injects the conducting resistance that effectively can reduce device, but due to the impact of shallow-trench isolation and shallow trench field oxygen layer 106 (STI) pattern own, compared with the device adopting local oxidation (LOCOS) to isolate, the N-type increasing drift region injects the decline more easily causing device electric breakdown strength, bottom STI106, sharp corner electric field can sharply raise along with the raising of N-type drift region doped level and reach critical electric field, the puncture voltage of more than 50V is made to be reduced to about 30V, shown in dotted line frame 1 in Fig. 2, region is sharp corner bottom STI106, region described in dotted line frame 2 is the enlarged drawing in region shown in dotted line frame 1, known in whole drift region, the electric field of dotted line frame 1 is the most concentrated.
As shown in Figure 3, be the ionization by collision distribution map of embodiment of the present invention LDMOS device; The embodiment of the present invention utilizes original process conditions in BCD technique platform, below the N-type implanted layer 109 of the drift region near source, adopt the P type of higher dosage to inject form P type assisted depletion layer 110, near drain terminal for increasing the injection of P+ buried regions 103 above the N+ buried regions 102 of isolating, namely P+ buried regions 103 is integrated in BCD technique platform originally, only need to modify to reticle, do not need to increase extra reticle.In P+ buried regions 103, impurity is through picking into forming assisted depletion district and p type diffused layer 105 below N-type drift region; Can to N-type implanted layer 109 be exhausted from bottom by P type assisted depletion layer 110 and p type diffused layer 105 thus can increase the puncture voltage of device, the setting of P type assisted depletion layer 110 and p type diffused layer 105 doping content also helps change surface electric field distribution; As described in Figure 3, electric field does not concentrate on the corner positions of dotted line frame 1 as shown in Figure 2, and electric field compares the bottom being evenly distributed on whole shallow trench field oxygen 106.
As shown in Figure 4, be embodiment of the present invention LDMOS device and the electric field strength profile comparison diagram of existing LDMOS device below the oxygen layer of shallow trench field.Wherein curve 3 corresponds to the electric field strength profile of existing LDMOS device below the oxygen layer of shallow trench field, its electric field strength known sharp corner bottom STI106 has a peak value, and electric field strength at other region place reduces, when the electric field strength at this peak value place reaches critical value, device will puncture.Wherein curve 4 corresponds to the electric field strength profile of embodiment of the present invention LDMOS device below the oxygen layer of shallow trench field, and its electric field strength known is relatively more even bottom STI106, does not have to occur obviously high and low region.Comparison curves 4 and 3 is known, when device breakdown, curve 4 enclose area be obviously greater than curve 3 enclose area, namely also the puncture voltage of the embodiment of the present invention is greater than the puncture voltage of existing device.Existing device by making puncture voltage be reduced to about 30V from the puncture voltage of more than 50V after drift region increases N-type implanted layer, and embodiment of the present invention device really can also make puncture voltage maintain more than 50V after increase N-type implanted layer, the conducting resistance of device can be made to be reduced to 35 from 49 simultaneously.
As shown in Fig. 5 A to Fig. 5 I, it is the device architecture schematic diagram in each step of the manufacture method of embodiment of the present invention LDMOS device.The manufacture method of embodiment of the present invention LDMOS device comprises the steps:
Step one, as shown in Figure 5A, adopts ion implantation technology to form N+ buried regions 102 in P-type silicon substrate 101.The resistivity of described P-type silicon substrate 101 is 0.007 ohmcm ~ 0.013 ohmcm.
Step 2, as shown in Figure 5 B, adopt ion implantation technology to form P+ buried regions 103 above the subregion of described N+ buried regions 102, the ion implanted regions of described P+ buried regions 103 is defined by photoetching process.
Step 3, as shown in Figure 5 C, forms N-type epitaxy layer 104 on described silicon substrate 101 surface being formed with described N+ buried regions 102 and described P+ buried regions 103, the bottom of described N-type epitaxy layer 104 respectively after described N+ buried regions 102 contact with described P+ buried regions 103.
Step 4, as shown in Figure 5 C, carries out picking and to be spread in the described N-type epitaxy layer 104 at described P+ buried regions 103 top by the p type impurity of described P+ buried regions 103 into technique and to form p type diffused layer 105.
Step 5, as shown in Figure 5 D, described N-type epitaxy layer 104 forms shallow trench field oxygen layer 106, described shallow trench field oxygen layer 106 is for isolating active area 114a.Need to utilize active area photoetching when forming shallow trench field oxygen layer 106, described N-type epitaxy layer 104 opens shallow trench area, the silicon etching this shallow trench area forms shallow trench, fill oxide in described shallow trench, forms described shallow trench field oxygen layer 106. after etching and grind to the oxide of filling
Step 6, as shown in fig. 5e, photoetching is opened P trap 108 injection zone and is carried out P type ion implantation in this region and form P trap 108 in described N-type epitaxy layer 104, and described P trap 108 and described p type diffused layer 105 are separated by a segment distance; Photoetching is opened N trap 107 injection zone and is carried out N-type ion implantation in this region and form N trap 107 in described p type diffused layer 105, between described N trap 107 and described P trap 108, isolation has a described shallow trench field oxygen layer 106, this shallow trench field oxygen layer 106 is made to be the first shallow trench field oxygen layer 106, described N trap 107 and described first shallow trench field oxygen layer 106 autoregistration.
Step 7, as illustrated in figure 5f, photoetching is opened N-type implanted layer 109 region and is carried out N-type ion implantation in this region and form N-type implanted layer 109 in described N-type epitaxy layer 104, the contacts side surfaces of described N-type implanted layer 109 first side and described P trap 108, the second side of described N-type implanted layer 109 to extend in described p type diffused layer 105 and described first shallow trench field oxygen layer 106 and described N trap 107 is surrounded.Be preferably, the implanted dopant of the ion implantation of described N-type implanted layer 109 is phosphorus or arsenic, and Implantation Energy is 50KeV ~ 600KeV, and implantation dosage scope is 1e11cm
-2~ 1e13cm
-2.
Step 8, as illustrated in figure 5f, photoetching is opened P type assisted depletion layer 110 region and is carried out P type ion implantation in this region in described N-type epitaxy layer 104, forms P type assisted depletion layer 110, described P type assisted depletion layer 110 is positioned at below described N-type implanted layer 109, described first side of P type assisted depletion layer 110 and the contacts side surfaces of described P trap 108, described second side of P type assisted depletion layer 110 and the contacts side surfaces of described p type diffused layer 105, the top of described P trap 108 assisted depletion layer contacts with described N-type implanted layer 109.Be preferably, the implanted dopant of the ion implantation of described P type assisted depletion layer 110 is boron, and Implantation Energy is 800KeV ~ 1500KeV, and implantation dosage scope is 1e11cm
-2~ 1e13cm
-2.
Step 9, as depicted in fig. 5g, on described N-type epitaxy layer 104 surface successively deposit gate dielectric layer 111 and polysilicon gate 112, chemical wet etching is carried out to described polysilicon gate 112 and described gate dielectric layer 111 and forms grid structure, P trap 108 surface described in described grid structure cover part also extends transverse to described N-type implanted layer 109 surface and described first shallow trench field oxygen layer 106 on the surface, described P trap 108 surface that covers by described grid structure for the formation of raceway groove.
As illustrated in fig. 5h, the silicon dioxide of deposit one deck 2500 dust ~ 3500 dust, forms side wall 113 in the side of described polysilicon gate 112 after dry etching.
Step 10, as shown in fig. 5i, carry out N+ source and drain ion implantation and form source region 114a and drain region 114b, described source region 114a is arranged in described P trap 108, the first side autoregistration of described source region 114a and described grid structure; Described drain region 114b is arranged in described N trap 107, described drain region 114b and described first shallow trench field oxygen layer 106 autoregistration; Carry out P+ ion implantation and form P type substrate draw-out area 115, described P type substrate draw-out area 115 is arranged in described P trap 108, for drawing described P trap 108.
The drift region of LDMOS device is made up of the described N-type implanted layer 109 between described N trap 107 and described P trap 108, described P type assisted depletion layer 110, described p type diffused layer 105 and described N-type epitaxy layer 104; The doping content of described N-type implanted layer 109 is higher, and the conducting resistance of described LDMOS device is lower; Described P type assisted depletion layer 110 and described p type diffused layer 105 are for exhausting from bottom to described N-type implanted layer 109, and it is smooth that the doping content that the doping content of described P type assisted depletion layer 110 is greater than described P trap 108 diffusion layer makes described N-type implanted layer 109 exhaust rear surface electric field.
As shown in Figure 1, finally also comprise step: form interlayer film, form contact hole 116 by contact hole technique and connect; Form top metal lead-in wire 117, described source region 114a, described drain region 114b, described P type substrate draw-out area 115 and described polysilicon gate 112 to be connected respectively by contact hole 116 and top metal lead-in wire 117 and the extraction realizing source electrode, drain electrode, P type substrate extraction electrode and grid respectively.
The manufacturing process of LDMOS device described in the embodiment of the present invention can be integrated in BCD technique, described P trap 108 in the manufacturing process of described LDMOS device is identical with P trap 108 technique of the cmos device in described BCD technique and synchronously formed, described N trap 107 in the manufacturing process of described LDMOS device is identical with N trap 107 technique of the cmos device in described BCD technique and synchronously formed, described N+ source and drain ion implantation in the manufacturing process of described LDMOS device is identical with the N+ source and drain ion implantation of the cmos device in described BCD technique and synchronously formed, the described P+ source and drain ion implantation of the described P type substrate draw-out area 115 in the manufacturing process of described LDMOS device is identical with the P+ source and drain ion implantation of the cmos device in described BCD technique and synchronously formed, the formation process of the described grid structure in the manufacturing process of described LDMOS device is identical with the formation process of the grid structure of the cmos device in described BCD technique and synchronously formed.
Above by specific embodiment to invention has been detailed description, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (8)
1. a LDMOS device, is characterized in that, comprising:
N+ buried regions, is formed in P-type silicon substrate;
P+ buried regions, above the subregion being formed at described N+ buried regions, the bottom of described P+ buried regions contacts with described N+ buried regions;
N-type epitaxy layer, is formed at described surface of silicon, and after the bottom difference of described N-type epitaxy layer, described N+ buried regions contacts with described P+ buried regions;
P type diffused layer, be formed in the described N-type epitaxy layer at described P+ buried regions top, the p type impurity of described p type diffused layer is diffuseed to form in described N-type epitaxy layer by described P+ buried regions;
Shallow trench field oxygen layer, to be formed in described N-type epitaxy layer and for the isolation of active area;
P trap, is formed in described N-type epitaxy layer, and described P trap and described p type diffused layer are separated by a segment distance;
N trap, is formed in described p type diffused layer; Between described N trap and described P trap, isolation has a described shallow trench field oxygen layer, makes this shallow trench field oxygen layer be the first shallow trench field oxygen layer, described N trap and described first shallow trench field oxygen layer autoregistration;
N-type implanted layer, is formed in described N-type epitaxy layer, the contacts side surfaces of described N-type implanted layer first side and described P trap, and the second side of described N-type implanted layer extends in described p type diffused layer and also described first shallow trench field oxygen layer and described N trap surrounded;
P type assisted depletion layer, be formed at below described N-type implanted layer, described first side of P type assisted depletion layer and the contacts side surfaces of described P trap, described second side of P type assisted depletion layer and the contacts side surfaces of described p type diffused layer, the top of described P trap assisted depletion layer contacts with described N-type implanted layer;
Grid structure, be made up of the gate dielectric layer and polysilicon gate that are formed at described N-type epitaxy layer surface, P trap surface described in described grid structure cover part also extends transverse to described N-type implanted layer surface and described first shallow trench field oxygen layer on the surface, the described P trap surface that covers by described grid structure for the formation of raceway groove;
Source region, forms by being formed at described P trap Zhong N+ district, the first side autoregistration of described source region and described grid structure;
Drain region, forms by being formed at described N trap Zhong N+ district, described drain region and described first shallow trench field oxygen layer autoregistration;
P type substrate draw-out area, forms, for drawing described P trap by being formed at described P trap Zhong P+ district;
The drift region of LDMOS device is made up of the described N-type implanted layer between described N trap and described P trap, described P type assisted depletion layer, described p type diffused layer and described N-type epitaxy layer; The doping content of described N-type implanted layer is higher, and the conducting resistance of described LDMOS device is lower; Described P type assisted depletion layer and described p type diffused layer are used for exhausting from bottom to described N-type implanted layer, and it is smooth that the doping content that the doping content of described P type assisted depletion layer is greater than described p type diffused layer makes described N-type implanted layer exhaust rear surface electric field.
2. LDMOS device as claimed in claim 1, is characterized in that: the implanted dopant of the ion implantation of described N-type implanted layer is phosphorus or arsenic, and Implantation Energy is 50KeV ~ 600KeV, and implantation dosage scope is 1e11cm
-2~ 1e13cm
-2.
3. LDMOS device as claimed in claim 1, is characterized in that: the implanted dopant of the ion implantation of described P type assisted depletion layer is boron, and Implantation Energy is 800KeV ~ 1500KeV, and implantation dosage scope is 1e11cm
-2~ 1e13cm
-2.
4. a manufacture method for LDMOS device, is characterized in that, comprises the steps:
Step one, employing ion implantation technology form N+ buried regions in P-type silicon substrate;
Step 2, employing ion implantation technology form P+ buried regions above the subregion of described N+ buried regions, and the ion implanted regions of described P+ buried regions is defined by photoetching process;
Step 3, form N-type epitaxy layer in the described surface of silicon being formed with described N+ buried regions and described P+ buried regions, the bottom of described N-type epitaxy layer respectively after described N+ buried regions contact with described P+ buried regions;
Step 4, carry out picking and into technique the p type impurity of described P+ buried regions to be spread in the described N-type epitaxy layer at described P+ buried regions top and to form p type diffused layer;
Step 5, in described N-type epitaxy layer, form shallow trench field oxygen layer, described shallow trench field oxygen layer is used for isolating active area;
Step 6, photoetching are opened P trap injection zone and are carried out P type ion implantation in this region and form P trap in described N-type epitaxy layer, and described P trap and described p type diffused layer are separated by a segment distance; Photoetching is opened N trap injection zone and is carried out N-type ion implantation in this region and form N trap in described p type diffused layer, between described N trap and described P trap, isolation has a described shallow trench field oxygen layer, this shallow trench field oxygen layer is made to be the first shallow trench field oxygen layer, described N trap and described first shallow trench field oxygen layer autoregistration;
Step 7, photoetching are opened N-type implanted layer region and are carried out N-type ion implantation in this region and form N-type implanted layer in described N-type epitaxy layer, the contacts side surfaces of described N-type implanted layer first side and described P trap, the second side of described N-type implanted layer extends in described p type diffused layer and also described first shallow trench field oxygen layer and described N trap is surrounded;
Step 8, photoetching are opened P type assisted depletion layer region and are carried out P type ion implantation in this region in described N-type epitaxy layer, form P type assisted depletion layer, described P type assisted depletion layer is positioned at below described N-type implanted layer, described first side of P type assisted depletion layer and the contacts side surfaces of described P trap, described second side of P type assisted depletion layer and the contacts side surfaces of described p type diffused layer, the top of described P trap assisted depletion layer contacts with described N-type implanted layer;
Step 9, on described N-type epitaxy layer surface successively deposit gate dielectric layer and polysilicon gate, chemical wet etching is carried out to described polysilicon gate and described gate dielectric layer and forms grid structure, P trap surface described in described grid structure cover part also extends transverse to described N-type implanted layer surface and described first shallow trench field oxygen layer on the surface, the described P trap surface that covers by described grid structure for the formation of raceway groove;
Step 10, carry out N+ source and drain ion implantation and form source region and drain region, described source region is arranged in described P trap, the first side autoregistration of described source region and described grid structure; Described drain region is arranged in described N trap, described drain region and described first shallow trench field oxygen layer autoregistration; Carry out P+ ion implantation and form P type substrate draw-out area, described P type substrate draw-out area is arranged in described P trap, for drawing described P trap;
The drift region of LDMOS device is made up of the described N-type implanted layer between described N trap and described P trap, described P type assisted depletion layer, described p type diffused layer and described N-type epitaxy layer; The doping content of described N-type implanted layer is higher, and the conducting resistance of described LDMOS device is lower; Described P type assisted depletion layer and described p type diffused layer are used for exhausting from bottom to described N-type implanted layer, and it is smooth that the doping content that the doping content of described P type assisted depletion layer is greater than described p type diffused layer makes described N-type implanted layer exhaust rear surface electric field.
5. method as claimed in claim 4, is characterized in that: the implanted dopant of the ion implantation of the implanted layer of N-type described in step 7 is phosphorus or arsenic, and Implantation Energy is 50KeV ~ 600KeV, and implantation dosage scope is 1e11cm
-2~ 1e13cm
-2.
6. method as claimed in claim 4, is characterized in that: the implanted dopant of the ion implantation of the type of P described in step 8 assisted depletion layer is boron, and Implantation Energy is 800KeV ~ 1500KeV, and implantation dosage scope is 1e11cm
-2~ 1e13cm
-2.
7. method as claimed in claim 4, is characterized in that: the resistivity of described P-type silicon substrate is 0.007 ohmcm ~ 0.013 ohmcm.
8. method as claimed in claim 4, it is characterized in that: the manufacturing process of described LDMOS device is integrated in BCD technique, described P trap in the manufacturing process of described LDMOS device is identical with the P trap technique of the cmos device in described BCD technique and synchronously formed, described N trap in the manufacturing process of described LDMOS device is identical with the N-well process of the cmos device in described BCD technique and synchronously formed, described N+ source and drain ion implantation in the manufacturing process of described LDMOS device is identical with the N+ source and drain ion implantation of the cmos device in described BCD technique and synchronously formed, the described P+ source and drain ion implantation of the described P type substrate draw-out area in the manufacturing process of described LDMOS device is identical with the P+ source and drain ion implantation of the cmos device in described BCD technique and synchronously formed, the formation process of the described grid structure in the manufacturing process of described LDMOS device is identical with the formation process of the grid structure of the cmos device in described BCD technique and synchronously formed.
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