CN104658601A - PUF (physically unclonable function) authentication method based on STT-RAM (spin-torque transfer RAM) storage unit error rate distribution - Google Patents

Abstract

The invention discloses a physical non-clonable authentication method using the error rate distribution of the storage unit of the spin torque transfer random reader (STT-RAM), including a preprocessing stage, a registration stage and a verification stage, including the steps: first in the preprocessing The stage records the positions of all EDPs in the STT-RAM array, and then inputs a number of EDP positions in the registration stage. The chip circuit uses the relative size of the two cell error rates in these EDPs to output a reference output, and reproduces the registration stage again in the verification stage. Finally, according to The output of the verification phase and the registration phase verifies whether the given device is the same as the device in the registration phase, thereby authenticating the authenticity of the chip. The method provided by the invention solves the problem of equipment authentication and improves the reliability of authentication at a small hardware cost and time cost.

Description

PUF authentication method based on error rate distribution of STT-RAM storage unit

technical field

The invention belongs to the field of information security and relates to a physical unclonable (PUF) authentication method, in particular to a physical unclonable authentication method based on the error rate distribution of STT-RAM storage units.

Background technique

Spin torque transfer random reader (STT-RAM) is a new type of non-volatile (Non-volatile) memory. STT-RAM is considered to be one of the future SRAM substitutes, with the advantages of high density, low static power consumption, and low memory access time. At the same time, physical unclonable technology (PUF) is being widely suggested for device authentication, and other non-volatile storage has been proposed for making PUF, but there are generally problems such as high hardware overhead or high latency.

In 2011, Prabhu et al. in the United States proposed to use NAND Flash for device authentication. They first extract the sensitivity of each bit in Flash to disturbance errors, programming delays, etc., and then calculate the correlation coefficient to distinguish and authenticate chips. This method has a long delay (15s), and may fail under environmental influence.

In 2012, Rajendran et al. in the United States proposed to use Memristor for device authentication. They first use a sensor to collect the voltage of each unit node, and then use the voltage information to authenticate the chip. Because this method needs to use sensors to collect the voltage of each node, the additional circuit overhead is relatively large, and environmental changes will also affect stability.

Contents of the invention

In order to overcome the deficiencies of the above-mentioned prior art, the present invention provides a physical non-clonable authentication method using the error rate distribution of the storage unit of the spin torque transfer random reader (STT-RAM), at a very small hardware cost and time cost , solve the problem of equipment authentication, and improve the reliability of authentication.

This document defines the following terms:

(1) Error-Least-State: Indicates the environment in which the error rate of the STT-RAM unit is the lowest in the working environment of the present invention. For example, in an environment with an operating voltage of 0.9V-1.1V and an operating temperature of 275K-325K, Error-Least-State indicates an environment with the highest operating voltage and the lowest operating temperature, that is, an environment of (1.1V, 275K).

(2) Error-Most-State: Indicates the environment in which the error rate of the STT-RAM unit is the highest in the working environment of the present invention. For example, in an environment with an operating voltage of 0.9V-1.1V and an operating temperature of 275K-325K, Error-Most-State indicates an environment with the lowest operating voltage and the highest operating temperature, that is, the environment of (0.9V, 325K).

(3) RWR test: that is, read and write read test, which is a method to detect the error rate of the unit. This method first reads unit data, inverts the data and writes it back, and then reads out the data to detect whether the data has changed successfully to detect read and write errors.

(4) EDP: Error-rate Differential Pair (Error-rate Differential Pair), indicating two adjacent units in the STT-RAM array that satisfy the following relationship: In N rounds of RWR tests, the difference between the number of errors that occur between the two units greater than or equal to a given number of times N _th . Through the simulation experiment of the STT-RAM storage array with a size of 1MB and 1T1J, it is proved that the values of N and _Nth should satisfy N= _Nth >=3, and N= _Nth =3 in the embodiment of the present invention.

The principle of the present invention is that the physical unclonable authentication method based on the error rate distribution of the STT-RAM storage unit of the present invention includes three stages: a preprocessing stage, a registration stage and a verification stage. First, record the positions of all EDPs in the STT-RAM array in the pre-processing stage (Pre-process), and then input multiple EDP positions in the enrollment phase (Enrollment Phase), and the chip circuit uses the relative size of the two cell error rates in these EDPs to output Reference output (Reference Response), in the verification phase (Evaluation Phase), reproduce the registration phase again, and finally judge the authenticity of the chip according to the output of the verification phase and the registration phase.

The technical scheme provided by the invention is:

A physical non-clonable authentication method based on STT-RAM storage unit error rate distribution, comprising the following steps in turn:

1) Perform the following operations in the preprocessing stage to obtain the addresses of multiple EDP units:

1.1 In the Error-Least-State and Error-Most-State environments respectively, for each odd address unit, set the address of the unit to Addr, and judge whether the two units whose addresses are Addr and Addr+1 through N rounds of RWR tests constitute the EDP;

1.2 If the above two units constitute an EDP, the addresses EDP_Addr and EDP_Addr+1 of the EDP are obtained;

1.3 Save the EDP_Addr output to the database;

2) Perform the following operations in the registration phase to get the reference output:

2.1 obtain N _sec EDPs in the database obtained in the preprocessing stage, and the counter is set to 0; wherein, N _sec is an even number; the value of N _sec should be greater than or equal to 128, and the value of N _sec is 128 in the embodiment of the present invention ;

2.2 For each EDP, judge whether the two units of EDP_Addr and EDP_Addr+1 have more errors in the R-round RWR test; if EDP_Addr+1 has more errors than EDP_Addr, add 1 to the counter; pass A simulation experiment is carried out on an STT-RAM storage array with a size of 1MB and 1T1J, and it is proved that the value of R should satisfy R>=4, and R=4 in the embodiment of the present invention.

2.3 After traversing N _sec EDPs, compare the number in the counter with half of N _sec , output 1 if greater than or equal to, otherwise output 0;

2.4 Use the output of 2.3 as a reference output and store it in a safe database;

3) Set the number of different results to 0, and perform the following operations in the verification phase to obtain the total number of different results, which is used to verify whether the given device is the same as the device in the registration phase:

3.1 Obtain N _sec EDPs in the database obtained in the preprocessing stage, and set the counter to 0; ensure that the N _sec EDPs have been used as a whole input in the registration stage; the N _sec value is the same as that in step 2.1 The value of N _sec is the same, and the value is 128 in the embodiment of the present invention;

3.2 For each EDP, judge whether the two units of EDP_Addr and EDP_Addr+1 have more errors in the R-round RWR test; if EDP_Addr+1 has more errors than EDP_Addr, add 1 to the counter; The value of R is the same as the value of R in step 2.2, and the value is 4 in the embodiment of the present invention;

3.3 After traversing N _sec EDP_Addr, compare the number in the counter with half of N _sec , and output 1 when it is greater than or equal to, otherwise output 0;

3.4 Compare the output result of 3.3 with the reference output result of step 2.4 in the registration phase, if the two results are different, add 1 to the number of different results;

3.5 Repeat steps 3.1 to 3.4 multiple times to obtain the total number of different results;

3.6 Determine whether the total number of different results in step 3.5 is greater than the set threshold, if greater, determine that the device has not passed the authentication, otherwise the device has passed the authentication.

In the embodiment of the present invention, the above-mentioned physical unclonable authentication method based on the error rate distribution of STT-RAM storage cells is carried out under the environment of operating voltage 0.9V-1.1V and operating temperature 275K-325K, wherein the Error in step 1.1 -Most-State means the environment with the lowest working voltage and the highest working temperature, that is, the environment of (0.9V, 325K); Error-Least-State means the environment with the highest working voltage and the lowest working temperature, that is, the environment of (1.1V, 275K) .

In the above-mentioned physical non-clonable authentication method based on the error rate distribution of STT-RAM storage units, after simulation experiments, step 1.1 is to determine whether the units at two positions constitute an EDP by whether the difference between the number of times errors occur in the two units is greater than or equal to N _th The value of N and _Nth in step 1.1 should satisfy N= _Nth >=3, N= _Nth =3 in the embodiment of the present invention; The value of R in step 2.2 should satisfy R>=4, the present invention In the embodiment, R=4; the value of R in step 3.2 is the same as that in step 2.2; the number of times in step 3.5 is 128, and the threshold in step 3.6 is 23. In the embodiment of the present invention, the value of N _sec in step 2.1 and step 3.1 is 128.

Compared with prior art, the beneficial effect of the present invention is:

Through the physical non-clonable authentication method based on the error rate distribution of the STT-RAM storage unit provided by the present invention, the relative size of the error rate of the two units in the EDP output by the verification stage and the registration stage is used to authenticate the hardware device, which improves the reliability of the authentication. performance, which speeds up the authentication speed and saves hardware overhead.

Description of drawings

Fig. 1 is a flowchart of the preprocessing stage in the embodiment of the present invention.

Fig. 2 is a flowchart of the registration phase in the embodiment of the present invention.

Fig. 3 is a flowchart of the verification phase in the embodiment of the present invention.

Detailed ways

Below in conjunction with accompanying drawing, further describe the present invention through embodiment, but do not limit the scope of the present invention in any way.

This embodiment is certified for one STT-RAM with a size of 1MB and 1T1J, and its working environment is specified as a voltage range of 0.9V-1.1V and a temperature range of 275K to 325K. Utilizing the physical unclonable authentication method based on the error rate distribution of STT-RAM storage units provided by the present invention, the authentication work in this embodiment is divided into three stages—preprocessing stage, registration stage, and verification stage.

A. In the preprocessing stage, perform the following operations:

A1. Under Error-Least-State and Error-Most-State respectively, for each odd address Addr, determine whether the units at Addr and Addr+1 constitute an EDP. The method for judging the EDP is that in the N rounds of RWR tests, the difference between the number of errors of the two units is greater than or equal to N _th , and in this embodiment, both N and N _th are set to 3;

A2. If EDP is formed, output the value of Addr, otherwise continue to detect whether the two units corresponding to the next odd address constitute EDP. ;

A3. Save the output EDP for later use;

B. During the registration phase, perform the following operations:

B1. Input the EDP_Addr obtained in 128 preprocessing stages;

B2. For each EDP_Addr, judge whether the two units of EDP_Addr and EDP_Addr+1 addresses have the most errors in the 4 rounds of RWR tests. If the latter has more errors, the counter is incremented by 1, otherwise it is not added;

B3. After traversing 128 EDP_Addr, compare the number in the counter with 64, output 1 if greater than or equal to, otherwise 0;

B4. Store the output results in a secure database as a reference output for the later authentication stage;

C. In the verification phase, perform the following operations:

C1. Input 128 EDP_Addr to ensure that these 128 EDP_Addr are used as a whole input during the registration phase;

C2. For each EDP_Addr, determine which unit has the most errors in the R-round RWR test of the two units of EDP_Addr and EDP_Addr+1 addresses, if the latter has more errors, add 1 to the counter, otherwise do not add;

C3. After traversing 128 EDP_Addr, compare the number in the counter with 64, output 1 if greater than or equal to, otherwise 0;

C4. Compare the output result with the result of the registration phase;

C5. Repeat steps C1 to C4 for a certain number of times to see how many times the final output is different. If the number of times of difference is greater than 23, it is judged that the chip has not passed the certification, otherwise it has passed the certification.

Fig. 1 is a flowchart of the preprocessing stage in the embodiment of the present invention. Referring to accompanying drawing 1, in the preprocessing stage, the working environment of STT-RAM is at first set to Error-Most-State, namely (0.9V, 325K) environment; Then verify one by one that the unit of odd address Addr and Addr+1 position is in In the 3 rounds of RWR tests, whether the difference between the number of errors Err1 and Err2 at the odd address Addr and Addr+1 is greater than or equal to N _th , and the value of N _th is 3, and if so, store Addr in the database. For example, after 3 rounds of RWR testing, it is found that the units at positions 1 and 2 are wrong 3 times and 0 times respectively, then 1 will be stored in the database. Immediately afterwards, the working environment of STT-RAM is set to Error-Least-State, that is, (1.1V, 275K) environment, and then it is tested whether the Addr in the above database still meets the requirements of Addr and Addr+1 in this environment. The difference between the error times Err1 and Err2 of the unit in the three rounds of RWR tests is greater than or equal to N _th , and the value of N _th is 3. If it is satisfied, Addr will be kept, and if it is not satisfied, Addr will be deleted from the database. For example, under Error-Least-State, it is found that the difference between the number of errors between address 1 and address 2 in 3 rounds of RWR tests is less than 3, then 1 will be removed from the database.

Fig. 2 is a flowchart of the registration phase in the embodiment of the present invention. Referring to Figure 2, in the registration phase, first set the counter Intermediate to 0, and then input 128 Addr obtained in the preprocessing phase and in the database. For each Addr, compare the number of errors of Addr and Addr+1 position units under R (R is 4) rounds of RWR tests. If the number of errors of Addr is greater than Addr+1, then add 1 to the counter Intermediate. After traversing 128 Addr, that is, when Counter=128, compare the value of the counter Intermediate with the size of 64 (half of 128), if it is greater, output 1, otherwise output 0. Finally, the output is stored in a secure database. For example, for 128 Addr, assuming that 67 Addr among them satisfy that Addr has more error times than Addr+1 position unit under 4 rounds of RWR tests, then the final value of the counter is 67. Since 67>64, output 1 to the security database.

Fig. 3 is a flowchart of the verification phase in the embodiment of the present invention. Referring to Fig. 3 , in the verification phase, the counter Intermediate is first set to 0, and then the 128 Addr used as a group input in the registration phase are input. For each Addr, compare the number of errors of Addr and Addr+1 position units under 4 rounds of RWR tests, if the number of errors of Addr is greater than Addr+1, then add 1 to the counter Intermediate. After traversing 128 Addr, that is, when Counter=128, compare the size of the counter with 64, and if it is larger, output 1, otherwise output 0. Finally, compare the output with the corresponding data in the security database, and record the different times HD if they are different. The above steps are repeated 128 times, that is, when Compare_times=128, different times HD are compared with the threshold value 23, and if it is greater than 23, it is judged that the verification fails, otherwise it succeeds. For example, for the tested STT-RAM chip, if the test finds that its output in the verification phase is different from the corresponding output in the security database 25 times, then the verification result is a verification failure, that is, it can be considered that this chip is not a chip in the registration phase.

It should be noted that the purpose of the disclosed embodiments is to help further understand the present invention, but those skilled in the art can understand that various replacements and modifications are possible without departing from the spirit and scope of the present invention and the appended claims of. Therefore, the present invention should not be limited to the content disclosed in the embodiments, and the protection scope of the present invention is subject to the scope defined in the claims.

Claims (8)

1. the physics based on the distribution of STT-RAM storage unit error rate can not clone an authentication method, in turn includes the following steps:

1) perform following operation at pretreatment stage, obtain the address of multiple EDP unit:

1.1 respectively under Error-Least-State and Error-Most-State environment, and for each odd address unit, the address setting this unit is Addr, and whether two unit being Addr and Addr+1 by N wheel RWR test judging unit address form EDP;

If 1.2 said two units form EDP, then obtain address EDP_Addr and EDP_Addr+1 of this EDP;

EDP_Addr output is saved in database by 1.3;

2) performing following operation at registration phase, obtaining with reference to exporting:

2.1 obtain N from database described in step 1.3 _secthe individual EDP obtained at pretreatment stage, is set to 0 by counter; Described N _secfor being more than or equal to the even number of 128;

2.2 for each EDP in step 2.1, and judge that two unit of EDP_Addr and EDP_Addr+1 address are taken turns in RWR test at R, the number of times which unit makes a mistake is more; If EDP_Addr+1 makes a mistake often than EDP_Addr, the counter in step 2.1 adds 1;

2.3 as traversal N _secafter individual EDP, by the number in counter and N _sechalf than size, the number in counter is more than or equal to N _secone half export 1, otherwise export 0;

2.3 Output rusults export as reference by 2.4, deposit in the database of a safety;

3) set the different number of times of result as 0, perform following operation at Qualify Phase, obtain the total degree that result is different, whether identical with the equipment of registration phase for verifying to locking equipment:

3.1 obtain N _seceDP in the database that individual pretreatment stage obtains, is set to 0 by counter; Described N _secindividual EDP is previously used at registration phase as the input of Integratively; Described N _secvalue and step 2.1 in N _secidentical;

3.2 for each EDP in step 3.1, and judge that two unit of EDP_Addr and EDP_Addr+1 address are taken turns in RWR test at R, the number of times which unit makes a mistake is more; If EDP_Addr+1 makes a mistake often than EDP_Addr, the counter in step 3.1 adds 1;

3.3 as the described N of traversal _secafter individual EDP_Addr, by the number in counter and N _sechalf than size, the number in counter is more than or equal to N _secone half export 1, otherwise export 0;

The reference Output rusults of the Output rusults of 3.3 and registration phase step 2.4 is made comparisons by 3.4, if the two result difference, the different number of times of result adds 1;

Repeat step 3.1 to 3.4, obtain the total degree that result is different for more than 3.5 time;

Whether the total degree that in 3.6 determining steps 3.5, result is different is greater than setting threshold value, and as being greater than then, judgment device is not by certification, otherwise equipment passes through certification.

2. physics can not clone authentication method as claimed in claim 1, it is characterized in that, Error-Most-State described in step 1.1 represents that minimum operating voltage is 0.9V, and maximum operating temperature is the environment of 325K; Described Error-Least-State represents that maximum operating voltage is 1.1V, and minimum operating temperature is the environment of 275K.

3. physics can not clone authentication method as claimed in claim 1, it is characterized in that, whether the difference whether forming the number of times that EDP makes a mistake particular by two unit that described element address is Addr and Addr+1 described in step 1.1 is more than or equal to N _thjudge, N _thequal with N described in step 1.1, value is for being more than or equal to 3.

4. physics can not clone authentication method as claimed in claim 3, it is characterized in that, N value described in step 1.1 is 3.

5. physics can not clone authentication method as claimed in claim 1, it is characterized in that, the N in step 2.1 and step 3.1 _secvalue is 128.

6. physics can not clone authentication method as claimed in claim 1, it is characterized in that, described in step 2.2 and step 3.2, the value of R is 4.

7. physics can not clone authentication method as claimed in claim 1, it is characterized in that, is repeatedly 128 times described in step 3.5.

8. physics can not clone authentication method as claimed in claim 1, it is characterized in that, threshold value described in step 3.6 is 23.