CN105426314B - A kind of process mapping method of FPGA memories - Google Patents

Abstract

The present invention relates to a process mapping method of FPGA memory. The method comprises: classifying and encapsulating according to the original information of the logic netlist of the memory to generate a port group set; according to the number of port groups and port group parameters included in the port group set , constructing a memory macro; segmenting the data space and address space of the memory macro according to the resource scale in the target process library to obtain a memory component; the memory component includes function parameters, and the function parameters are specifically: constructing the The port group parameter of the port group of the memory macro; the memory component is expanded by bits and addresses to generate a memory component expansion group; according to each memory component included in the memory component expansion group, the exact matching of the memory component type is performed and performing mapping in a device process mapping library to generate the FPGA memory according to the precisely matched connection relationship of the memory components and the functional parameters.

Description

A Process Mapping Method for FPGA Memory

technical field

The invention relates to the technical field of integrated circuit design in the field of microelectronics, in particular to a process mapping method for Field Programmable Gate Array (Field Programmable Gate Array, FPGA) memory.

Background technique

FPGA is a logic device with abundant hardware resources, powerful parallel processing capability and flexible reconfigurable capability. These features make FPGA more and more widely used in data processing, communication, network and many other fields.

Memory is the basic unit of FPGA, and technology mapping (Technology Mapping) is an important bridge connecting front-end logic synthesis and back-end layout and routing in the process involved in FPGA. At this stage, the process-independent circuit netlist is mapped to the relevant structure of the process library under certain hardware constraints, and the process mapping method directly affects the performance of the FPGA.

Contents of the invention

The invention provides a process mapping method of an FPGA memory, which can realize the process mapping of an FPGA memory supporting multiple scales, multiple read-write modes and multiple ports.

The embodiment of the present invention provides a process mapping method of FPGA memory, comprising:

Classify and encapsulate according to the original information of the memory logic netlist to generate a port group set;

Constructing a memory macro according to the number of port groups included in the port group set and port group parameters;

Segment the data space and address space of the memory macro according to the resource scale in the target process library to obtain a memory component; the memory component includes functional parameters, and the functional parameters are specifically: constructing a port group of the memory macro The port group parameters;

bit-extending and address-extending the memory components to generate a memory component expansion group;

performing precise matching of memory component types according to each memory component included in the memory component expansion group;

According to the precisely matched connection relationship of the memory components and the functional parameters, mapping is performed in a device process mapping library to generate the FPGA memory.

Preferably, according to the number of port groups included in the port group set and port group parameters, constructing a memory macro includes:

determining whether the number of port groups is 1 or 2;

If it is 1, construct a single-port memory macro according to the port group parameter;

If it is 2, construct a full dual-port memory macro or a pseudo-dual-port memory macro according to the port group parameters; wherein, when the port group parameters of the two port groups are read-only, or one is read-only and the other is read-write Constructing a full dual-port memory macro; when the port group parameter of one port group is write-only and the port group parameter of the other port group is read-only, construct a pseudo-dual-port memory macro;

If the number of the port groups is 3 or more, pair the port groups in the port group set according to the preset dual-port read-write mode pairing rules, and construct a full dual-port memory according to the successfully paired port groups A macro or a pseudo-dual-port memory macro constructs a single-port memory macro based on an unpaired port group.

Further preferably, the pairing of the port groups in the port group set according to the preset dual-port read-write mode pairing rules is specifically:

Pairing the port groups whose port group parameters are read-only with the port group parameters whose port group parameters are read-write in turn, until all the port groups whose port group parameters are read-write are paired, or the port group parameters are only The read port groups are all paired;

When the unpaired port group parameters are still read-only port groups, pair the unpaired port group parameters with read-only port groups with the port group parameters for write-only port groups in turn, until all port groups whose port group parameters are write-only are paired, or all port groups whose port group parameters are read-only are paired;

When there are still unpaired port groups whose parameters are read-only, pair the unpaired port groups whose parameters are read-only.

Preferably, the data space and address space of the memory macro are segmented according to the resource scale in the target process library, and the memory components obtained are specifically:

calculating the size of the memory macro according to the data depth and address width of the memory macro;

In the target process library, obtain a component type with a resource scale larger than and closest to the memory macro scale as the primary split component type, or obtain a component type with a resource scale equal to the memory macro scale as the primary split component type ;

Divide the memory macro according to the type of the initial division component to construct a memory component.

Further preferably, when the size of all resources in the target process library is smaller than the macro-scale of the memory, the method further includes:

Obtain the component type with the largest resource scale in the target process library as the initial split component type.

Further preferably, the exact matching includes:

calculating a first cost for constructing the memory component by using the primary slicing component type;

Obtaining other component types in the target process library that are smaller than the resource scale of the initial segmentation component type;

Calculate the cost of constructing the memory component by using other component types in turn, wherein the smallest cost is the second cost;

When the second cost is less than the first cost, the component type corresponding to the second cost is used as the optimal component type for constructing the memory component;

Otherwise, the initial split component type is used as the optimal component type for constructing the memory component.

The process mapping method of the FPGA memory provided by the embodiment of the present invention generates a port group set by classifying and encapsulating the original information of the memory logic netlist; according to the port group quantity and port group parameters included in the port group set, the memory is constructed Macro; segment the data space and address space of the memory macro according to the resource scale in the target process library to obtain the memory component; after accurately matching the type of the memory component, and then according to the connection of the precisely matched memory component The relationship and the functional parameters are mapped in a device process mapping library to generate the FPGA memory, thereby realizing a process mapping method for an FPGA memory that supports multiple scales, multiple read-write modes, and multiple ports.

Description of drawings

Fig. 1 is the flow chart of the technology mapping method of the FPGA memory that the embodiment of the present invention provides;

FIG. 2 is a schematic diagram of a port group assembly pin provided by an embodiment of the present invention;

FIG. 3 is a flowchart of a method for constructing a memory macro provided by an embodiment of the present invention;

FIG. 4 is a flow chart of a method for splitting a memory component provided by an embodiment of the present invention;

FIG. 5 is a flowchart of a method for precise matching of memory components provided by an embodiment of the present invention.

Detailed ways

The technical solutions of the present invention will be described in further detail below with reference to the accompanying drawings and embodiments.

FIG. 1 is a flow chart of a process mapping method for an FPGA memory provided by an embodiment of the present invention. As shown in Figure 1, the method includes the following steps:

Step 110, classifying and encapsulating according to the original information of the memory logic netlist, and generating a port group set;

Specifically, when performing FPGA process mapping, the original information of the logic netlist needs to be input first. For the original information of the input logic netlist, it is classified and packaged to generate a set of related pins and parameter settings with the address pin as the main key, that is, in the form of a port group. The port group set refers to a set of multiple port groups accessing the same memory. The port group set may be shown in FIG. 2 , in which PORT GROUP 0 is the first port group in the port group set, and PORT GROUPi is the i+1th port group in the port group set.

Port groups in a port group collection have the same template class, and they have the same pin architecture.

Each port group has some port group parameters, which can be specifically shown in Table 1 below in an example.

Port Group Parameters parameter eigenvalue synchronous mode output register, address register control signal chip enable, write enable, read enable, reset enable read-write conflict mode Read First, Write Through, Hold, Bypass Data output port reset value >=0

Table 1

Taking the set of port groups shown in Figure 2 as an example, each port group includes a clock signal pin CLK, a chip select signal pin EN, a write enable signal pin WE, a reset signal pin RST, and a data input signal pin DIN (data width), address signal pin ADDR (address depth) and data output signal pin DOUT.

It should be noted that the characteristic values of the parameters of the port groups in the port group set may be different.

Step 120, constructing a memory macro according to the number of port groups included in the port group set and port group parameters;

Specifically, the memory macro is characterized by a port mode, and all port groups in the port group set are divided according to the read/write enable and address pins, and the logical layer encapsulation is obtained by pairing. Port modes can be specifically classified into: single-port, pseudo-dual-port, full-dual-port and multi-port.

The concrete method of constructing memory macro can be shown in Figure 3, comprises the following steps:

Step 301, determine whether the number of the port group is 1;

If it is 1, execute step 302; otherwise execute step 303;

Step 302, when the number of port groups is 1, construct a single-port memory macro according to the port group parameters.

Step 303, determining whether the number of the port groups is 2;

If it is 2, execute step 304; otherwise execute step 307;

Step 304, when the number of port groups is 2, determine whether the port group parameters of the two port groups are both read-only or one read-only and one read-write;

Step 305, if the port group parameters of the two port groups are read-only or one is read-only and the other is read-write, construct a full dual-port memory macro according to the port group parameters;

Step 306, if the port group parameter of one port group is write-only and the port group parameter of the other port group is read-only, construct a pseudo dual-port memory macro according to the port group parameters;

Step 307, when the number of port groups is 3 or more, pair the port groups in the port group set according to the preset dual-port read-write mode pairing rules, and construct a full dual-port memory according to the successfully paired port groups A macro or a pseudo-dual-port memory macro constructs a single-port memory macro based on an unpaired port group.

Specifically, if there are at least 3 port groups in the port group set, it is necessary to classify the port groups first, traverse all port groups in the port group set, and sort all port groups according to the readable Write, read-only, and write-only parameter attributes are divided into read-write port group sub-sets, read-only port group sub-sets, and write-only port group sub-sets. Then, pair the port groups in all subcollections.

The pairing follows certain matching rules, as shown in Table 2 below.

Table 2

Moreover, the two matching port groups need to be two port groups accessing the same memory.

In a specific example, the matching process can be specified as:

Select a port group in the read-only port group sub-set in turn, first pair a port group in the read-only port group sub-set with a port group in the read-write port group sub-set, if the pairing is successful, the paired The two port groups are respectively removed from the read-only port group subset and the read-write port group subset, and a full dual-port memory macro is constructed from the paired two port groups until the read-write port group subset The port groups in are all paired, or the port groups in the read-only port group subset are all paired.

After the above pairing process is completed, if there are still unpaired port groups in the read-only port group sub-set, the unpaired port groups in the read-only port group sub-set are sequentially compared with the port groups in the write-only port group sub-set For pairing, if the pairing is successful, the two successfully paired port groups are respectively removed from the read-only port group sub-set and the write-only port group sub-set, and a pseudo dual-port memory macro is constructed according to the paired two port groups. Until all the port groups in the write-only port group subset are paired, or all the port groups in the read-only port group subset are paired.

After the above pairing process is completed, if there are still unpaired port groups in the read-only port group subset, pair the unpaired port group parameters into read-only port groups for pairwise pairing. Also, a full dual-port memory macro is constructed from paired two port groups. Until there are no port groups that can be paired.

After the above pairing process is completed, a single-port memory macro is constructed from the remaining unpaired port groups.

Step 130, segmenting the data space and address space of the memory macro according to the resource scale in the target process library to obtain memory components;

Specifically, the memory component is obtained by dividing the data space and address space of the memory macro according to the resource scale of the target process library, and is a logical layer package that can be matched to the target process library. The memory component includes function parameters, specifically, the function parameters are: port group parameters of the port groups that construct the memory macro.

The resource of the target process library may include various components, such as block storage, distributed storage, etc., and each component may have multiple sizes. For example, the block memory can be 5K, 9K, 18K, etc., and the distributed memory can be 32×2S, 32×2D, 32×2T, 32×2Q, etc.

For the memory macro constructed in the previous step, which has a certain macro scale, the threshold can be set by using the size scale of the components of the target process library resource to determine the first time to divide the data space and address space of the memory macro. Segment component type, segment according to the initial component type, and then perform optimal component type matching. Specifically as shown in Figure 4, it includes the following steps:

Step 401, calculating the size of the memory macro according to the data depth and address width of the memory macro;

Step 402, determining whether there is a component whose size scale is larger than the memory macro scale in the target process library;

Step 403, if it exists, obtain a component type whose size is equal to, or larger than and closest to the macroscale of the memory, as the initial split component type;

Step 404, if it does not exist, obtain the component type with the largest size in the target process library as the initial segmentation component type;

Step 405, split the memory macro according to the type of the initial split component, and construct the memory component.

Step 140, expand the memory component by bit and address to generate a memory component expansion group;

Specifically, in the aforementioned port group set, the address depth and data width have been specified. After the memory component is determined, it is necessary to perform address expansion and bit expansion according to the address depth and data width, so that the address depth and data width of the memory component expansion group The data width corresponds to the memory macro constructed by the port group set.

For example, if the address depth of the port group set is 2K, the address depth of the memory component determined in the previous step is 1K, and the data width is 18bit, then in terms of address depth, the memory component needs to be expanded to two, and gated by EN , one of the memory components is gated for access when EN is high, and the other memory component is gated for access when EN is low.

According to the methods described in the above specific examples, the memory components can be expanded according to the parameters of the port group set, and an extended set of memory components corresponding to the port group set can be constructed.

Step 150, according to each storage component included in the storage component expansion group, perform exact matching of the storage component type;

Specifically, for each storage component included in the extended group, exact matching of component types may be performed. The specific steps are as follows:

Step 501, calculating the first cost of constructing the memory component by using the component type of the primary division;

Step 502, obtaining other component types in the target process library that are smaller than the resource scale of the initial split component type;

Step 503, sequentially calculating the manufacturing cost of constructing memory components using the other component types, wherein the smallest manufacturing cost is the second manufacturing cost;

The above step 501 may be performed after step 502 or 503, or may be performed in parallel with step 502 or 503.

Step 504, judging whether the first cost is higher than the second cost;

Step 505, when the first cost is higher than the second cost, use the component type corresponding to the second cost as the optimal component type for constructing the memory component;

Step 506, otherwise, take the initial split component type as the optimal component type for constructing the memory component.

The optimal component type is also the final determined memory component.

The optimal component type is determined for each storage component included in the expansion group, so as to obtain each storage component finally determined in the expansion group.

Step 160 , according to the connection relationship of the precisely matched memory components in the extended group of memory components and the functional parameters, perform mapping in a device process mapping library to generate the FPGA memory.

Specifically, for the mapping from memory components to memory entities, the connections may follow different configuration relationship rules. When the FPGA memory is constructed according to the extended group of memory components, information of different component selection modes is stored in the constructor, and the corresponding connection relationship configuration is performed according to the different modes selected. And according to the functional parameters, map in the device process mapping library to construct the required FPGA memory.

Through the method provided by the embodiment of the present invention, process mapping of FPGA memories with multiple scales, multiple read-write modes and multiple ports can be supported.

Professionals should further realize that the units and algorithm steps described in conjunction with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the relationship between hardware and software Interchangeability. In the above description, the composition and steps of each example have been generally described according to their functions. Whether these functions are executed by hardware or software depends on the specific application and design constraints of the technical solution. Skilled artisans may use different methods to implement the described functions for each specific application, but such implementation should not be regarded as exceeding the scope of the present invention.

The steps of the methods or algorithms described in connection with the embodiments disclosed herein may be implemented by hardware, software modules executed by a processor, or a combination of both. Software modules can be placed in random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other Any other known storage medium.

The specific embodiments described above have further described the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above descriptions are only specific embodiments of the present invention and are not intended to limit the scope of the present invention. Protection scope, within the spirit and principles of the present invention, any modification, equivalent replacement, improvement, etc., shall be included in the protection scope of the present invention.

Claims (6)

1. a process mapping method of Field Programmable Gate Array FPGA memory, it is characterized in that, described method comprises: Classify and encapsulate according to the original information of the memory logic netlist to generate a port group set; Constructing a memory macro according to the number of port groups included in the port group set and port group parameters; Segment the data space and address space of the memory macro according to the resource scale in the target process library to obtain a memory component; the memory component includes functional parameters, and the functional parameters are specifically: constructing a port group of the memory macro The port group parameters; bit-extending and address-extending the memory components to generate a memory component expansion group; performing precise matching of memory component types according to each memory component included in the memory component expansion group; According to the precisely matched connection relationship of the memory components and the functional parameters, mapping is performed in a device process mapping library to generate the FPGA memory. 2. The method according to claim 1, wherein said constructing a memory macro comprises: determining whether the number of port groups is 1 or 2; If it is 1, construct a single-port memory macro according to the port group parameter; If it is 2, construct a full dual-port memory macro or a pseudo-dual-port memory macro according to the port group parameters; wherein, when the port group parameters of the two port groups are read-only, or one is read-only and the other is read-write Constructing a full dual-port memory macro; when the port group parameter of one port group is write-only and the port group parameter of the other port group is read-only, construct a pseudo-dual-port memory macro; If the number of the port groups is 3 or more, pair the port groups in the port group set according to the preset dual-port read-write mode pairing rules, and construct a full dual-port memory according to the successfully paired port groups A macro or a pseudo-dual-port memory macro constructs a single-port memory macro based on an unpaired port group. 3. The method according to claim 2, wherein the pairing of the port groups in the port group set according to the preset dual-port read-write mode pairing rules is specifically: Pairing the port groups whose port group parameters are read-only with the port group parameters whose port group parameters are read-write in turn, until all the port groups whose port group parameters are read-write are paired, or the port group parameters are only The read port groups are all paired; When there are still unpaired port groups whose parameters are read-only, pair the unpaired port groups whose parameters are read-only with the port groups whose parameters are write-only. until all port groups whose port group parameters are write-only are paired, or all port groups whose port group parameters are read-only are paired; When there are still unpaired port groups whose parameters are read-only, pair the unpaired port groups whose parameters are read-only. 4. The method according to claim 1, wherein the data space and address space of the memory macro are segmented according to the resource scale in the target process library, and the memory components obtained are specifically: calculating the size of the memory macro according to the data depth and address width of the memory macro; In the target process library, obtain resource-scale components greater than or equal to the macro-scale of the memory, and use the resource-scale component type closest to the macro-scale of the memory as the initial split component type; Divide the memory macro according to the type of the initial division component to construct a memory component. 5. The method according to claim 4, wherein, when all resource scales in the target process library are smaller than the macro scale of the memory, the method further comprises: Obtain the component type with the largest resource scale in the target process library as the initial split component type. 6. The method according to claim 4 or 5, wherein the exact matching comprises: calculating a first cost for constructing the memory component by using the primary slicing component type; Obtaining other component types in the target process library that are smaller than the resource scale of the initial segmentation component type; Calculate the cost of constructing the memory component by using other component types in turn, wherein the smallest cost is the second cost; When the second cost is less than the first cost, the component type corresponding to the second cost is used as the optimal component type for constructing the memory component; Otherwise, the initial split component type is used as the optimal component type for constructing the memory component.