CN104617047B - Transistor and preparation method thereof - Google Patents

Abstract

A method for manufacturing a transistor, comprising: providing a substrate, forming a first dummy gate and a first spacer on the substrate; forming a first trench; forming a first stress layer in the first trench; removing the first side Wall, forming a second sidewall on the sidewall of the first dummy gate; forming a second dummy gate on the first stress layer; exposing the substrate between the first stress layers; in the substrate between the first stress layers A second stress layer is formed. The present invention also provides a transistor, including a substrate, a first stress layer, a second stress layer, a source region or a drain region formed on the second stress layer, a gate and a side wall arranged on the substrate. The present invention has the following advantages: by forming the first stress layer around the second stress layer as the source region or the drain region of the transistor, and making the stress direction of the first stress layer opposite to that of the second stress layer, the channel in the transistor can be increased The stress in the region increases the electron mobility of the transistor.

Description

Transistor and method of making the same

technical field

The invention relates to the field of semiconductor manufacturing, in particular to a transistor and a manufacturing method thereof.

Background technique

The performance of metal oxide semiconductor devices (Complementary Metal Oxide Semiconductor, CMOS) can be improved mainly by increasing the gate capacitance of CMOS, increasing carrier mobility or reducing the channel length of the device. The traditional lifting method is to reduce the channel length and the thickness of the gate dielectric layer. This method is called the transistor size reduction method. However, as the size of CMOS devices decreases today, simply reducing the size has been limited by physical limits and equipment costs and cannot achieve the expected performance of the device. Improving the channel carrier mobility has become one of the main ways to further increase the operating speed of the device.

Strained silicon technology can be applied to CMOS devices to improve the performance of the formed metal oxide semiconductor devices, that is, to increase the mobility of carriers in CMOS devices by stretching or compressing the silicon lattice by physical methods, so as to improve The purpose of CMOS device performance.

For example, applying tensile stress (Tensilestress) in the channel region of an N-type metal oxide semiconductor (NMOS) device can improve electron mobility in the NMOS device. Similarly, applying compressive stress to the channel region of a P-type metal oxide semiconductor (PMOS) device can also increase the mobility of holes in the PMOS device.

At this point, how to further increase the stress in the channel region of the CMOS device has become an urgent problem to be solved by those skilled in the art.

Contents of the invention

The problem to be solved by the present invention is to provide a transistor and its manufacturing method, so as to improve the carrier mobility in the channel region of the transistor, and further optimize the performance of the transistor.

In order to solve the above problems, the present invention provides a method for manufacturing a transistor, comprising:

Provide the substrate,

forming a first dummy gate and a first sidewall on the sidewall of the first dummy gate on the substrate;

Using the first sidewall as a mask, forming first trenches in the substrate on both sides of the first dummy gate;

forming first stress layers in the first trenches on both sides of the first dummy gate;

removing the first spacer, and forming a second sidewall on the sidewall of the first dummy gate;

forming a second dummy gate on the first stress layer exposed by the second spacer;

removing the first dummy gate to expose a portion of the substrate between the first stress layers;

forming a second stressor layer in a portion of the substrate between the first stressor layers, the second stressor layer providing a stress of the opposite type to the stress provided by the first stressor layer;

A source region or a drain region is formed in the second stress layer.

Optionally, in the step of providing the substrate, the substrate is a silicon substrate.

Optionally, in the step of forming the first dummy gate, silicon is used as a material for the first dummy gate.

Optionally, in the step of forming the first sidewall, the first sidewall is a silicon nitride sidewall or a silicon oxide sidewall.

Optionally, in the step of forming the first groove, the first groove is a Σ-shaped groove.

Optionally, dry etching and wet etching are used to form the Σ-shaped trench.

Optionally, the wet etching uses tetramethylammonium hydroxide as an etchant.

Optionally, in the step of forming the first stress layer, the first stress layer is formed by selective epitaxial growth.

Optionally, in the step of forming the second sidewall, the second sidewall is a silicon nitride or silicon oxide sidewall.

Optionally, in the step of forming the second dummy gate, silicon is used as a material for the second dummy gate.

Optionally, in the step of forming the second dummy gate, the second dummy gate is formed by selective epitaxial growth.

Optionally, in the step of removing the first dummy gate, the first dummy gate is removed by selective etching.

Optionally, the step of forming the second stress layer includes:

removing a portion of the substrate between the first stressor layers to form a second trench;

The second stress layer is formed in the second trench.

Optionally, the substrate is removed by selective etching.

Optionally, in the step of forming the second stress layer, the second stress layer is formed by selective epitaxial growth.

Optionally, the step of forming the second stress includes:

Ion doping is performed on the portion of the substrate between the first stress layers to form a doped region in the substrate, and the doped region is the second stress layer.

Optionally, the transistor is NMOS, the substrate is a silicon substrate, and carbon ions are used for ion doping to form a second stress layer of silicon carbide material.

Optionally, in the step of forming the first stress layer, the first stress layer is a silicon germanium stress layer; in the step of forming the second stress layer, the second stress layer is a silicon carbide stress layer.

In addition, the present invention also provides a transistor, including:

Substrate;

at least two first stress layers respectively provided in the substrate;

a second stress layer disposed between the first stress layers, the stress provided by the second stress layer is opposite to the type of stress provided by the first stress layer;

formed in the source region or the drain region of the second stress layer;

A gate structure disposed on the substrate, where the gate structure corresponds to the position of the first stress layer.

Optionally, the first stress layer is a silicon germanium stress layer, and the second stress layer is a silicon carbide stress layer.

Compared with the prior art, the technical solution of the present invention has the following advantages:

By forming the first stress layer in the channel region of the transistor, and forming the second stress layer at the position of the source region or the drain region, and making the stress of the second stress layer similar to and opposite to that of the first stress layer, the first stress layer The combination of the first stress layer and the second stress layer can increase the stress of the channel region in the transistor, thereby improving the carrier mobility of the transistor.

Further, the Σ-shaped trench can be better formed by dry etching and wet etching.

Further, a relatively uniform first stress layer can be formed by adopting the selective epitaxial growth method.

Further, the doped region for forming the second stress layer is formed by ion doping, the second stress layer can be directly formed, and the manufacturing steps are reduced to a certain extent.

Description of drawings

FIG. 1 is a schematic flowchart of an embodiment of a method for manufacturing a transistor of the present invention.

FIG. 2 to FIG. 6 are structural schematic diagrams of transistors in various steps in FIG. 1 .

FIG. 7 is a schematic structural diagram of an embodiment of the transistor of the present invention.

Detailed ways

The present invention firstly provides a method for manufacturing a transistor, by arranging a first stress layer in the source region or drain region, and a second stress layer opposite to the stress type of the first stress layer in the channel region, through the first stress layer Combined with the second stress layer, the stress on the channel region of the transistor is increased, thereby improving the mobility of carriers in the channel region and optimizing the performance of the transistor.

Referring to FIG. 1 , it shows a schematic flow chart of Embodiment 1 of the transistor manufacturing method of the present invention. In the first embodiment, an NMOS device is taken as an example, and the method for manufacturing the NMOS device includes:

Step S1, providing a substrate;

Step S2, forming a first dummy gate and a first sidewall located on the sidewall of the first dummy gate on the substrate;

Step S3, using the first sidewall as a mask to form first trenches in the substrate on both sides of the first dummy gate;

Step S4, respectively forming first stress layers in the first trenches on both sides of the first dummy gate;

Step S5, removing the first spacer, and forming a second sidewall on the sidewall of the first dummy gate;

Step S6, forming a second dummy gate on the first stress layer exposed by the second sidewall;

Step S7, removing the first dummy gate to expose the part of the substrate between the first stress layer;

Step S8, removing the part of the substrate between the first stress layer to form a second trench;

Step S9, forming the second stress layer in the second groove, the stress provided by the second stress layer is opposite to the stress provided by the first stress layer;

Step S10, forming a source region or a drain region in the second stress layer.

Through the above steps, the first trench is defined by setting the first dummy gate, and the first stress layer is formed in the first trench, and the first stress layer is located at the channel region of the transistor; and then through the The second dummy gate defines the second trench, and forms a second stress layer opposite to the stress type of the first trench in the second trench, and the second stress layer is located in the source region of the transistor At the position of the drain region and the first stress layer combined with the second stress layer, the stress of the channel region of the transistor can be increased, thereby increasing the electron mobility of the NMOS device.

In order to make the above objects, features and advantages of the present invention more comprehensible, a specific embodiment 1 of the present invention will be described in detail below in conjunction with the accompanying drawings.

Referring to FIG. 2, step S1 is performed to provide a substrate 100;

In this embodiment, the substrate 100 is a silicon substrate. However, the present invention is not limited thereto, and substrates of other materials may also be used.

Step S2 is continued to form a first dummy gate (Dummy Gate) 110 and a first sidewall 111 located on a sidewall of the first dummy gate 110 on the substrate 100 .

In this embodiment, the first dummy gate 110 is made of the same silicon as the substrate 100, which has the advantage that in subsequent steps, the first dummy gate 110 and part of it can be removed at one time. Substrate 100.

The first spacer 111 is used as a mask layer of the first dummy gate 110 in subsequent steps.

In this embodiment, the first sidewall 111 is made of silicon nitride, but the present invention is not limited thereto, and other materials (such as silicon dioxide, other oxides or nitrides of silicon) can also be used. The material of the first side wall 111 is not limited in the present invention.

Referring to FIG. 3 , step S3 is performed, using the first spacer 111 as a mask to form first trenches 101 a and 101 b in the substrate 100 on both sides of the first dummy gate 110 .

The first trenches 101a and 101b are used to form the first stress layer in subsequent steps.

Since this first embodiment takes an NMOS device as an example, in this embodiment, the first trenches 101 a and 101 b are Σ-shaped trenches.

In this embodiment, forming the Σ-shaped trench further includes the following sub-steps:

Step S31, forming an arc-shaped groove in the substrate 100 by dry etching;

Step S32 , processing the arc-shaped grooves by wet etching to form the Σ-shaped grooves (the first grooves 101 a and 101 b ).

In this embodiment, tetramethylammonium hydroxide (TMAH) is used as an etchant, however, the present invention does not make any limitation thereto.

The above sub-steps are a common method for fabricating Σ-shaped grooves (the first grooves 101 a and 101 b ) in the field, which will not be described in detail in the present invention.

Referring to FIG. 4 , step S4 is performed to form first stress layers 102 a and 102 b in the first trenches 101 a and 101 b on both sides of the first dummy gate 110 , respectively.

Since the first trenches 101 a and 101 b are Σ-shaped trenches, in this embodiment, the first stress layers 102 a and 102 b are silicon germanium (SiGe) stress layers that generate compressive stress.

In this embodiment, the first stress layers 102 a and 102 b are formed by selective epitaxial growth, and a relatively ideal SiGe stress layer can be formed by using this method.

It should be noted that the present invention is not limited thereto, and the SiGe stress layer may also be formed in other ways.

Continuing to refer to FIG. 4 , step S5 is performed to remove the first spacer 111 and form a second spacer 112 on the sidewall of the first dummy gate 110 .

Since the first spacer 111 is used as the mask layer of the first dummy gate 110 in the previous step S3, the edge of the first sidewall 111 is damaged to a certain extent (as shown by the dotted circle in FIG. It is beneficial to be used as a mask for forming the second dummy gate in the subsequent steps. Therefore, the first sidewall 111 is removed, and a relatively complete shape is formed on the sidewall of the first dummy gate 110. The surface of a dummy gate 110 is flush with the second spacer 112 to facilitate subsequent formation of the second dummy gate.

In this embodiment, this step S5 includes the following sub-steps:

Step S51, removing the first side wall 111;

Step S52, covering the first dummy gate 110 with a dielectric layer, and covering the dielectric layer with a mask layer;

Step S53 , patterning the mask layer, and etching the dielectric layer using the patterned mask layer as a mask, so as to form the second spacer 112 .

Since the patterned mask layer has a good protective effect on the dielectric layer, no rounded corners will be formed at the top edge of the formed second sidewall 112, so that the sidewall is substantially perpendicular to the substrate 100 and the top surface The second spacer 112 is substantially flush with the surface of the first dummy gate 110 .

The above sub-steps are only the method adopted in this embodiment, and the present invention does not make any limitation on how to remove the first side wall 111 and form the second side wall 112 .

In addition, in this embodiment, the second sidewall 112 is made of silicon nitride. However, the present invention is not limited thereto, and other materials (such as silicon dioxide, other oxides or nitrides of silicon) may also be used as the material of the second sidewall 112 .

Continuing to refer to FIG. 4 , step S6 is performed to form a second dummy gate 120 on the first stress layers 102 a and 102 b using the second spacer 112 as a mask.

Since the edge of the second sidewall 112 formed in step S5 is not damaged, it is a sidewall whose surface is flush with the surface of the first dummy gate 110 , so the second sidewall 112 and the substrate 100 enclose a relatively vertical opening. In this embodiment, the second dummy gate 120 is formed in the opening by selective epitaxial growth by using the second sidewall 112 as a growth mask, so that an ideal second dummy gate 120 can be formed.

The second dummy gate 120 is made of silicon, but the present invention is not limited thereto.

Referring to FIG. 5 , step S7 is performed to remove the first dummy gate 110 to expose the portion of the substrate 100 between the first stress layers 102 a and 102 b.

In this embodiment, the first dummy gate 110 is removed by selective etching, so as to reduce the impact on surrounding devices.

In this embodiment, before etching the first dummy gate 110 , a mask is also covered over the second dummy gate 120 to prevent the second dummy gate 120 from being affected during the etching process.

Continuing to refer to FIG. 5 , step S8 is performed to remove the part of the substrate 100 between the first stress layers to form the second trench 103 . The second trench 103 is used to form the second stress layer. (Figure 5 only shows the second groove 103 between the first stress layer 102a and 102b)

In this embodiment, the partial substrate 100 is removed by selective etching, so as to reduce the impact on the first stress layers 102 a and 102 b on both sides of the second trench 103 .

Since the first trenches 101a and 101b where the first stress layers 102a and 102b are located are Σ-shaped trenches, the shape of the second trench 103 is the same as that of the first trenches 101a and 101b shown in FIG. A mirror-symmetrical "inverse Σ groove".

It should be noted that the present invention does not limit parameters such as specific etchant and etching ratio, but makes corresponding adjustments according to actual conditions.

Referring to FIG. 6, step S9 is performed to form the second stress layer 104 in the second groove 103, the stress provided by the second stress layer 104 is the same as the stress type provided by the first stress layer 102a and 102b on the contrary.

In this embodiment, since the device to be formed is an NMOS device, the first stress layers 102a and 102b are silicon germanium stress layers that generate compressive stress, and correspondingly, the second stress layer 104 is a carbide layer that generates tensile stress. Silicon (SiC) stress layer.

Step S10 is executed to form a source region or a drain region in the second stress layer 104 .

The manufacturing method of the transistor of the present invention further includes: removing the second dummy gate 120 , and forming a metal gate at the position of the second dummy gate 120 . It is the same as the prior art and will not be repeated here.

The second stress layer 104 is used to form the source region or the drain region of the NMOS device in this embodiment. At this time, the substrate where the first stress layer 102a and 102b are located is used to form the gate. Therefore, the The first stress layer 102a ( 102b ) is located in the channel region of the NMOS device. Since the stress generated by the second stress layer 104 is opposite to the stress type generated by the first stress layer 102a and 102b, the tensile stress of the channel region of the NMOS device can be increased under the joint action of the first stress layer 102a and the second stress layer 104, Furthermore, the electron mobility of the channel region of the NMOS device is improved.

In addition, the present invention also provides another second embodiment:

Steps S1 to S7 of this embodiment are the same as those of the first embodiment. Referring to Figure 6, the difference between the second embodiment and the first embodiment above is that:

In the step of forming the second stress layer, after removing the first dummy gate 110, ion doping is used to form a doped region in the part between the first stress layer 102a and 102b of the substrate, for forming The second stress layer 104 .

In this embodiment, since the first stress layers 102a and 102b formed in the previous steps are silicon germanium stress layers, in order to make the second stress layer 104 be used to provide a stress different from that of the first stress layers 102a and 102b , using carbon as dopant ions to form the second stress layer 104 made of silicon carbide.

It should be noted that the present invention does not limit the doping method.

In addition, referring to FIG. 7, the present invention also provides a transistor, including:

substrate 200;

at least two first stress layers 202a and 202b respectively disposed in the substrate 200;

A second stress layer 204 disposed between the first stress layers 202a and 202b, the type of stress provided by the second stress layer 104 is opposite to the type of stress provided by the first stress layers 202a and 202b;

Formed in the source region or the drain region of the second stress layer 204;

The gate structure 220 provided on the substrate 200, the gate structure 220 corresponds to the position of the first stress layer 202a and 202b; wherein, the gate structure 220 includes: located on the substrate 200 The high-k dielectric layer, the metal gate (not shown in the figure) on the high-k dielectric layer, and the spacer 212 on the sidewalls of the high-k dielectric layer and the metal gate.

It should be noted that the shape of the sidewall 212 is relatively complete, and the surface of the sidewall 212 is flush with the surface of the gate structure 220 .

In this embodiment, taking an NMOS device as an example, the first stress layers 202a and 202b are silicon germanium stress layers, and the second stress layer 204 is a silicon carbide stress layer.

Since the stress provided by the first stress layer 202a and 202b is opposite to the stress type provided by the second stress layer 204, the total stress generated by the first stress layer 202a and 202b and the second stress layer 204 on the channel region of the NMOS device Compared with the existing NMOS device, the size is increased to a certain extent, and the electron mobility in the channel region of the NMOS device is improved.

It should be noted that the transistor structure can be obtained by, but not limited to, the above-mentioned manufacturing method.

It should also be noted that the above-mentioned embodiment is described with an NMOS device as an example, but the present invention is not limited thereto. In other embodiments, the transistor can also be a PMOS device, and correspondingly, the substrate is silicon, and the transistor is located in the trench The first stress layer in the channel region is silicon carbide, and the second stress layer at the position of the source region or the drain region is silicon germanium. The combination of the first stress layer and the second stress layer increases the compressive stress in the channel region of the PMOS device. Those skilled in the art can make corresponding modifications, replacements and deformations to the present invention according to the above-mentioned embodiments.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims (18)

1. a kind of production method of transistor, which is characterized in that including：

Substrate is provided,

The first pseudo- grid and the first side wall on the described first pseudo- grid side wall are formed over the substrate；

Using first side wall as mask, first groove is formed in the substrate of the described first pseudo- grid both sides respectively；

It is respectively formed the first stressor layers in the first groove of the described first pseudo- grid both sides；

First side wall is removed, and the second side wall is formed in the side wall of the described first pseudo- grid；

The second pseudo- grid are formed in first stressor layers that second side wall exposes；

The described first pseudo- grid are removed, part of the substrate between the first stressor layers is exposed；

The second stressor layers, the stress that second stressor layers provide are formed in part of the substrate between the first stressor layers It is opposite with the stress types that first stressor layers provide；

Source region or drain region are formed in second stressor layers.

2. production method as described in claim 1, which is characterized in that in the step of providing substrate, the substrate serves as a contrast for silicon Bottom.

3. production method as described in claim 1, which is characterized in that in the step of forming the first pseudo- grid, described first is pseudo- Grid are using silicon as material.

4. production method as described in claim 1, which is characterized in that in the step of forming the first side wall, first side Wall is silicon nitride spacer or monox lateral wall.

5. production method as described in claim 1, which is characterized in that in the step of forming first groove, first ditch Slot is ∑ type groove.

6. production method as claimed in claim 5, which is characterized in that form the ∑ using dry etching and wet etching Type groove.

7. production method as claimed in claim 6, which is characterized in that the wet etching uses tetramethylammonium hydroxide conduct Etchant.

8. production method as described in claim 1, which is characterized in that in the step of forming the first stressor layers, using selection The mode of property epitaxial growth forms first stressor layers.

9. production method as described in claim 1, which is characterized in that in the step of forming the second side wall, the second side Wall is silicon nitride or monox lateral wall.

10. production method as described in claim 1, which is characterized in that in the step of forming the second pseudo- grid, described second is pseudo- Grid are using silicon as material.

11. production method as described in claim 1, which is characterized in that in the step of forming the second pseudo- grid, using selectivity The mode of epitaxial growth forms the described second pseudo- grid.

12. production method as described in claim 1, which is characterized in that in the step of removing the first pseudo- grid, using selectivity The described first pseudo- grid of method removal of etching.

13. production method as described in claim 1, which is characterized in that formed the second stressor layers the step of include：Described in removal Part of the substrate between the first stressor layers, to form second groove；

Second stressor layers are formed in the second groove.

14. production method as claimed in claim 13, which is characterized in that remove the lining using the method for selective etch Bottom.

15. production method as claimed in claim 13, which is characterized in that in the step of forming the second stressor layers, using choosing The mode of selecting property epitaxial growth forms second stressor layers.

16. production method as described in claim 1, which is characterized in that formed the second stress the step of include：To the substrate Part between the first stressor layers carries out ion doping, and to form doped region in the substrate, the doped region is described Second stressor layers.

17. production method as claimed in claim 16, which is characterized in that the transistor is NMOS, and the substrate serves as a contrast for silicon Bottom carries out ion doping, to form the second stressor layers of carbofrax material using carbon ion.

18. production method as described in claim 1, which is characterized in that in the step of forming the first stressor layers, described first Stressor layers are germanium silicon stressor layers；In the step of forming the second stressor layers, second stressor layers are silicon carbide stressor layers.