CN103730421A - Formation method of CMOS - Google Patents

Abstract

A method for forming a CMOS, comprising: providing a semiconductor substrate, forming a gate structure on the semiconductor substrate; forming an oxide layer covering the gate structure and the semiconductor substrate, forming an oxide layer covering the oxide layer A nitride layer; forming a first barrier layer covering the NMOS region; etching the nitride layer and the oxide layer in the PMOS region to form a PMOS sidewall; using the gate structure and the PMOS sidewall of the PMOS region as a mask, in the PMOS In the semiconductor substrate of the region, a groove is formed in the region where the source region and the drain region are to be formed; the first barrier layer is removed, and silicon germanium material is epitaxially filled in the groove; a second barrier layer covering the PMOS region is formed; The nitride layer and the oxide layer in the NMOS region are etched to form the NMOS sidewalls, and the second barrier layer is removed. In the CMOS forming method of the present invention, there is no leakage current between the source/drain and the gate.

Description

Formation method of CMOS

technical field

The invention relates to the technical field of semiconductors, in particular to a method for forming a CMOS.

Background technique

MOS transistors generate switching signals by regulating the current through the channel region by applying a voltage to the gate. In the existing semiconductor device manufacturing process, in order to improve the performance of the MOS transistor, stress is usually introduced into the channel region of the MOS transistor to increase the carrier mobility. For PMOS transistors, embedded silicon germanium technology (Embedded SiGe Technology) can be used to generate compressive stress in the channel region of the transistor, thereby improving carrier mobility. The so-called embedded silicon germanium technology refers to embedding silicon germanium materials in the regions where the source region and the drain region need to be formed on the semiconductor substrate, and using the lattice mismatch between silicon and silicon germanium (SiGe) to generate compressive stress on the channel region .

The prior art provides a method for forming a CMOS. Please refer to Figure 1, which is a schematic diagram of the process of forming CMOS using embedded silicon germanium technology in the prior art, including:

In step S101 , a semiconductor substrate is provided, and a gate structure is formed on the semiconductor substrate.

Step S102 , forming a silicon oxide layer and a silicon nitride layer covering the gate structure and the semiconductor substrate, and sequentially etching the nitride layer and the oxide layer to form NMOS sidewalls and PMOS sidewalls.

Step S103, forming an epitaxial selection layer (Epitaxy SelectivitV Film) covering the semiconductor substrate and the gate structure. The selective epitaxial layer is usually silicon oxide, and when the silicon germanium layer is subsequently formed using a selective epitaxial process, the silicon germanium material is mainly grown on the silicon material, and less grown on the epitaxial selective layer.

Step S104, forming a barrier layer covering the NMOS region, forming grooves in the semiconductor substrate in the PMOS region where the source region and the drain region are to be formed, and removing the barrier layer. The barrier layer is usually a photoresist layer, which is used to protect the NMOS region from damage during the etching process.

Step S105, epitaxially forming a SiGe layer in the groove. Since the groove is located in the PMOS area where the source region and the drain region are to be formed, and the remaining surface of the semiconductor substrate is covered by the epitaxial selective layer, silicon germanium is selectively grown in the groove to form a Germanium source/drain PMOS.

S106, removing the epitaxial selection layer.

For other methods of forming embedded silicon germanium source/drain PMOS, please refer to the Chinese patent application with publication number CN1870295.

However, in the prior art method of forming an embedded silicon germanium source/drain CMOS, leakage current exists between the source/drain and the gate.

Contents of the invention

The problem solved by the invention is that there is a leakage current between the source/drain and the gate in the embedded silicon germanium source/drain CMOS formed in the prior art.

In order to solve the above problems, the invention provides a method for forming a CMOS, comprising:

A semiconductor substrate is provided, the semiconductor substrate has a PMOS region and an NMOS region, an isolation structure is provided between the PMOS region and the NMOS region; a gate structure is formed in the PMOS region and the NOMS region; and the gate structure is formed to cover the gate structure and the oxide layer of the semiconductor substrate, forming a nitride layer covering the oxide layer; forming a first barrier layer covering the NMOS region; etching the nitride layer and the oxide layer in the PMOS region to form a PMOS sidewall; The gate structure and the PMOS sidewall of the region are masks, and grooves are formed in the semiconductor substrate of the PMOS region where the source region and the drain region are to be formed; the first barrier layer is removed to remove the PMOS sidewall And the nitride layer covering the NMOS area is an epitaxial selection layer, and the silicon germanium material is epitaxially filled in the groove; the second barrier layer covering the PMOS area is formed; the nitride layer and the oxide layer of the NMOS area are etched to form the NMOS side wall, remove the second barrier layer.

Optionally, the formation process of the silicon germanium material is selective epitaxy.

Optionally, the parameters of the selective epitaxy process include: the reaction gas includes silicon source gas and germanium source gas, the silicon source gas is SiH ₄ or SiH ₂ Cl ₂ , and the flow rate is 1 sccm-1000 sccm; the germanium source gas It is GeH ₄ , the flow rate is 1 sccm-1000 sccm; the reaction temperature is 500-800 degrees Celsius; the reaction pressure is 1-100 Torr.

Optionally, the reaction gas of the selective epitaxy process further includes HCl and H ₂ , the flow rate of the HCl is 1 sccm-1000 sccm, and the flow rate of the H ₂ is 0.1 slm-50 slm.

Optionally, the groove is a Sigma-shaped groove, and the Sigma-shaped groove has a protruding tip pointing to the channel region of the transistor in the middle of the groove.

Optionally, the process for forming the Sigma-shaped groove includes:

Plasma etching is performed first, and the parameters of the plasma etching include: the etching gas includes HBr, O ₂ , He, Cl ₂ and NF ₃ , the HBr flow rate is 100-1000 sccm, and the O ₂ flow rate is 2-20 sccm , the flow rate of He is 100-1000 sccm, the flow rate of Cl ₂ is 2-200 sccm, the flow rate of NF ₃ is 2-200 sccm, the etching pressure is 10-200 mTorr, the bias voltage is 0-400 V, and the time is 5-60 seconds;

Then perform wet etching, the wet etching process uses TMAH (tetramethylammonium hydroxide) solution, the temperature of the TMAH solution is 15-70 degrees Celsius, and the time is 20-500 seconds.

Optionally, the isolation structure is a shallow trench isolation structure.

Optionally, the gate structure includes a gate dielectric layer and a gate electrode layer on the gate dielectric layer.

Optionally, after forming the gate structure, a step of performing lightly doped source-drain implantation (LDD: Lightly Doped Drain) and halo implant (Halo Implant) doping in the semiconductor substrate is also included.

Optionally, the material of the oxide layer is silicon oxide, and the material of the nitride layer is silicon nitride.

Optionally, the first barrier layer and the second barrier layer are photoresist layers.

Optionally, the width of the PMOS sidewall is 5nm to 50nm.

Optionally, the width of the NMOS sidewall is 5nm to 50nm.

Compared with the prior art, the present invention has the following advantages:

The method for forming a CMOS provided by an embodiment of the present invention uses the gate structure of the PMOS region and the PMOS sidewall as a mask to form grooves in the semiconductor substrate of the PMOS region where the source region and the drain region are to be formed, Silicon germanium material is epitaxially filled in the groove. Since the material of the PMOS sidewall is silicon nitride, and the silicon nitride material covers the NMOS region, the selectivity window (Selectivity Window) of silicon nitride in the selective epitaxy process of silicon germanium material is larger than that of the prior art The silicon oxide epitaxy selection layer is larger, that is, it is less likely to grow silicon germanium material on the silicon nitride material, which ensures that the silicon germanium material is only grown in the groove during the silicon germanium epitaxy process, and will not grow in the PMOS area. Silicon germanium material is grown in the gate structure region and the NMOS region. In the subsequent step of forming the silicide in the source/drain region, the silicide is only formed in the PMOS source/drain region, and there is no conductive channel between the source/drain and the gate, which prevents leakage current.

Further, in the CMOS forming method provided in the embodiment of the present invention, the first barrier layer covering the NMOS region is formed, the nitride layer and the oxide layer in the PMOS region are etched to form PMOS sidewalls; the first barrier layer covering the PMOS region is formed. The second barrier layer etches the nitride layer and oxide layer in the NMOS area to form NMOS sidewalls. The PMOS sidewalls and NMOS sidewalls are formed by etching processes in different steps. According to process requirements, PMOS sidewalls and NMOS sidewalls of different widths can be obtained by adjusting the etching parameters, and further PMOS sidewalls of different widths can be obtained. PMOS and NMOS source/drains of different widths are obtained from NMOS sidewalls to improve CMOS device performance.

Description of drawings

Fig. 1 is the schematic flow sheet of the formation method of prior art CMOS;

2 to 9 are schematic cross-sectional structure diagrams of different preparation stages in the CMOS formation method of the embodiment of the present invention.

Detailed ways

It can be seen from the background art that in the prior art method of forming an embedded silicon germanium source/drain CMOS, leakage current exists between the source/drain and the gate of the PMOS.

The inventors of the present invention have studied the method of forming embedded silicon germanium source/drain CMOS in the prior art, and found that the prior art uses silicon oxide as the epitaxial selectivity film (Epitaxy Selectivity Film), and the selectivity window (Selectivity Window) of silicon oxide is limited. In the epitaxy process of silicon germanium materials, silicon germanium materials will still be grown on the selective epitaxial layer to form a silicon germanium layer covering the gate structure area of the PMOS area, that is, mushroom defects (Mushroom Defect), and there will be no need in the NMOS area. The region of the epitaxial silicon germanium layer grows silicon germanium material. When the silicon oxide epitaxial selection layer is subsequently removed, since the silicon oxide layer is covered with silicon germanium material, the removal difficulty is increased, resulting in incomplete removal. The remaining silicon germanium material, in the step of forming the source/drain region silicide in the subsequent CMOS preparation process, is easy to react with the metal material to form a silicide, which acts as a conductive channel between the source/drain and the gate, causing leakage current.

The inventors of the present invention also used selective epitaxy to grow silicon germanium materials on silicon oxide substrates formed by thermal oxidation, silicon oxide substrates formed by chemical vapor deposition, and silicon nitride substrates, and found that the oxides formed by thermal oxidation Silicon germanium will grow on the edge of the silicon substrate, and silicon germanium will grow on the surface of the silicon oxide substrate formed by chemical vapor deposition, but no silicon germanium will grow on the silicon nitride substrate. Therefore, when silicon nitride is used as an epitaxial selective layer for silicon germanium selective epitaxy, it has a larger selection window.

Based on the above studies, the inventors of the present invention propose a method for forming a CMOS, including: providing a semiconductor substrate, the semiconductor substrate has a PMOS region and an NMOS region, and an isolation structure is provided between the PMOS region and the NMOS region; The PMOS region and the NOMS region form a gate structure; forming an oxide layer covering the gate structure and the semiconductor substrate, forming a nitride layer covering the oxide layer; forming a first barrier layer covering the NMOS region; Etching the nitride layer and oxide layer in the PMOS region to form a PMOS sidewall; using the gate structure and the PMOS sidewall in the PMOS region as a mask, the source region and the drain region are to be formed in the semiconductor substrate of the PMOS region A groove is formed in the region; the first barrier layer is removed, the PMOS sidewall and the nitride layer covering the NMOS region are used as an epitaxial selection layer, and silicon germanium material is epitaxially filled in the groove; a second layer covering the PMOS region is formed. The second barrier layer: etching the nitride layer and oxide layer in the NMOS area to form NMOS side walls, and removing the second barrier layer.

The specific embodiments will be described in detail below in conjunction with the accompanying drawings, and the above-mentioned purpose and advantages of the present invention will be more clear. It should be noted that the purpose of providing these drawings is to facilitate the understanding of the embodiments of the present invention, and should not be interpreted as undue limitations on the present invention. For clarity, the dimensions shown in the figures are not drawn to scale and may be enlarged, reduced or otherwise changed. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, the present invention can be implemented in many other ways different from those described here, and those skilled in the art can make similar extensions without violating the connotation of the present invention, so the present invention is not limited by the specific embodiments disclosed below.

Referring to FIG. 2 , a semiconductor substrate 200 is provided, the semiconductor substrate 200 has a PMOS region and an NMOS region, and an isolation structure 201 is provided between the PMOS region and the NMOS region.

The semiconductor substrate 200 is used as a working platform for subsequent processes. The semiconductor substrate 200 may be single crystal silicon or single crystal germanium; the semiconductor substrate 200 may also be silicon germanium, gallium arsenide or a silicon-on-insulator substrate (SOI substrate). In this embodiment, the semiconductor substrate 200 is single crystal silicon. The semiconductor substrate 200 has a PMOS region and an NMOS region, the PMOS region has an N-type well region, the NMOS region has a P-type well region, and the PMOS region and the NMOS region are isolated by an isolation structure 201 . In this embodiment, the isolation structure 201 is a shallow trench isolation structure to isolate the active region in the semiconductor substrate 200, the formation method of the shallow trench isolation structure can refer to the existing process, here No longer.

Referring to FIG. 3 , a gate structure 213 is formed in the PMOS region and the NOMS region, and the gate structure 213 includes a gate dielectric layer 212 and a gate electrode layer 211 on the gate dielectric layer 212 .

The material of the gate dielectric layer 212 is silicon oxide or a high K (high dielectric constant) material, and the high K material includes HfO ₂ , HfSiO, HfSiON, HfTaO, HfZrO, Al ₂ O ₃ and ZrO ₂ , the The material of the gate electrode layer 211 is polysilicon or metal, and the metal includes Al, Cu, Ti, Ta, TaN, NiSi, CoSi, TiN, TiAl and TaSiN.

In one embodiment, the gate structure 213 is formed by thermally oxidizing and growing a silicon oxide layer on the surface of the semiconductor substrate 200, then forming a polysilicon layer on the surface of the silicon oxide by chemical vapor deposition, and forming a pattern on the surface of the polysilicon layer. The patterned photoresist layer is used as a mask to etch the polysilicon layer and the silicon oxide layer until the surface of the semiconductor substrate 200 is exposed, and the photoresist layer is removed to form the gate structure 213 .

It should be noted that, usually after forming the gate electrode layer, a hard mask layer will be formed on the surface of the gate electrode layer. The material of the hard mask layer can be silicon nitride. It plays the role of etching stop layer and protective gate electrode layer. According to process conditions, if the gate electrode layer is polysilicon, the hard mask layer will be removed before forming the silicide contact layer of the gate structure; if the gate electrode layer is a metal material, the hard mask layer The film does not need to be removed.

It should also be noted that after the gate structure 213 is formed, the steps of lightly doped source-drain implantation (LDD: Lightly Doped Drain) and halo implantation (HaloImplant) are also included in the semiconductor substrate. The LDD doping suppresses the threshold voltage drift by dispersing the strong electric field pointing to the LDD region along the drain pinch-off region, reduces the leakage current and alleviates the thermal electron effect; the Halo doping can suppress the lowering of the threshold low voltage and reduce the leakage current And enhance the ability to resist hot carriers. The process of forming LDD and Halo doping is well known to those skilled in the art, and will not be repeated here.

Referring to FIG. 4 , an oxide layer (not shown) is formed covering the gate structure 213 and the semiconductor substrate 200 , and a nitride layer 214 is formed covering the oxide layer.

In one embodiment, the material of the oxide layer is silicon oxide, and the formation process is chemical vapor deposition; the material of the nitride layer 214 is silicon nitride, and the formation process is chemical vapor deposition. The oxide layer and the nitride layer are subsequently etched to form gate spacers to protect the gate and isolate the source/drain from the gate. In addition, in the present invention, the nitride layer is subsequently epitaxy The silicon germanium material is used as an epitaxial selective layer.

Referring to FIG. 5 , the first barrier layer 227 covering the NMOS region is formed, and the nitride layer 214 and the oxide layer (not shown) in the PMOS region are etched to form PMOS sidewalls.

In one embodiment, a photoresist layer is coated on the surface of the semiconductor substrate 200, and the first barrier layer 227 covering the NMOS region is formed through steps such as drying, exposure, and development. Using the first barrier layer 227 as a mask, etch the nitride layer 214 and the oxide layer in the PMOS region. The process of etching the nitride layer 214 is plasma etching, and the etching parameters include: the etching gas is CF ₄ (or CHF ₃ ), O ₂ and He, and the flow rate of the CF ₄ (or CHF ₃ ) is 2- 200 sccm, the O ₂ flow rate is 2-500 sccm, the He flow rate is 10-1000 sccm, the etching pressure is 1-200 mTorr, the bias voltage is 50-400 V, and the time is 2-60 seconds. The process of etching the oxide layer is plasma etching, and the etching parameters include: the etching gas is CF ₄ , O ₂ and He, the flow rate of the CF ₄ is 2-200 sccm, and the flow rate of the O ₂ is 2-20 sccm , the He flow rate is 10-500 sccm, the etching gas pressure is 1-200 mTorr, the bias voltage is 50-400 V, and the etching time is 2-60 seconds. Since the plasma etching has very good anisotropy, after the etching is completed, the nitride layer 214 and the oxide layer located on the surface of the semiconductor substrate 200 in the PMOS region and the surface of the gate structure 213 are removed, and the oxide layer located on the surface of the gate structure 213 is removed. The nitride layer 214 and the oxide layer on the side are retained to form a PMOS spacer. The width of the PMOS sidewall is 5nm to 50nm, and the width of the PMOS sidewall can be adjusted according to the deposition thickness of the oxide layer and the nitride layer 214 and the etching process parameters.

Referring to FIG. 6 , using the gate structure 213 and the PMOS sidewall of the PMOS region as a mask, a groove 215 is formed in the semiconductor substrate 200 of the PMOS region where the source region and the drain region are to be formed.

In one embodiment, the shape of the groove 215 is a Sigma shape, and the Sigma-shaped groove has a protruding tip pointing to the channel region of the transistor in the middle of the groove. Please refer to FIG. 6, the Sigma-shaped groove has a protruding tip in the horizontal direction, and when the silicon-germanium material is subsequently filled in the Sigma-shaped groove, the silicon-germanium material fills the entire groove, and the protruding tip of the groove The silicon germanium material at the tip is closer to the channel region of the PMOS transistor, which will introduce greater compressive stress in the channel region.

The process of forming the Sigma-shaped groove is to perform plasma etching first, and the parameters of the plasma etching include: the etching gas includes HBr, O ₂ , He, Cl ₂ and NF ₃ , and the HBr flow rate is 100-1000sccm, O ₂ flow of 2-20sccm, He flow of 100-1000sccm, Cl ₂ flow of 2-200sccm, NF ₃ flow of 2-200sccm, etching pressure of 10-200mTorr, bias voltage of 0-400V, The time is 5-60 seconds; wet etching is performed after plasma etching, the wet etching process uses TMAH (tetramethylammonium hydroxide) solution, the temperature of TMAH is 15-70 degrees Celsius, and the time is 20 ~500 seconds. In other embodiments of the present invention, the wet etching process may also use potassium hydroxide solution or ammonia solution.

Please refer to FIG. 7, remove the first barrier layer, use the PMOS sidewall and the nitride layer covering the NMOS region as the epitaxial selection layer, and epitaxially fill the groove with silicon germanium material to form an embedded silicon germanium source /drain 216. The formation process of the silicon germanium material is selective epitaxy.

After forming a groove in the semiconductor substrate 200 in the PMOS region where the source region and the drain region are to be formed, remove the first barrier layer covering the NMOS region, and fill the groove with silicon germanium material using a selective epitaxial process . The parameters of the selective epitaxy process are: the reaction gas includes silicon source gas and germanium source gas, the silicon source gas is SiH ₄ or SiH ₂ Cl ₂ , and the flow rate is 1 sccm-1000 sccm; the germanium source gas is GeH ₄ , The flow rate is 1 sccm-1000 sccm; the reaction temperature is 500-800 degrees Celsius; the reaction pressure is 1-100 Torr.

In another embodiment of the present invention, the parameters of the selective epitaxy process are: silicon source gas, the silicon source gas is SiH ₄ or SiH ₂ Cl ₂ , and the flow rate is 1 sccm-1000 sccm; germanium source gas, the The germanium source gas is GeH ₄ , with a flow rate of 1 sccm-1000 sccm; HCl gas, with a flow rate of 1 sccm-1000 sccm; H ₂ gas, with a flow rate of 0.1 slm-50 slm; the reaction temperature is 500-800 degrees Celsius; and the reaction pressure is 1-100 Torr.

Filling the silicon germanium material in the groove forms the embedded silicon germanium source/drain 216, because the lattice constant of the silicon germanium material is greater than the lattice constant of the silicon material in the PMOS channel region, the embedded silicon germanium source/drain 216 can be in The channel region of the PMOS introduces compressive stress to improve the carrier mobility of the PMOS.

The embodiment of the present invention adopts PMOS sidewall silicon nitride as the epitaxial selection layer of the selective epitaxial silicon germanium material. Compared with the prior art, no additional silicon oxide epitaxial selection layer needs to be formed, which saves process steps. In addition, compared with silicon oxide, silicon nitride has a larger selection window in the process of selective epitaxy of silicon germanium materials, that is, it is less easy to grow silicon germanium materials on silicon nitride materials, ensuring The silicon germanium material is only grown in the groove, and the silicon germanium material is not grown in the gate structure of the PMOS region and the NMOS region. In the subsequent step of forming the silicide in the source/drain region, the silicide is only formed in the PMOS source/drain region, and there is no conductive channel between the source/drain and the gate, which prevents leakage current.

Referring to FIG. 8 , the second barrier layer 217 covering the PMOS region is formed; the nitride layer 214 and the oxide layer (not shown) in the NMOS region are etched to form NMOS sidewalls.

In one embodiment, a photoresist layer is coated on the surface of the semiconductor substrate 200, and the second barrier layer 217 covering the PMOS region is formed through steps such as drying, exposure, and development. Using the second barrier layer 217 as a mask, etch the nitride layer 214 and the oxide layer in the NMOS region. The process of etching the nitride layer 214 is plasma etching, and the etching parameters include: the etching gas is CF ₄ (or CHF ₃ ), O ₂ and He, and the flow rate of the CF ₄ (or CHF ₃ ) is 2- 200 sccm, the O ₂ flow rate is 2-500 sccm, the He flow rate is 10-1000 sccm, the etching pressure is 1-200 mTorr, the bias voltage is 50-400 V, and the time is 2-60 seconds. The process of etching the oxide layer is plasma etching, and the etching parameters include: the etching gas is CF ₄ , O ₂ and He, the flow rate of the CF ₄ is 2-200 sccm, and the flow rate of the O ₂ is 2-20 sccm , the He flow rate is 10-500 sccm, the etching gas pressure is 1-200 mTorr, the bias voltage is 50-400 V, and the etching time is 2-60 seconds. Due to the good anisotropy of plasma etching, after the etching is completed, the nitride layer 214 and oxide layer located on the surface of the NMOS region semiconductor substrate 200 and the surface of the gate structure 213 are removed, while the oxide layer located on the surface of the gate structure 213 The nitride layer 214 and the oxide layer on both sides are preserved to form NMOS sidewalls. The width of the NMOS sidewall is 5nm to 50nm.

It should be noted that, in the embodiment of the present invention, the NMOS sidewalls and PMOS sidewalls are formed by etching processes in different steps, and NMOS sidewalls and PMOS sidewalls of different widths can be obtained by controlling the etching process, further PMOS and NMOS source/drains of different widths can be obtained through PMOS sidewalls and NMOS sidewalls of different widths to meet the requirements of different processes.

Referring to FIG. 9 , the second barrier layer is removed.

In the subsequent manufacturing process of CMOS, it is necessary to implant the source/drain regions of NMOS and PMOS, form the silicide of the source/drain regions, and also form an interlayer dielectric covering the semiconductor substrate 200, the gate structure 213 and the spacers. layers (not shown) and conductive plugs (not shown) to form metal interconnect structures. The above-mentioned process method can refer to the existing process, and will not be repeated here.

In summary, compared with the prior art, the present invention has the following advantages:

The method for forming a CMOS provided by an embodiment of the present invention uses the gate structure of the PMOS region and the PMOS sidewall as a mask to form grooves in the semiconductor substrate of the PMOS region where the source region and the drain region are to be formed, SiGe material is filled in the groove. Since the material of the sidewall is silicon nitride, the selectivity window (Selectivity Window) of silicon nitride in the selective epitaxy process of silicon germanium material is larger than that of the silicon oxide epitaxial selective layer in the prior art, that is, in silicon nitride It is less easy to grow silicon germanium material in terms of material, which ensures that silicon germanium material is only grown in the groove during the silicon germanium epitaxy process, and silicon germanium material is not grown in the gate structure area and NMOS area of the PMOS area. In the subsequent step of forming the silicide in the source/drain region, the silicide is only formed in the PMOS source/drain region, and there is no conductive channel between the source/drain and the gate, which prevents leakage current.

In the CMOS forming method provided in the embodiment of the present invention, a first barrier layer covering the NMOS region is formed, a nitride layer and an oxide layer in the PMOS region are etched to form PMOS sidewalls; a second barrier layer covering the PMOS region is formed , etch the nitride layer and oxide layer in the NMOS region to form NMOS sidewalls. The PMOS sidewalls and NMOS sidewalls are formed by etching processes in different steps. According to process requirements, PMOS sidewalls and NMOS sidewalls of different widths can be obtained by adjusting the etching parameters, and further PMOS sidewalls of different widths can be obtained. PMOS and NMOS source/drains of different widths are obtained with NMOS sidewalls to improve transistor performance.

Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention, and any person skilled in the art can utilize the methods and techniques disclosed above to analyze the technical aspects of the present invention without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention, which do not depart from the content of the technical solution of the present invention, all belong to the protection of the technical solution of the present invention. scope.

Claims (13)

1. A method for forming CMOS, characterized in that, comprising: A semiconductor substrate is provided, the semiconductor substrate has a PMOS region and an NMOS region, and an isolation structure is provided between the PMOS region and the NMOS region; forming a gate structure in the PMOS region and the NOMS region; forming an oxide layer covering the gate structure and the semiconductor substrate, and forming a nitride layer covering the oxide layer; forming a first barrier layer covering the NMOS region; Etching the nitride layer and oxide layer in the PMOS region to form PMOS sidewalls; Using the gate structure and the PMOS sidewall of the PMOS region as a mask, forming grooves in the semiconductor substrate of the PMOS region where the source region and the drain region are to be formed; removing the first barrier layer, using the PMOS sidewall and the nitride layer covering the NMOS region as an epitaxial selection layer, and epitaxially filling the groove with a silicon germanium material; forming a second barrier layer covering the PMOS region; The nitride layer and the oxide layer in the NMOS region are etched to form NMOS side walls, and the second barrier layer is removed. 2 . The method for forming CMOS according to claim 1 , wherein the formation process of the silicon germanium material is selective epitaxy. 3 . 3. The formation method of CMOS as claimed in claim 2, is characterized in that, the parameter of described selective epitaxy process comprises: reaction gas comprises silicon source gas and germanium source gas, and described silicon source gas is SiH ₄ or SiH ₂ Cl ₂ , the flow rate is 1 sccm-1000 sccm; the germanium source gas is GeH ₄ , the flow rate is 1 sccm-1000 sccm; the reaction temperature is 500-800 degrees Celsius; the reaction pressure is 1-100 Torr. 4. The method for forming CMOS according to claim 3, wherein the reaction gas of the selective epitaxy process further comprises HCl and H ₂ , the flow rate of the HCl is 1 sccm to 1000 sccm, and the flow rate of the H ₂ 0.1slm ~ 50slm. 5. The forming method of CMOS as claimed in claim 1, characterized in that, the groove is a Sigma-shaped groove, and the Sigma-shaped groove has a protruding tip pointing to the transistor channel region in the middle of the groove . 6. The forming method of CMOS as claimed in claim 5, is characterized in that, the process of forming described Sigma-shaped groove comprises: Plasma etching is performed first, and the parameters of the plasma etching include: the etching gas includes HBr, O ₂ , He, Cl ₂ and NF ₃ , the HBr flow rate is 100-1000 sccm, and the O ₂ flow rate is 2-20 sccm , the flow rate of He is 100-1000 sccm, the flow rate of Cl ₂ is 2-200 sccm, the flow rate of NF ₃ is 2-200 sccm, the etching pressure is 10-200 mTorr, the bias voltage is 0-400 V, and the time is 5-60 seconds; Then perform wet etching, the wet etching process uses TMAH solution, the temperature of the TMAH solution is 15-70 degrees Celsius, and the time is 20-500 seconds. 7. The method for forming a CMOS according to claim 1, wherein the isolation structure is a shallow trench isolation structure. 8. The method for forming a CMOS according to claim 1, wherein the gate structure comprises a gate dielectric layer and a gate electrode layer on the gate dielectric layer. 9. The method for forming CMOS according to claim 1, further comprising the steps of lightly doped source and drain implantation and halo doping in the semiconductor substrate after forming the gate structure . 10. The method for forming a CMOS according to claim 1, wherein the material of the oxide layer is silicon oxide, and the material of the nitride layer is silicon nitride. 11. The method for forming a CMOS according to claim 1, wherein the first barrier layer and the second barrier layer are photoresist layers. 12 . The method for forming a CMOS according to claim 1 , wherein the width of the PMOS sidewall is 5 nm to 50 nm. 13 . 13 . The method for forming CMOS according to claim 1 , wherein the width of the NMOS sidewall is 5 nm to 50 nm. 14 .

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