CN104599622A - Dynamic logic circuit, grid driving circuit, display panel and display device - Google Patents
Dynamic logic circuit, grid driving circuit, display panel and display device Download PDFInfo
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Abstract
The invention discloses a dynamic logic circuit, a grid driving circuit, a display panel and a display device. The dynamic logic circuit comprises a shift registering unit and a scanning signal generating unit, and the shift registering unit is arranged to be a dynamic-logic shift registering unit and only comprises two phase inverters, a clock phase inverter and a capacitor. Compared with a shift registering unit of an existing logic circuit, the dynamic logic circuit has the advantages that circuit devices of the shift registering unit are reduced effectively, in other words, one phase inverter and two transistors are omitted relatively to an existing shift registering unit, so that occupation area of the dynamic logic circuit is reduced, a lot of transistors are reduced in the whole grid driving circuit, and requirements on a narrow frame of the display device are met.
Description
Technical Field
The invention relates to the technical field of display, in particular to a dynamic logic circuit, a gate driving circuit, a display panel and a display device.
Background
Nowadays, Display devices mainly include LCD (Liquid Crystal Display) Display devices and OLED (Organic Light-Emitting Display) Display devices, and both Display devices include a gate driving circuit including a multi-stage logic circuit arranged along a direction.
Referring to fig. 1a and 1b, fig. 1a is a schematic diagram of a logic circuit structure of a conventional OLED display device, and fig. 1b is a timing diagram of the logic circuit provided IN fig. 1a, IN which the logic circuit includes a shift register unit 100, a scan signal generating unit 200, a first buffer unit 300, and a second buffer unit 400, the shift register unit 100 includes a first inverter 101, a second inverter 102, a first clock inverter 103, and a second clock inverter 104, the shift register unit 100 outputs a "high-low" level signal with a timing by controlling a first clock signal CK1 and the timing of an input signal IN, and the shift register unit 100 outputs a signal NEXT as an input signal of the first clock inverter IN a logic circuit of a NEXT stage. The shift register unit 100 simultaneously transmits the "high-low" signal to an input terminal of the nand gate of the SCAN signal generating unit 200, and the SCAN signal generating unit 200 outputs a corresponding "high-low" signal according to the timing "low-high" of the second clock signal CK2, and then the driving capability of the signal is increased through the first buffer unit 300 to output the SCAN; in addition, the shift register unit 100 simultaneously transmits the "high/low" signal to the input terminal of the second buffer unit 400, and the second buffer unit 400 increases the driving capability of the signal to provide the OLED display device with the control light emitting signal EMIT. The existing logic circuit has a complex structure, a plurality of devices and a large occupied area, and does not meet the requirement of a narrow frame of a display device.
Disclosure of Invention
In view of this, the present invention provides a dynamic logic circuit, a gate driving circuit, a display panel and a display device, which implement signal output through dynamic logic, and reduce the occupied area of the circuit to meet the requirement of a narrow frame of the display device.
In order to achieve the purpose, the technical scheme provided by the invention is as follows:
a dynamic logic circuit includes a shift register unit and a scan signal generation unit, the shift register unit including:
the scanning circuit comprises a first phase inverter, a clock phase inverter and a storage capacitor, wherein the input end of the clock phase inverter is connected to a trigger signal, the first control end of the clock phase inverter is connected to a first control signal, the second control end of the clock phase inverter is connected to a second control signal, the output end of the clock phase inverter is connected to the first polar plate of the storage capacitor and the input end of the first phase inverter, the second polar plate of the storage capacitor is connected to a high-potential signal, the output end of the first phase inverter is connected to a scanning signal generating unit, and the first control signal and the second control signal are mutually inverse signals.
Correspondingly, the invention also provides a gate drive circuit, which comprises a first-stage dynamic logic circuit to an Nth-stage dynamic logic circuit arranged along a first direction, wherein the dynamic logic circuit is the dynamic logic circuit; wherein,
and the output end of the first phase inverter of the previous-stage dynamic logic circuit along the first direction is connected to the input end of the clock phase inverter of the next-stage dynamic logic circuit, and N is an integer not less than 2.
Correspondingly, the invention also provides a display panel which comprises the grid drive circuit.
Correspondingly, the invention also provides a display device which comprises the display panel.
Compared with the prior art, the technical scheme provided by the invention has at least the following advantages:
the invention provides a dynamic logic circuit, a grid drive circuit, a display panel and a display device, comprising a shift register unit and a scanning signal generating unit, wherein the shift register unit comprises: the scanning circuit comprises a first phase inverter, a clock phase inverter and a storage capacitor, wherein the input end of the clock phase inverter is connected to a trigger signal, the first control end of the clock phase inverter is connected to a first control signal, the second control end of the clock phase inverter is connected to a second control signal, the output end of the clock phase inverter is connected to the first polar plate of the storage capacitor and the input end of the first phase inverter, the second polar plate of the storage capacitor is connected to a high-potential signal, the output end of the first phase inverter is connected to a scanning signal generating unit, and the first control signal and the second control signal are mutually inverse signals.
Compared with the shift register unit of the existing logic circuit, the shift register unit of the invention effectively reduces the circuit components of the shift register unit, namely, reduces one inverter compared with the existing shift register unit, namely, reduces two transistors, further reduces the occupied area of the dynamic logic circuit, reduces a large number of transistors of the whole grid drive circuit, and meets the requirement of a narrow frame of a display device.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1a is a schematic diagram of a logic circuit structure of a conventional OLED display device;
FIG. 1b is a timing diagram of the logic circuit provided in FIG. 1 a;
fig. 2 is a schematic structural diagram of a dynamic logic circuit according to an embodiment of the present disclosure;
fig. 3a is a schematic structural diagram of another dynamic logic circuit provided in an embodiment of the present application;
FIG. 3b is a timing diagram of the dynamic logic circuit provided in FIG. 3 a;
FIG. 4a is a schematic diagram of a dynamic logic circuit according to an embodiment of the present disclosure;
FIG. 4b is a timing diagram of the dynamic logic circuit provided in FIG. 4 a;
FIG. 5a is a schematic diagram of a dynamic logic circuit according to an embodiment of the present disclosure;
FIG. 5b is a timing diagram of the dynamic logic circuit provided in FIG. 5 a;
FIG. 6a is a schematic diagram of a dynamic logic circuit according to an embodiment of the present disclosure;
FIG. 6b is a timing diagram of the dynamic logic circuit provided in FIG. 6 a;
fig. 7 is a schematic structural diagram of another dynamic logic circuit provided in an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As described in the background art, in the conventional logic circuit, the shift register unit includes two inverters and two clock inverters, each inverter includes 2 transistors, and each clock inverter includes 4 transistors, which has a complex structure, a large number of devices, and a large occupied area, and does not meet the requirement of a narrow frame of a display device.
Based on this, the embodiment of the present application provides a dynamic logic circuit, and the dynamic logic circuit provided in the embodiment of the present application is described in detail with reference to fig. 2a to fig. 7.
Referring to fig. 2, a schematic structural diagram of a dynamic logic circuit provided in an embodiment of the present application is shown, where the dynamic logic circuit includes: shift register unit 1 and scanning signal generation unit 2, shift register unit 1 includes:
the scanning circuit comprises a first inverter INV1, a clock inverter CKINV and a storage capacitor C, wherein the input end of the clock inverter CKINV is connected to a trigger signal STV, the first control end of the clock inverter CKINV is connected to a first control signal K1, the second control end of the clock inverter CKINV is connected to a second control signal K2, the output end of the clock inverter CKINV is connected to the first polar plate of the storage capacitor C and the input end of the first inverter INV1, the second polar plate of the storage capacitor C is connected to a high potential signal VGH, the output end of the first inverter INV1 is connected to the scanning signal generating unit 2, and the scanning signal generating unit 2 outputs a scanning signal, wherein the first control signal K1 and the second control signal K2 are mutually inverse signals.
Preferably, the shift register unit 1 includes a second inverter INV 2;
an input end of the second inverter INV2 and a first control end of the clock inverter CKINV are both connected to the first clock signal CK1, and an output end of the second inverter INV2 is connected to a second control end of the clock inverter CKINV; or,
an input end of the second inverter INV2 and a second control end of the clock inverter CKINV are both connected to the first clock signal CK1, and an output end of the second inverter INV2 is connected to the first control end of the clock inverter CKINV.
Referring to fig. 2, a scan signal generating unit provided in an embodiment of the present application includes a transmission gate TG and a transistor T, wherein,
the first control end of the transmission gate TG is connected to a third control signal K3, the third control signal K3 is the same as the input end signal of the first inverter INV1, the second control end of the transmission gate TG is connected to the output end of the first inverter INV1, the input end of the transmission gate TG is connected to the second clock signal CK2, the second end of the transistor T is connected with the output end of the transmission gate TG, the first end of the transistor T is connected to the first signal S1, and the gate of the transistor T is connected to the fourth control signal K4. Alternatively, in the transmission gate provided in the embodiment of the present application, two control terminals of the transmission gate may be connected to the third control signal, and a first control terminal of the transmission gate is connected to the output terminal of the first inverter, that is, the scan signal generating unit includes a transmission gate and a transistor, wherein,
the second control end of the transmission gate is connected to a third control signal, the third control signal is the same as the input end signal of the first inverter, the first control end of the transmission gate is connected to the output end of the first inverter, the input end of the transmission gate is connected to a second clock signal, the second end of the transistor is connected to the output end of the transmission gate, the first end of the transistor is connected to the first signal, the gate of the transistor is connected to a fourth control signal, and the connection relation between the two control ends of the transmission gate in the embodiment of the application needs to be selected according to practical application.
In addition, the type of the transistor provided in the embodiment of the present application is not particularly limited, and needs to be selected according to practical applications, where the transistor is an N-type transistor; a gate of the transistor is connected to the third control signal, a first terminal of the transistor is connected to the first signal, and a second terminal of the transistor is connected to an output terminal of the transmission gate; or, the transistor is a P-type transistor; the gate of the transistor is connected to the output of the first inverter, the first terminal of the transistor is connected to the first signal, and the second terminal of the transistor is connected to the output of the transmission gate.
In the practical application of the dynamic logic circuit, the driving capability of the scan signal output by the scan signal generation unit needs to be improved, in the dynamic logic circuit provided in the embodiment of the present application, the width-to-length ratio of the transistor of the transmission gate of the scan signal generation unit can be set to the preset width-to-length ratio, so as to reduce the resistance of the transmission gate, and further improve the driving capability of the scan signal, that is, the width-to-length ratio of the transistor of the transmission gate is adjusted to meet the preset requirement, and further, the scan signal output by the scan signal generation unit can be directly transmitted to the scan line.
As can be seen from the above, in the embodiment of the present application, the shift register unit is set as a dynamic logic shift register unit, and the shift register unit only includes two inverters, one clock inverter and one capacitor, that is, compared with the existing shift register unit, one inverter is reduced, which is equivalent to reducing two transistors, thereby effectively reducing circuit components of the shift register unit, and further reducing the occupied area of the dynamic logic circuit; in addition, the scan signal generating unit provided by the embodiment of the present application includes a transmission gate and a transistor, which include 4 transistors in total, and the existing nand gate includes 4 transistors, so that it can be seen that the scan signal generating unit provided by the embodiment of the present application also reduces the number of circuit devices, and further reduces the occupied area of the dynamic logic circuit. By adopting the dynamic logic circuit provided by the embodiment of the application, a large number of transistors can be reduced in the whole gate driving circuit, and the narrow frame requirement of the display device is met.
The following describes in detail the operation principle of the dynamic logic circuit provided in the embodiments of the present application with reference to the accompanying drawings, and it should be noted that the dynamic logic circuit provided in the embodiments of the present application is not only applicable to LCD display devices, but also applicable to OLED display devices.
Specifically, first, a dynamic logic circuit in an LCD display device is described, and since a pixel switch in the LCD display device generally uses an N-type thin film transistor, the dynamic logic circuit in the LCD display device provided in the embodiments of the present application is described below with reference to the pixel switch being an N-type thin film transistor:
referring to fig. 3a, a schematic structural diagram of another dynamic logic circuit provided in the present embodiment is shown, where a device structure of the circuit provided in fig. 3a is partially the same as a device structure of the dynamic logic circuit provided in fig. 2, and redundant description is omitted; the difference is that the dynamic logic circuit provided in fig. 3a further includes a third inverter INV3, an input end of the third inverter INV3 is connected to an output end of the first inverter INV1, an output end of the third inverter INV3 is connected to the first control end of the transmission gate TG, that is, the third control signal K3 is an output signal of the third inverter INV 3; in addition, the input end of the second inverter INV2 and the second control end of the clocked inverter CKINV are both connected to the first clock signal CK1, and the output end of the second inverter INV2 is connected to the first control end of the clocked inverter CKINV, i.e. the first control signal K1 is the output signal of the second inverter INV2, and the second control signal K2 is the first clock signal CK 1; for convenience of manufacturing, the transistor T in the scan signal generating unit 2 is also an N-type transistor, wherein the fourth control signal K4 is also an output signal of the third inverter INV3, that is, the output terminal of the third inverter INV3, the first control terminal of the transmission gate TG and the gate of the transistor T are all connected, the first terminal of the transistor T is connected to the first signal S1, wherein the first signal S1 is a low-level signal VGL, and the second terminal of the transistor T is connected to the output terminal of the transmission gate TG to serve as the output terminal of the scan signal generating unit 2;
in addition, the first control end of the clock inverter CKINV is active at low level, and the second control end is active at high level, that is, when the first control end is switched in low level and the second control end is switched in high level, the clock inverter CKINV is equivalent to a common inverter; the first control end of the transmission gate TG is active at a low level, and the second control end of the transmission gate TG is active at a high level, that is, when the first control end is switched in a low level and the second control end is switched in a high level, the transmission gate TG is in an open state.
In conjunction with the dynamic logic circuit structure shown in fig. 3a, and referring to fig. 3b, a timing diagram of the dynamic logic circuit provided in fig. 3a is provided, it should be noted that the trigger signal STV provided in fig. 3b of the present application is an on signal, that is, an on signal provided to an input terminal of a clock inverter of a shift register unit in the first-stage dynamic logic circuit; the trigger signal provided by the input end of the clock inverter of the shift register unit in the dynamic logic circuit of other stage is the same as the output signal of the first inverter in the dynamic logic circuit of the previous stage. When CK1 is at high level, INV2 converts the high level signal of CK1 into low level signal and outputs, CKINV is controlled by the high level signal of CK1 and the low level signal output from INV2 and is equivalent to a common inverter, CKINV converts the high level signal provided by STV into low level signal and outputs; the storage capacitor C stores the low level signal output by the CKINV; INV1 converts the low level signal outputted by CKINV into high level signal and outputs it, wherein, the output signal NEXT of INV1 is used as the trigger signal of the NEXT stage dynamic logic circuit of the display device; the TG is turned on by the control of the high level signal output by the INV1 and the low level signal output by the INV3, and outputs the low level signal corresponding to CK2 at this time, that is, the SCAN signal SCAN is the low level signal at this time;
then CK1 becomes low level, INV2 converts the low level signal of CK1 into high level signal to output, CKINV is controlled according to the low level signal of CK1 and the high level signal output by INV2, and is in high impedance state; the storage capacitor C releases the stored low level signal and inputs the low level signal to the INV 1; the INV1 converts the low level signal into a high level signal and outputs the high level signal; the TG is controlled to be turned on by the high level signal output by the INV1 and the low level signal output by the INV3, and outputs the high level corresponding to CK2 at this time, that is, the SCAN signal SCAN is the high level signal at this time;
finally CK1 becomes high level again, INV2 converts the high level signal of CK1 into low level signal and outputs, CKINV is controlled according to the high level signal of CK1 and the low level signal output by INV2, equivalent to a common inverter, CKINV converts the low level signal provided by STV into high level signal and outputs; INV1 converts the high level signal output by CKINV into low level signal and outputs; TG is turned off by control of a low level signal output by INV1 and a high level signal output by INV 3; the transistor T is turned on by the control of the high signal output from the INV3, and outputs the first signal S1 (i.e., a low signal), i.e., the SCAN signal SCAN is a low signal at this time.
For the dynamic logic circuit of the LCD display device provided in the above embodiment, the third inverter is connected to the first control terminal of the transmission gate, and the second control terminal of the transmission gate is connected to the output terminal of the first inverter; in the dynamic logic circuit of the LCD device provided in the embodiment of the present application, the third inverter may be further connected to the second control terminal of the transmission gate, and the first control terminal of the transmission gate is connected to the output terminal of the first inverter, only a part of the timing sequence needs to be changed, as shown in fig. 4a and 4b, where fig. 4a is a schematic structural diagram of another dynamic logic circuit provided in the embodiment of the present application, fig. 4b is a timing diagram of the dynamic logic circuit provided in fig. 4a, the dynamic logic circuit provided in fig. 4a is partially identical to the dynamic logic circuit provided in fig. 3a, except that the input terminal of the third inverter INV3 is connected to the output terminal of the first inverter INV1, and the output terminal of the third inverter INV3 is connected to the second control terminal of the transmission gate TG, where, as shown in fig. 4b, when CK1 is at high level, INV2 converts the high level signal of CK1 into a low level signal for output, CKINV is controlled by a high level signal of CK1 and a low level signal output by INV2 to be equivalent to a common inverter, and converts the low level signal provided by STV into a high level signal and outputs the high level signal; the storage capacitor C stores the high level signal output by the CKINV; the INV1 converts the high level signal output by the CKINV into a low level signal and outputs the low level signal, wherein, the output signal NEXT of the INV1 is used as a trigger signal of a NEXT stage dynamic logic circuit of the display device; the TG is turned on by the control of the low level signal output by the INV1 and the high level signal output by the INV3, and outputs the low level signal corresponding to CK2 at this time, that is, the SCAN signal SCAN is the low level signal at this time;
then CK1 becomes low level, INV2 converts the low level signal of CK1 into high level signal to output, CKINV is controlled according to the low level signal of CK1 and the high level signal output by INV2, and is in high impedance state; the storage capacitor C releases the stored high-level signal and inputs the high-level signal to the INV 1; the INV1 converts the high level signal into a low level signal and outputs the low level signal; the TG is controlled to be turned on by the low level signal output by the INV1 and the high level signal output by the INV3, and outputs the high level signal corresponding to the CK2 at this time, that is, the SCAN signal SCAN is the high level signal at this time;
finally CK1 becomes high level again, INV2 converts the high level signal of CK1 into low level signal and outputs, CKINV is controlled according to the high level signal of CK1 and the low level signal output by INV2, equivalent to a common inverter, CKINV converts the high level signal provided by STV into low level signal and outputs; INV1 converts the low level signal output by CKINV into high level signal and outputs; TG is turned off by control of a high level signal output by INV1 and a low level signal output by INV 3; the transistor T is turned on by the control of the low signal output from the INV3, and outputs the first signal S1 (i.e., a low signal), i.e., the SCAN signal SCAN is a low signal at this time.
In addition, a dynamic logic circuit in an OLED display device is described, and since a pixel switch in the OLED display device generally uses a P-type thin film transistor, the dynamic logic circuit of the OLED display device provided in the embodiment of the present application is described below with reference to the pixel switch being the P-type thin film transistor:
referring to fig. 5a, a schematic structural diagram of another dynamic logic circuit provided in the present embodiment is shown, where a device structure of the circuit provided in fig. 5a is partially the same as a device structure of the dynamic logic circuit provided in fig. 2, and redundant description is omitted; the difference is that the dynamic logic circuit provided in fig. 5a further includes a third inverter INV3, an input end of the third inverter INV3 is connected to an output end of the first inverter INV1, an output end of the third inverter INV3 is connected to the first control end of the transmission gate TG, that is, the third control signal K3 is an output signal of the third inverter INV 3; in addition, since the OLED display device also needs to output a control light emitting signal EMIT, the dynamic logic circuit includes: an input end of the fourth inverter INV4 is connected to an output end of the third inverter INV3, wherein the connection between the third inverter INV3 and the fourth inverter INV4 is equivalent to a buffer unit, and the driving capability of the signal output by the first inverter INV1 is improved and then the signal is output as a control light emitting signal EMIT;
in addition, an input end of the second inverter INV2 and a first control end of the clocked inverter CKINV are both connected to the first clock signal CK1, and an output end of the second inverter INV2 is connected to a second control end of the clocked inverter CKINV, that is, the first control signal K1 is the first clock signal CK1, and the second control signal K2 is an output signal of the second inverter INV 2; for convenience of manufacturing, the transistor T in the scan signal generating unit 2 is also a P-type transistor, wherein the fourth control signal K4 is an output signal of the first inverter INV1, that is, the output terminal of the first inverter INV1, the second control terminal of the transmission gate TG and the gate of the transistor T are all connected, the first terminal of the transistor T is connected to the first signal S1, wherein the first signal S1 is a high-level signal VGH, and the second terminal of the transistor T is connected to the output terminal of the transmission gate TG to serve as the output terminal of the scan signal generating unit 2;
in addition, the first control end of the clock inverter CKINV is active at low level, and the second control end is active at high level, that is, when the first control end is switched in low level and the second control end is switched in high level, the clock inverter CKINV is equivalent to a common inverter; the first control end of the transmission gate TG is active at a low level, and the second control end of the transmission gate TG is active at a high level, that is, when the first control end is switched in a low level and the second control end is switched in a high level, the transmission gate TG is in an open state.
In conjunction with the dynamic logic circuit structure shown in fig. 5a, and referring to fig. 5b, providing a timing diagram of the dynamic logic circuit shown in fig. 5a, it should be noted that the trigger signal S1 provided in fig. 5b of the present application is an on signal, i.e., an on signal provided to an input terminal of a clock inverter of a shift register unit in the first-stage dynamic logic circuit; the trigger signal provided by the input end of the clock inverter of the shift register unit in the dynamic logic circuit of other stage is the same as the output signal of the first inverter in the dynamic logic circuit of the previous stage. When CK1 is at low level, INV2 converts the low level signal of CK1 into high level signal and outputs, CKINV is controlled by the low level signal of CK1 and the high level signal output by INV2 and is equivalent to a common inverter, CKINV converts the high level signal provided by STV into low level signal and outputs; the storage capacitor C stores the low level signal output by the CKINV; the INV1 converts the low level signal output by the CKINV into a high level signal and outputs the high level signal, wherein, the output signal NEXT of the INV1 is used as a trigger signal of a NEXT stage dynamic logic circuit of the display device, and the output signal of the INV1 is output as an EMIT (control light emitting signal) high level signal after the driving capability is improved by the third inverter INV3 and the fourth inverter INV 4; the TG is turned on by the control of the low level signal output by the INV3 and the high level signal output by the INV1, and outputs the high level signal corresponding to the CK2 at this time, that is, the SCAN signal SCAN is the high level signal at this time;
then CK1 becomes high level, INV2 converts the high level signal of CK1 into low level signal and outputs, CKINV is controlled according to the high level signal of CK1 and the low level signal output by INV2, and is in high impedance state; the storage capacitor C releases the stored low level signal and inputs the low level signal to the INV 1; the INV1 converts the low level signal into a high level signal and outputs the high level signal; the high level signal of the output of the INV1 is output as an EMIT (control light emission signal) high level signal after the driving capability is improved through the INV3 and INV 4; the TG is turned on by the control of the low level signal output by the INV3 and the high level signal output by the INV1, and outputs the low level signal corresponding to the CK2 at this time, that is, the SCAN signal SCAN is the low level signal at this time;
finally CK1 becomes low level again, INV2 converts the low level signal of CK1 into high level signal and outputs, CKINV is controlled according to the low level signal of CK1 and the high level signal output by INV2, equivalent to a common inverter, CKINV converts the low level signal provided by STV into high level signal and outputs; INV1 converts the high level signal output by CKINV into low level signal and outputs; the low level signal of the output of the INV1 is output as an EMIT (control light emission signal) low level signal after the driving capability is improved through the INV3 and INV 4; TG is turned off by control of a high level signal output by INV3 and a low level signal output by INV 1; the transistor T is turned on by the low signal output from the INV1, and outputs the first signal S1 (i.e., a high signal), i.e., the SCAN signal SCAN is a high signal at this time.
For the dynamic logic circuit of the OLED display device provided in the above embodiment, the third inverter is connected to the first control terminal of the transmission gate, and the second control terminal of the transmission gate is connected to the output terminal of the first inverter; in the dynamic logic circuit of the OLED display device provided in the embodiment of the present application, the third inverter may be further connected to the second control terminal of the transmission gate, and the first control terminal of the transmission gate is connected to the output terminal of the first inverter, and only a part of the timing sequence needs to be changed, specifically referring to fig. 6a and 6b, where fig. 6a is a schematic structural diagram of another dynamic logic circuit provided in the embodiment of the present application, fig. 6b is a timing diagram of the dynamic logic circuit provided in fig. 6a, and the dynamic logic circuit provided in fig. 6a is partially identical to the dynamic logic circuit provided in fig. 5a in structure, except that an input terminal of the third inverter INV3 is connected to the output terminal of the first inverter INV1, and an output terminal of the third inverter INV3 is connected to the second control terminal of the transmission gate TG; and, the difference also includes: the dynamic logic circuit shown in FIG. 6a does not require the fourth inverter INV3 shown in FIG. 5a, i.e., the third inverter INV3 is equivalent to a buffer unit, the output signal thereof is the EMIT signal, and the fourth control signal K4 is the output signal of the third inverter INV 3. Wherein, referring to fig. 5b, when CK1 is low level, INV2 converts the low level signal of CK1 into high level signal for output, CKINV is controlled by the low level signal of CK1 and the high level signal output by INV2 and is equivalent to a normal inverter, CKINV converts the low level signal provided by STV into high level signal for output; the storage capacitor C stores the high level signal output by the CKINV; the INV1 converts the high level signal output by the CKINV into a low level signal and outputs the low level signal, wherein, the output signal NEXT of the INV1 is used as a trigger signal of a NEXT stage dynamic logic circuit of the display device, and the output signal of the INV1 is inverted by the third inverter INV3 and the driving capability is improved and then is output as an EMIT (control light emitting signal) high level signal; the TG is turned on by the control of the high level signal output by the INV3 and the low level signal output by the INV1, and outputs the high level signal corresponding to the CK2 at this time, that is, the SCAN signal SCAN is the high level signal at this time;
then CK1 becomes high level, INV2 converts the high level signal of CK1 into low level signal and outputs, CKINV is controlled according to the high level signal of CK1 and the low level signal output by INV2, and is in high impedance state; the storage capacitor C releases the stored high-level signal and inputs the high-level signal to the INV 1; the INV1 converts the high level signal into a low level signal and outputs the low level signal; a low level signal output by the INV1 is inverted by the INV3, and the driving capability is increased, and then the signal is output as an EMIT (control light emission signal) high level signal; the TG is turned on by the control of the high level signal output by the INV3 and the low level signal output by the INV1, and outputs the low level signal corresponding to the CK2 at this time, that is, the SCAN signal SCAN is the low level signal at this time;
finally CK1 becomes low level again, INV2 converts the low level signal of CK1 into high level signal and outputs, CKINV is controlled according to the low level signal of CK1 and the high level signal output by INV2, equivalent to a common inverter, CKINV converts the high level signal provided by STV into low level signal and outputs; INV1 converts the low level signal output by CKINV into high level signal and outputs; a high level signal output by the INV1 is inverted by the INV3, and the driving capability is increased, and then the signal is output as an EMIT (control light emitting signal) low level signal; TG is turned off by control of a low level signal output by INV3 and a high level signal output by INV 1; the transistor T is turned on by the low signal output from the INV3, and outputs the first signal S1 (i.e., a high signal), i.e., the SCAN signal SCAN is a high signal at this time.
It should be noted that the above contents are only a few examples specifically illustrated in the present application for describing the dynamic logic circuit in detail, and in practical applications, each signal in the dynamic logic circuit provided in the present application needs to be designed according to actual situations.
In addition, in consideration of the fact that in practical application, the dynamic logic circuit may have a situation that the potential of each node in the circuit is abnormal due to the fact that a display device has a charge residue when the display device is abnormally powered off or initially started, and further the work of the dynamic logic circuit is abnormal, the dynamic logic circuit provided in the embodiment of the present application further includes: and the reset unit is used for resetting the dynamic logic circuit before the dynamic logic circuit is scanned.
Specifically, referring to fig. 7, a schematic structural diagram of another dynamic logic circuit provided in an embodiment of the present application is shown, where the dynamic logic circuit structure in fig. 7 includes all circuit structures of the dynamic logic circuit in fig. 2, where fig. 7 provides the dynamic logic circuit, and further includes: and a control terminal of the reset unit 3 is connected to the fifth control signal K5, an input terminal of the reset unit 3 is connected to the reset signal S2, and an output terminal of the reset unit 3 is connected to an input terminal of the first inverter INV 1. The reset unit 3 provided in the embodiment of the present application may be a transistor T ', and the type of the transistor T ' is not particularly limited, wherein a gate of the transistor T ' is connected to the fifth control signal K5, a first end of the transistor T ' is connected to the reset signal S2, a second end of the transistor T ' is connected to an input end of the first inverter INV1, and the reset signal S2 is transmitted to the dynamic logic circuit through the control of the fifth control signal K5, so as to reset the dynamic logic circuit.
It should be noted that the reset signal provided in the embodiment of the present application is mainly used to control the transistor in the scan signal generating unit to be turned on, so that the transistor transmits the first signal to the display device, so as to reset the dynamic logic circuit before the dynamic logic circuit scans; the reset signal may be a high-level signal or a low-level signal, and needs to be specifically designed according to the type of the transistor and a path through which the reset signal is transmitted to the control terminal of the transistor, which is not specifically limited in the embodiment of the present application.
Correspondingly, the embodiment of the application also provides a gate driving circuit, which comprises a first-stage dynamic logic circuit to an Nth-stage dynamic logic circuit arranged along a first direction, wherein the dynamic logic circuit is the dynamic logic circuit; wherein,
and the output end of the first phase inverter of the previous-stage dynamic logic circuit along the first direction is connected to the input end of the clock phase inverter of the next-stage dynamic logic circuit, and N is an integer not less than 2.
Correspondingly, the embodiment of the application also provides a display panel, and the display panel comprises the gate driving circuit.
Correspondingly, the embodiment of the application also provides a display device which comprises the display panel.
The dynamic logic circuit, the gate driving circuit, the display panel and the display device provided by the embodiment of the application comprise a shift register unit and a scanning signal generating unit, wherein the shift register unit comprises: the scanning circuit comprises a first phase inverter, a clock phase inverter and a storage capacitor, wherein the input end of the clock phase inverter is connected to a trigger signal, the first control end of the clock phase inverter is connected to a first control signal, the second control end of the clock phase inverter is connected to a second control signal, the output end of the clock phase inverter is connected to the first polar plate of the storage capacitor and the input end of the first phase inverter, the second polar plate of the storage capacitor is connected to a high-potential signal, the output end of the first phase inverter is connected to a scanning signal generating unit, and the first control signal and the second control signal are mutually inverse signals.
As can be seen from the above, in the embodiment of the present application, the shift register unit is set as a dynamic logic shift register unit, and the shift register unit includes only two inverters, one clock inverter and one capacitor, compared with the shift register unit of the existing logic circuit, the technical solution provided in the embodiment of the present application effectively reduces circuit components of the shift register unit, that is, one inverter is reduced compared with the existing shift register unit, which is equivalent to reducing two transistors, and further reduces the occupied area of the dynamic logic circuit, so that the whole gate driving circuit reduces a large number of transistors, and meets the narrow frame requirement of the display device.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (12)
1. A dynamic logic circuit comprising a shift register unit and a scan signal generating unit, wherein the shift register unit comprises:
the scanning circuit comprises a first phase inverter, a clock phase inverter and a storage capacitor, wherein the input end of the clock phase inverter is connected to a trigger signal, the first control end of the clock phase inverter is connected to a first control signal, the second control end of the clock phase inverter is connected to a second control signal, the output end of the clock phase inverter is connected to the first polar plate of the storage capacitor and the input end of the first phase inverter, the second polar plate of the storage capacitor is connected to a high-potential signal, the output end of the first phase inverter is connected to a scanning signal generating unit, and the first control signal and the second control signal are mutually inverse signals.
2. The dynamic logic circuit of claim 1, wherein the shift register cell comprises a second inverter;
the input end of the second inverter and the first control end of the clock inverter are both connected to a first clock signal, and the output end of the second inverter is connected to the second control end of the clock inverter; or,
the input end of the second inverter and the second control end of the clock inverter are both connected to a first clock signal, and the output end of the second inverter is connected to the first control end of the clock inverter.
3. The dynamic logic circuit of claim 1, wherein the scan signal generation unit comprises a transmission gate and a transistor, wherein,
the first control end of the transmission gate is connected to a third control signal, the third control signal is the same as the signal of the input end of the first inverter, the second control end of the transmission gate is connected to the output end of the first inverter, the input end of the transmission gate is connected to a second clock signal, the second end of the transistor is connected with the output end of the transmission gate, the first end of the transistor is connected to the first signal, and the grid of the transistor is connected to a fourth control signal.
4. The dynamic logic circuit of claim 3, further comprising: and the input end of the third inverter is connected to the output end of the first inverter, and the output end of the third inverter is connected to the first control end of the transmission gate.
5. The dynamic logic circuit of claim 4, wherein the dynamic logic circuit comprises: a fourth inverter, an input of the fourth inverter being connected to an output of the third inverter.
6. The dynamic logic circuit of claim 1, wherein the scan signal generation unit comprises a transmission gate and a transistor, wherein,
the second control end of the transmission gate is connected to a third control signal, the third control signal is the same as the signal of the input end of the first inverter, the first control end of the transmission gate is connected to the output end of the first inverter, the input end of the transmission gate is connected to a second clock signal, the second end of the transistor is connected with the output end of the transmission gate, the first end of the transistor is connected to the first signal, and the grid of the transistor is connected to a fourth control signal.
7. The dynamic logic circuit of claim 6, further comprising: and the input end of the third inverter is connected to the output end of the first inverter, and the output end of the third inverter is connected to the second control end of the transmission gate.
8. The dynamic logic circuit of claim 3 or 6, wherein the transistors are N-type transistors; wherein a gate of the transistor is connected to the third control signal, a first terminal of the transistor is connected to the first signal, and a second terminal of the transistor is connected to an output terminal of the transmission gate;
or, the transistor is a P-type transistor; wherein a gate of the transistor is connected to an output of the first inverter, a first terminal of the transistor is connected to the first signal, and a second terminal of the transistor is connected to an output of the transmission gate.
9. The dynamic logic circuit of claim 1, further comprising: and the control end of the reset unit is connected to a fifth control signal, the input end of the reset unit is connected to a reset signal, and the output end of the reset unit is connected to the input end of the first phase inverter.
10. A gate driving circuit comprising first to nth stages of dynamic logic circuits arranged in a first direction, the dynamic logic circuits being as claimed in any one of claims 1 to 9; wherein,
and the output end of the first phase inverter of the previous-stage dynamic logic circuit along the first direction is connected to the input end of the clock phase inverter of the next-stage dynamic logic circuit, and N is an integer not less than 2.
11. A display panel comprising the gate driver circuit according to claim 10.
12. A display device characterized by comprising the display panel according to claim 11.
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Effective date of registration: 20210929 Address after: No.8, liufangyuan Henglu, Donghu New Technology Development Zone, Wuhan City, Hubei Province Patentee after: WUHAN TIANMA MICROELECTRONICS Co.,Ltd. Patentee after: Wuhan Tianma Microelectronics Co.,Ltd. Shanghai Branch Patentee after: Tianma Micro-Electronics Co.,Ltd. Address before: Room 509, building 1, No. 6111, Longdong Avenue, Pudong New Area, Shanghai, 201201 Patentee before: SHANGHAI TIANMA AM-OLED Co.,Ltd. Patentee before: Tianma Micro-Electronics Co.,Ltd. |