CN103985361A - Grid driving circuit and control method thereof, and liquid crystal display - Google Patents
Grid driving circuit and control method thereof, and liquid crystal display Download PDFInfo
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Abstract
The invention provides a grid driving circuit and a control method thereof, and a liquid crystal display. The grid driving circuit comprises multiple shift register units. The shift register units comprise first latch registers, second latch registers, third latch registers, first NAND circuits, second NAND circuits, third NAND circuits and fourth NAND circuits. The output ends of the first latch registers are respectively connected with the input ends of the first NAND circuits and the input ends of the second NAND circuits; the output ends of the third latch registers are respectively connected with the input ends of the third NAND circuits and the input ends of the fourth NAND circuits; the input ends of the second latch registers are connected with the output ends of the first latch registers, and the output ends of the second latch registers are connected with the input ends of the third latch registers; and the shift register units are successively connected, and the output end of the third latch register of a previous shift register unit is connected with the input end of the first latch register of a later shift register unit.
Description
Technical field
The present invention relates to LCD Technology field, particularly a kind of gate driver circuit and control method thereof and liquid crystal display.
Background technology
Along with the development of semiconductor science and technology, flat-panel screens product also rises thereupon.In the middle of numerous flat-panel screens, liquid crystal display (Liquid Crystal Display), based on the advantage such as its low-power consumption, low radiation, lightweight and volume be little, has become the main flow of display product.
Liquid crystal display generally comprises source electrode drive circuit, gate driver circuit and display panels, wherein, display panels generally comprises M bar sweep trace and N bar data line, every row (column) sweep trace connects all pixels of same row (column), every row (OK) data line connects all pixels of same row (OK), the corresponding M row (column) of M bar sweep trace pixel, the corresponding N row of N bar data line (OK) pixel, has M * N pixel on display panels.Source electrode drive circuit and gate driver circuit are carried data-signal and sweep signal to data line and sweep trace respectively, in order to drive pixel.Accordingly, gate driver circuit generally comprises M level, in each level of a frame period inner grid driving circuit, all exports a sweep signal.Each level of gate driver circuit comprises a latch, a Sheffer stroke gate and an impact damper.
Please refer to Fig. 1, the part-structure block diagram that it is gate driver circuit of the prior art.As shown in Figure 1, in gate driver circuit 10 in the prior art, the latch 11 of the 1st grade is subject to clock signal ckv3 to control output shift signal next1, the Sheffer stroke gate 12 of the 1st grade is exported and the impact damper 13 of non-result of calculation to the 1st grade after receiving shift signal next1 and clock signal ckv1, thus a sweep signal Gout1 of impact damper 13 outputs of the 1st grade.The latch 21 of the 2nd grade is subject to clock signal ckv1 to control output shift signal next2, the Sheffer stroke gate 22 of the 2nd grade is exported and the impact damper 23 of non-result of calculation to the 2nd grade after receiving shift signal next2 and clock signal ckv3, the impact damper 23 of the 2nd grade is exported a sweep signal Gout2 thus, same, the latch 31 of 3rd level is subject to clock signal ckv3 to control output shift signal next3, the Sheffer stroke gate 32 of 3rd level is exported and the impact damper 33 of non-result of calculation to 3rd level after receiving shift signal next3 and clock signal ckv1, the impact damper 33 of 3rd level is exported a sweep signal Gout3 thus, by that analogy, clock signal ckv1 or ckv3 according to reception at different levels export a sweep signal Gout successively.
Visible, a sweep signal Gout of every grade of output in gate driver circuit, exporting a sweep signal Gout just needs a latch, a Sheffer stroke gate and an impact damper.Common, gate driver circuit has a hundreds of even thousands of level, and therefore, the Area comparison of gate driver circuit is large.
Development along with high definition HD display and full HD (FHD) display, pixel in display panels in unit area can get more and more, the quantity of sweep trace also can increase thereupon, accordingly, the sweep signal Gout of gate driver circuit output also can increase, and increase a sweep signal Gout of output and just need to increase a latch, a Sheffer stroke gate and an impact damper.The area of gate driver circuit also can be increasing, becomes the obstacle of narrow frame design.
And the shift signal next pulse width of latch equals the cycle of a clock signal ckv in the gate driver circuit of prior art, the dutycycle of clock signal ckv is less than 1:4.Please refer to Fig. 2, the portion waveshape simulation drawing that it is gate driver circuit of the prior art.As shown in Figure 2, the pulse of a shift signal next only covers a clock signal ckv signal, and remainder has all been wasted.
Base this, how to solve the excessive narrow frame design that affects liquid crystal display of the area of gate driver circuit in prior art, simultaneously the very little problem of signal waste that causes of the dutycycle of clock signal has become the technical matters that those skilled in the art need solution badly.
Summary of the invention
The object of the present invention is to provide a kind of gate driver circuit and control method thereof and liquid crystal display device, to solve the excessive narrow frame design that affects liquid crystal display of area of existing gate driver circuit, the very little problem that causes signal waste of the dutycycle of while clock signal.
For solving the problems of the technologies described above, the invention provides a kind of gate driver circuit, described gate driver circuit comprises: a plurality of shift register cells; Described shift register cell comprises the first latch, the second latch, the 3rd latch, the first NAND circuit, the second NAND circuit, the 3rd NAND circuit and the 4th NAND circuit; The output terminal of described the first latch is connected with the input end of the second NAND circuit with the input end of described the first NAND circuit respectively; The output terminal of described the 3rd latch is connected with the input end of the 4th NAND circuit with the input end of described the 3rd NAND circuit respectively; The input end of described the second latch is connected with the output terminal of described the first latch, and the output terminal of described the second latch is connected with the input end of described the 3rd latch; Described shift register cell connects successively, and the output terminal of the 3rd latch of previous shift register cell is connected with the input end of the first latch of a rear shift register cell.
The present invention also provides a kind of liquid crystal display, and described liquid crystal display comprises: display panels, source electrode drive circuit and two gate driver circuits as above;
Described display panels comprises multi-strip scanning line and many signal line, and described source electrode drive circuit is connected with described many signal line, and described two gate driver circuits lay respectively at the relative both sides of described display panels and are connected with described multi-strip scanning line.
The present invention also provides a kind of control method of gate driver circuit, and the control method of described gate driver circuit comprises:
The first latch, the second latch, the 3rd latch are exported respectively shift signal according to clock signal;
The first NAND circuit, the second NAND circuit, the 3rd NAND circuit and the 4th NAND circuit receive respectively shift signal and clock signal output and non-result of calculation;
Impact damper is according to described and non-result of calculation difference output scanning signal.
The present invention also provides a kind of liquid crystal display, and described liquid crystal display comprises above-mentioned gate driver circuit.
In gate driver circuit provided by the invention and control method and liquid crystal display, the first latch and the 3rd latch carry out and non-calculating with two clock signals respectively, add the second latch in order to push shift signal simultaneously, thereby realized the type of drive that monolock is deposited dual output, by 3 latchs, just can export 4 sweep signals thus, saved 1 latch, therefore the area of reduction of gate driving circuit effectively, simultaneously, the shift signal of described gate driver circuit can cover 4 clock signals, increases the dutycycle of clock signal.
Accompanying drawing explanation
Fig. 1 is the part-structure block diagram of gate driver circuit of the prior art;
Fig. 2 is the portion waveshape simulation drawing of gate driver circuit of the prior art;
Fig. 3 is the part-structure block diagram of the gate driver circuit of the embodiment of the present invention;
Fig. 4 is the circuit structure diagram of the latch of the embodiment of the present invention;
Fig. 5 is the circuit structure diagram of the Sheffer stroke gate of the embodiment of the present invention;
Fig. 6 is the circuit structure diagram of the impact damper of the embodiment of the present invention;
Fig. 7 is the portion waveshape simulation drawing of the gate driver circuit of the embodiment of the present invention;
Fig. 8 is the structured flowchart of the liquid crystal display of the embodiment of the present invention.
Embodiment
Gate driver circuit the present invention being proposed below in conjunction with the drawings and specific embodiments and control method thereof and liquid crystal display are described in further detail.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only in order to convenient, the object of the aid illustration embodiment of the present invention lucidly.
Please refer to Fig. 3, the part-structure block diagram of its gate driver circuit that is the embodiment of the present invention.As shown in Figure 3, described gate driver circuit 100 comprises: a plurality of shift register cells 50; Described shift register cell 50 comprises the first latch 101, the second latch 201, the 3rd latch 301, the first Sheffer stroke gate 102, the second Sheffer stroke gate 202, the 3rd Sheffer stroke gate 302 and the 4th Sheffer stroke gate 402; The output terminal of described the first latch 101 is connected with the input end of the second Sheffer stroke gate 202 with the input end of described the first Sheffer stroke gate 102 respectively; The output terminal of described the 3rd latch 301 is connected with the input end of the 4th Sheffer stroke gate 402 with the input end of described the 3rd Sheffer stroke gate 302 respectively; The input end of described the second latch 201 is connected with the output terminal of described the first latch 101, and the output terminal of described the second latch 201 is connected with the input end of described the 3rd latch 301; Described shift register cell 50 connects successively, and the output terminal of the 3rd latch 301 of previous shift register cell 50 is connected with the input end of the first latch 101 of a rear shift register cell 50.
Concrete, described shift register cell 50 comprises the first latch 101, the second latch 201 and the 3rd latch 301, described the second latch 201 is between described the first latch 101 and described the 3rd latch 11, the input end of the second latch 201 is connected with the output terminal of described the first latch 101, and the output terminal of the second latch 201 is connected with the input end of described the 3rd latch 301.
Described shift register cell 50 also comprises 4 impact dampers, the output terminal of the first Sheffer stroke gate 102, the second Sheffer stroke gate 202, the 3rd Sheffer stroke gate 302 and the 4th Sheffer stroke gate 402 is connected with an impact damper respectively, described 4 impact dampers are respectively the first impact damper 103, the second impact damper 203, the 3rd impact damper 303 and the 4th impact damper 403, export respectively 4 sweep signals.
Visible, the shift register cell 50 in the present embodiment comprises 3 latchs, 4 Sheffer stroke gates and 4 impact dampers.
To respectively latch, Sheffer stroke gate and impact damper be elaborated below.
Latch comprises that the circuit structure of the first latch 101, the second latch 201 and the 3rd latch 301 comprises 2 phase inverters and 2 clocked inverters.The particular circuit configurations of latch please refer to Fig. 4, the circuit structure diagram of its latch that is the embodiment of the present invention.As shown in Figure 4, described latch comprises phase inverter 51, phase inverter 52, clocked inverter 53 and clocked inverter 54, the output terminal of phase inverter 51 connects the input end of clocked inverter 53 and clocked inverter 54, the output terminal of clocked inverter 53 connects the input end of phase inverter 52 and clocked inverter 54, the output terminal of phase inverter 52 is connected with the output terminal of clocked inverter 54, wherein, phase inverter 51, the input end of clocked inverter 53 and clocked inverter 54 all accesses real-time sequential signal ckv, the input end of clocked inverter 53 accesses a high level Vin, output terminal output shift signal next by phase inverter 52.
Sheffer stroke gate comprises that the particular circuit configurations of the first Sheffer stroke gate 102, the second Sheffer stroke gate 202, the 3rd Sheffer stroke gate 302, the 4th Sheffer stroke gate 402 please refer to Fig. 5, the circuit structure diagram of its Sheffer stroke gate that is the embodiment of the present invention.As shown in Figure 5, described Sheffer stroke gate is comprised of a N-type transistor and a P transistor npn npn, and the two ends of N-type transistor and P transistor npn npn are connected respectively high level Vin1 and low level Vin2.What deserves to be explained is, in the present embodiment, NAND circuit comprises being all Sheffer stroke gates, be one of the present invention and preferred embodiment but be not limited to this, as long as can realize with the logical circuit of non-calculating, be all feasible, be all within protection scope of the present invention.
Impact damper comprises that the circuit structure of the first impact damper 103, the second impact damper 203, the 3rd impact damper 303 and the 4th impact damper 403 comprises odd number phase inverter 55, described odd number phase inverter 55 bases and non-result of calculation output scanning signal.The particular circuit configurations of impact damper please refer to Fig. 6, the circuit structure diagram of its impact damper that is the embodiment of the present invention.As shown in Figure 6, described impact damper comprises 3 phase inverters 55, and the output of previous phase inverter 55 connects the input of a rear phase inverter 55, and 3 phase inverters 55 connect successively.In impact damper, by the input end of the 1st phase inverter 55, inputted and non-result of calculation IN, by the output terminal output scanning signal Gout of the 3rd phase inverter 55.
Continuation is with reference to figure 3 and Fig. 7, and in described gate driver circuit 50, described the first latch 101, the second latch 201 and the 3rd latch 301 are controlled output shift signal next by clock signal ckv.Described clock signal ckv comprises the first clock signal ckv1, the second clock signal ckv2, the 3rd clock signal ckv3 and the 4th clock signal ckv4.Wherein, described the first latch 101 is controlled by the 4th clock signal ckv4, and described the second latch 201 is controlled by the second clock signal ckv2 or the 3rd clock signal ckv3, and described the 3rd latch 301 is controlled ckv1 by the first clock signal.
As shown in Figure 7, the rising edge of respectively corresponding the 4th clock signal ckv4 of the rising edge of the shift signal next1 that described the first latch defeated 101 goes out and negative edge; The rising edge of the rising edge of the shift signal next2 of described the second latch 201 outputs and negative edge corresponding the second clock signal ckv2 of difference or the 3rd clock signal ckv3; The rising edge of the shift signal next3 of described the 3rd latch 301 outputs and negative edge be the rising edge of corresponding the first clock signal ckv1 respectively.
Wherein, the negative edge time of described the first clock signal ckv1 is corresponding with the rising time of the second clock signal ckv2, and free interval; The negative edge time of described the second clock signal ckv2 is corresponding with the rising time of the 3rd clock signal ckv3, and free interval; The negative edge time of described the 3rd clock signal ckv3 is corresponding with the rising time of the 4th clock signal ckv4, and free interval; The negative edge time of described the 4th clock signal ckv4 is corresponding with the rising time of the first clock signal ckv1, and free interval.And the pulse width of described shift signal (next1, next2 and next3) is more than or equal to the pulse width sum of described the first clock signal ckv1, the second clock signal ckv2, the 3rd clock signal ckv3 and the 4th clock signal ckv4.
After described the first latch 101 output shift signal next1 finish, described the 3rd latch 301 starts to export shift signal next3.In this process, described the second latch 201 is for pushing shift signal.
Accordingly, the present invention also provides a kind of control method of gate driver circuit, and the control method of described gate driver circuit comprises the following steps:
The first latch 101, the second latch 201 and the 3rd latch 30 are exported respectively shift signal next according to clock signal;
The first Sheffer stroke gate 102, the second Sheffer stroke gate 202, the 3rd Sheffer stroke gate 302, the 4th Sheffer stroke gate 402 receive respectively shift signal next and clock signal ckv output and non-result of calculation;
Impact damper is according to described and non-result of calculation difference output scanning signal Gout.
Concrete, described the first latch 101, the second latch 201 and the 3rd latch 301 are controlled output shift signal next by clock signal.Described clock signal comprises the first clock signal ckv1, the second clock signal ckv2, the 3rd clock signal ckv3 and the 4th clock signal ckv4, described the first latch 101 is controlled by the 4th clock signal ckv4, described the second latch 201 is controlled by the second clock signal ckv2 or the 3rd clock signal ckv3, and described the 3rd latch 301 is controlled by the first clock signal ckv1.
The rising time of shift signal next and negative edge time are all subject to the control of clock signal, wherein, the rising edge of the rising edge of the shift signal next1 of described the first latch 101 outputs and respectively corresponding the 4th clock signal ckv4 of negative edge, the rising edge of the rising edge of the shift signal next2 of described the second latch output and negative edge corresponding the second clock signal ckv2 of difference or the 3rd clock signal ckv3, the rising edge of the shift signal next3 of described the 3rd latch 301 outputs and negative edge be the rising edge of corresponding the first clock signal ckv1 respectively.
Wherein, in 4 clock signals, two clock signals (ckv4 and ckv1) are controlled the first latch 101 and the 3rd latch 301.Simultaneously, the first Sheffer stroke gate 102, the second Sheffer stroke gate 202, the 3rd Sheffer stroke gate 302 and the 4th Sheffer stroke gate 402 receive respectively 4 clock signals (ckv1, ckv2, ckv3 and ckv4), and carry out and non-calculating with shift signal next1 or the next3 of the first latch 101 and the 3rd latch 301 outputs.
After the shift signal next1 of first Sheffer stroke gate 102 reception the first latch 101 outputs and the first clock signal ckv1, carry out and non-calculating, and export result of calculation to the first impact damper 103, thus a sweep signal Gout1 of the first impact damper 103 outputs; Shift signal next1 and the 3rd clock signal ckv3 that the second Sheffer stroke gate 202 receives the first latch 101 outputs carry out and non-calculating, and export result of calculation to the second impact damper 203, thus a sweep signal Gout3 of the second impact damper 203 outputs; Shift signal next3 and the second clock signal ckv2 that the 3rd Sheffer stroke gate 302 receives the 3rd latch 301 outputs carry out and non-calculating, and export result of calculation to the three impact dampers 303, thus a sweep signal Gout6 of the 3rd impact damper 303 outputs; Shift signal next3 and the 4th clock signal ckv4 that the 4th Sheffer stroke gate 402 receives the 3rd latch 301 outputs carry out and non-calculating, and export result of calculation to the four impact dampers 403, thus a sweep signal Gout8 of the 4th impact damper 403 outputs.
In the shift register cell 50 of the embodiment of the present invention, the second latch 201 is for pushing shift signal next.Please refer to Fig. 7, the portion waveshape simulation drawing of its gate driver circuit that is the embodiment of the present invention.As shown in Figure 7, the shift signal next1 of the shift signal next2 of the second latch 201 outputs and the first latch 101 outputs overlaps each other in high level period, the shift signal next2 of the shift signal next3 of the 3rd latch 301 outputs and the second latch 201 outputs overlaps each other in high level period, and the first latch 101 completes the output shift signal next3 that the 3rd latch 301 starts output afterwards of shift signal next1.Visible, the shift signal next of the first latch 101 outputs pushes to the shift signal next of the 3rd latch 301, the three latch 301 output next cycles via the second latch 201.
In the present embodiment, the pulse width of described shift signal (next1, next2 and next3) is all more than or equal to the pulse width sum of described the first clock signal ckv1, the second clock signal ckv2, the 3rd clock signal ckv3 and the 4th clock signal ckv4.Please continue to refer to Fig. 7, as shown in Figure 7, in 4 clock signals, the negative edge time of the first clock signal ckv1 is corresponding with the rising time of the second clock signal ckv2, and free interval, the negative edge time of the second clock signal ckv2 is corresponding with the rising time of the 3rd clock signal ckv3, and free interval, the negative edge time of the 3rd clock signal ckv3 is that the rising time of the 4th clock signal ckv4 is corresponding, and free interval, the negative edge time of the 4th clock signal ckv4 is corresponding with the rising time of the first clock signal ckv1, and free interval, the pulse width of shift signal next covers 4 clock signal ckv.Visible, shift signal next is fully utilized, and the dutycycle of clock signal ckv is very large.
Described gate driver circuit 100 comprises in a plurality of shift register cell 50(Fig. 3 not shown a plurality of), described a plurality of shift register cell 50 connects successively, and the output terminal of the 3rd latch 301 of previous shift register cell 50 is connected with the input end of the first latch 101 of a rear shift register cell 50.
The shift signal next3 of the 3rd latch 301 outputs of previous shift register cell 50 offers the first latch 101 of a rear shift register cell 50, the first latch 101 of a rear shift register cell 50 is subject to be controlled by the 4th clock signal ckv4 equally, the first latch 101 of a rear shift register cell 50 is according to the 4th clock signal ckv4 output shift signal next4, the first Sheffer stroke gate 102 of a rear shift register cell 50 receives shift signal next4 and the first clock signal ckv1 of the first latch 101 outputs of a rear shift register cell 50, and output and non-result of calculation to a rear shift register cell 50 the first impact damper 103, thus, a sweep signal Gout9 of the first impact damper 103 outputs of a rear shift register cell 50.
Same, the second Sheffer stroke gate 202 of a rear shift register cell 50 receives shift signal next4 and the 3rd clock signal ckv3 of the first latch 101 outputs of a rear shift register cell 50, and output and non-result of calculation is to the second impact damper 203 of a rear shift register cell 50, a sweep signal Gout11 of the second impact damper 203 outputs thus; The 3rd Sheffer stroke gate 302 of a rear shift register cell 50 receives shift signal next6 and the second clock signal ckv2 of the 3rd latch 301 outputs of a rear shift register cell 50, and output and non-result of calculation is to the 3rd impact damper 303 of a rear shift register cell 50, a sweep signal Gout14 of the 3rd impact damper 303 outputs thus; The 4th Sheffer stroke gate 402 of a rear shift register cell 50 receives shift signal next6 and the 4th clock signal ckv4 of the 3rd latch 301 outputs of a rear shift register cell 50, and output and non-result of calculation is to the 4th impact damper 403 of a rear shift register cell 50, a sweep signal Gout16 of the 4th impact damper 403 outputs thus.
Visible, in described gate driver circuit 100, the first latch 101 and the 3rd latch 301 carry out and non-calculating with two clock signals respectively, realize monolock and deposit the type of drive of dual output, simultaneously, the shift signal next of the first latch 101 outputs is pushed to the 3rd latch 301 by the second latch 201, the shift signal next of the 3rd latch 301 output next cycles, the shift signal next of the 3rd latch 301 outputs can be used as the input of the first latch 101 of next shift register cell 50.So, a plurality of shift register cell 50 transmits shift signal next output scanning signal Gout successively.Therefore, described gate driver circuit 100 can be realized the cross complementary driving of left and right sides driving circuit.
The concrete quantity of shift register cell 50 is to determine according to the resolution of liquid crystal display, if the liquid crystal display of high definition (HD) pattern, its resolution is 720 * 1280, in gate driver circuit 100, the quantity of shift register cell 50 is 180, within a frame period, gate driver circuit 100 is sequentially exported 720 sweep signal Gout, and 720 sweep signals are sequentially provided to the sweep trace of display panels.The liquid crystal display of full HD if (FHD) pattern, its resolution is 1080 * 1920, in gate driver circuit 100, the quantity of shift register cell 50 is 270, within a frame period, gate driver circuit 100 is sequentially exported 1080 sweep signal Gout, and 1080 sweep signals are sequentially provided to the sweep trace of display panels.
Because 3 latchs of 50 need of a shift register cell just can be exported 4 sweep signals, the latch gate driver circuit 10 more of the prior art that the sweep signal Gout of gate driver circuit 100 output equal numbers adopts is few.For the liquid crystal display of high definition (HD) pattern, 540 latchs of 100 needs of gate driver circuit just can be exported 720 sweep signal Gout.For the liquid crystal display of full HD (FHD) pattern, 810 latchs of 100 needs of gate driver circuit just can be exported 1080 sweep signal Gout.Liquid crystal display adopts one-sided driving, and gate driver circuit 10 more of the prior art has reduced respectively by 190 and 270 latchs.
And the gate driver circuit 100 that the embodiment of the present invention provides, by impact damper output scanning signal Gout, therefore, has good driving force.
At present, in order to reduce the manufacturing cost of liquid crystal display and to use the object that realizes narrow frame, the general direct gate driver circuit that forms on display panels in manufacture process.Display panels has for showing the viewing area of image and around the non-display area of viewing area, wherein, gate driver circuit is positioned at non-display area.
Accordingly, the present invention also provides a kind of liquid crystal display 200, please refer to Fig. 8, the structured flowchart of its liquid crystal display that is the embodiment of the present invention.As shown in Figure 8, described liquid crystal display 200 comprises: display panels 60, source electrode drive circuit 70 and two above-mentioned gate driver circuits 100; Described display panels 60 comprises multi-strip scanning line 61 and many signal line 62, described source electrode drive circuit 70 is connected with described many signal line 62, and described two gate driver circuits 100 lay respectively at the relative both sides of described display panels 60 and are connected with described multi-strip scanning line 61.
Concrete, source electrode drive circuit 70 and gate driver circuit 100 are all positioned at the non-display area of display panels 60.Two gate driver circuits 100 are according to clock signal difference output scanning signal Gout, and sweep signal Gout is sent to the sweep trace of display panels 60 in order to drive pixel.The gate driver circuit 100 of display panels 60 both sides output scanning signal Gout respectively in the liquid crystal display 200 that the present embodiment provides, brightness that can equilibrium liquid LCD panel both sides.And gate driver circuit 100 gate driver circuit 10 employings more of the prior art latch still less.In the present embodiment, liquid crystal display adopts two side drives, if liquid crystal display one side of high definition (HD) pattern or full HD (FHD) pattern can reduce by 190 or 270 latchs.Therefore, can reduce the area of the non-display area of display panels both sides, realize the object of narrow frame, reduce the power consumption of gate driver circuit simultaneously.
To sum up, in the gate driver circuit providing in the embodiment of the present invention and control method thereof and liquid crystal display, a latch carries out and non-calculating with two clock signals respectively, between two latchs, add a latch for pushing shift signal simultaneously, thereby realize the type of drive that monolock is deposited dual output, described gate driver circuit only needs 3 latchs just can export 4 sweep signals, can save a large amount of latchs thus, when reducing power consumption, reduce the area of the non-display area of display panels both sides, realize the object of narrow frame.Meanwhile, the pulse of the shift signal of described gate driver circuit covers 4 clock signals, has greatly increased the dutycycle of clock signal, has improved the utilization factor of shift signal.
Foregoing description is only the description to preferred embodiment of the present invention, the not any restriction to the scope of the invention, and any change, modification that the those of ordinary skill in field of the present invention is done according to above-mentioned disclosure, all belong to the protection domain of claims.
Claims (18)
1. a gate driver circuit, is characterized in that, comprising: a plurality of shift register cells;
Described shift register cell comprises the first latch, the second latch, the 3rd latch, the first NAND circuit, the second NAND circuit, the 3rd NAND circuit and the 4th NAND circuit;
The output terminal of described the first latch is connected with the input end of the second NAND circuit with the input end of described the first NAND circuit respectively;
The output terminal of described the 3rd latch is connected with the input end of the 4th NAND circuit with the input end of described the 3rd NAND circuit respectively;
The input end of described the second latch is connected with the output terminal of described the first latch, and the output terminal of described the second latch is connected with the input end of described the 3rd latch;
Described shift register cell connects successively, and the output terminal of the 3rd latch of previous shift register cell is connected with the input end of the first latch of a rear shift register cell.
2. gate driver circuit as claimed in claim 1, is characterized in that, described shift register cell also comprises a plurality of impact dampers, and described impact damper is for output scanning signal;
The output terminal of described the first NAND circuit, the second NAND circuit, the 3rd NAND circuit and the 4th NAND circuit is connected with described impact damper respectively.
3. gate driver circuit as claimed in claim 2, is characterized in that, described impact damper comprises odd number phase inverter, and described odd number phase inverter connects successively.
4. gate driver circuit as claimed in claim 1, is characterized in that, described the first NAND circuit comprises one first Sheffer stroke gate; Described the second NAND circuit comprises one second Sheffer stroke gate; Described the 3rd NAND circuit comprises one the 3rd Sheffer stroke gate; Described the 4th NAND circuit comprises one the 4th Sheffer stroke gate.
5. gate driver circuit as claimed in claim 1, is characterized in that, described the first latch, the second latch, the 3rd latch are controlled output shift signal by clock signal.
6. gate driver circuit as claimed in claim 5, is characterized in that, described clock signal comprises the first clock signal, the second clock signal, the 3rd clock signal and the 4th clock signal;
Wherein, described the first latch is controlled by the 4th clock signal, and described the second latch is controlled by the second clock signal or the 3rd clock signal, and described the 3rd latch is controlled by the first clock signal.
7. gate driver circuit as claimed in claim 6, is characterized in that, the rising edge of the rising edge of the shift signal of described the first latch output and respectively corresponding the 4th clock signal of negative edge;
The rising edge of the rising edge of the shift signal of described the second latch output and negative edge corresponding the second clock signal of difference or the 3rd clock signal;
The rising edge of the shift signal of described the 3rd latch output and negative edge be the rising edge of corresponding the first clock signal respectively.
8. gate driver circuit as claimed in claim 7, is characterized in that, the negative edge time of described the first clock signal is corresponding with the rising time of the second clock signal, and free interval;
The negative edge time of described the second clock signal is corresponding with the rising time of the 3rd clock signal, and free interval;
The negative edge time of described the 3rd clock signal is corresponding with the rising time of the 4th clock signal, and free interval;
The negative edge time of described the 4th clock signal is corresponding with the rising time of the first clock signal, and free interval.
9. gate driver circuit as claimed in claim 8, is characterized in that, the pulse width of described shift signal is more than or equal to the pulse width sum of described the first clock signal, the second clock signal, the 3rd clock signal and the 4th clock signal.
10. gate driver circuit as claimed in claim 9, is characterized in that, after described the first latch output shift signal finishes, described the 3rd latch starts to export shift signal.
11. 1 kinds of liquid crystal display, is characterized in that, comprising: display panels, source electrode drive circuit and two gate driver circuits as described in any one in claim 1 to 10;
Described display panels comprises multi-strip scanning line and many signal line, and described source electrode drive circuit is connected with described many signal line, and described two gate driver circuits lay respectively at the relative both sides of described display panels and are connected with described multi-strip scanning line.
The control method of 12. 1 kinds of gate driver circuits, is characterized in that, comprising:
The first latch, the second latch, the 3rd latch are exported respectively shift signal according to clock signal;
The first NAND circuit, the second NAND circuit, the 3rd NAND circuit and the 4th NAND circuit receive respectively shift signal and clock signal output and non-result of calculation;
Impact damper is according to described and non-result of calculation difference output scanning signal.
The control method of 13. gate driver circuits as claimed in claim 12, is characterized in that, described impact damper comprises odd number phase inverter, and described odd number phase inverter connects successively;
Described sweep signal is exported by described odd number phase inverter.
The control method of 14. gate driver circuits as claimed in claim 12, is characterized in that, described clock signal comprises the first clock signal, the second clock signal, the 3rd clock signal and the 4th clock signal;
Described the first latch is controlled by the 4th clock signal, and described the second latch is controlled by the second clock signal or the 3rd clock signal, and described the 3rd latch is controlled by the first clock signal.
The control method of 15. gate driver circuits as claimed in claim 14, is characterized in that, the rising edge of the rising edge of the shift signal of described the first latch output and respectively corresponding the 4th clock signal of negative edge;
The rising edge of the rising edge of the shift signal of described the second latch output and negative edge corresponding the second clock signal of difference or the 3rd clock signal;
The rising edge of the shift signal of described the 3rd latch output and negative edge be the rising edge of corresponding the first clock signal respectively.
The control method of 16. gate driver circuits as claimed in claim 15, is characterized in that, the negative edge time of described the first clock signal is corresponding with the rising time of the second clock signal, and free interval;
The negative edge time of described the second clock signal is corresponding with the rising time of the 3rd clock signal, and free interval;
The negative edge time of described the 3rd clock signal is corresponding with the rising time of the 4th clock signal, and free interval;
The negative edge time of described the 4th clock signal is corresponding with the rising time of the first clock signal, and free interval.
The control method of 17. gate driver circuits as claimed in claim 16, it is characterized in that, the pulse width of described shift signal is more than or equal to the pulse width sum of described the first clock signal, the second clock signal, the 3rd clock signal and the 4th clock signal.
The control method of 18. gate driver circuits as claimed in claim 17, is characterized in that, after described the first latch output shift signal finishes, described the 3rd latch starts to export shift signal.
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| CN201310473356.2A CN103985361B (en) | 2013-10-11 | 2013-10-11 | Gate driver circuit and control method thereof and liquid crystal display |
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| CN201310473356.2A CN103985361B (en) | 2013-10-11 | 2013-10-11 | Gate driver circuit and control method thereof and liquid crystal display |
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