CN104579245A - RC (resistance-capacitance) oscillator - Google Patents
RC (resistance-capacitance) oscillator Download PDFInfo
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- CN104579245A CN104579245A CN201410151448.3A CN201410151448A CN104579245A CN 104579245 A CN104579245 A CN 104579245A CN 201410151448 A CN201410151448 A CN 201410151448A CN 104579245 A CN104579245 A CN 104579245A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/011—Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature
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Abstract
The invention discloses an RC oscillator which comprises a bias generation circuit and an oscillation generation circuit, wherein the bias generation circuit is used for generating bias current which is determined by two resistors and threshold voltage of an NMOS (N-channel metal oxide semiconductor) tube; the oscillation generation circuit adopts two mirror image circuits for charging capacitors of two charge/discharge circuits respectively, and the capacitors of the charge/discharge circuits are used for ground discharge; two control signal generation circuits are used for generating two control signals according to the voltages of the capacitors of the charge/discharge circuit, the control signals are input into an output circuit, an oscillation signal and a feedback signal used for controlling the charge and discharge of the capacitors are output, and the threshold voltages of the NMOS tubes of the control signal generation circuits are the same as the threshold voltage of the NMOS tube of the bias generation circuit, so that the frequency of the oscillation signal is related with two resistors and capacitors only. According to the RC oscillator, the circuit structure is simple and the frequency of the output oscillation signal is relatively high in precision.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit, particularly relate to a kind of RC oscillator.
Background technology
In many System on Chip/SoCs (system on chip, SOC) application, oscillator is a very important module.Oscillator is divided into resistance-capacitance oscillator and RC oscillator, LC oscillator, crystal oscillator, fork generator etc.RC oscillator is by carrying out to electric capacity the output that charging and discharging realizes oscillator signal, can be regulated the frequency of oscillator signal by the value of regulating resistance or electric capacity.Relative in other various types of oscillator, it is simple that RC oscillator has structure, and the advantage that precision is higher, so in some SOC, such as, in single-chip microcomputer (Micro ControlUnit, MCU), RC oscillator is very common.
In SOC, the circuit of device is simpler, then the cost of chip is lower; Meanwhile, the oscillator signal precision that RC oscillator exports is higher, and the performance of chip is better.The circuit structure of existing RC oscillator is still comparatively complicated, and the frequency of the oscillator signal exported easily is subject to the impact such as supply voltage, temperature, this all can reduce the frequency accuracy of oscillator signal, so how to obtain that circuit structure is simple and the RC oscillator that can export the oscillation signal frequency of degree of precision is a significantly research topic.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of RC oscillator, and circuit structure is simple, and the frequency of the oscillator signal exported has higher precision.
For solving the problems of the technologies described above, RC oscillator provided by the invention comprises offset generating circuit and oscillation generating circuit.
Described offset generating circuit is for generation of bias current; Described offset generating circuit comprises the first current path, the second current path and an operational amplifier, described first current path comprises the first PMOS and the first resistance, described second current path comprises the second PMOS, the second resistance and the first NMOS tube, and the source electrode of described first PMOS and described second PMOS all connects the output that supply voltage, grid all connect described operational amplifier; The first end of described first resistance connects the drain electrode of described first PMOS and the first input end of described operational amplifier, the second end ground connection of the first resistance; The first end of the drain electrode of described second PMOS, the grid of described first NMOS tube and described second resistance links together, second end of described second resistance connects the drain electrode of described first NMOS tube and the second input of described operational amplifier, the source ground of described first NMOS tube, the first input end of described operational amplifier and the second input are two anti-phase each other inputs.
The size ratio of the first bias current of described first current path and the second bias current of described second current path is determined by the ratio of the breadth length ratio of the breadth length ratio of the raceway groove of described first PMOS and the raceway groove of described second PMOS; Described first NMOS tube works in saturation region, the size of described first bias current and described second bias current is determined by the value of the grid voltage of described first NMOS tube, described first resistance and described second resistance, and the breadth length ratio of the raceway groove of described first NMOS tube meets makes the grid voltage of described first NMOS tube be in the scope of positive and negative 2% of the threshold voltage of described first NMOS tube.
Described oscillation generating circuit comprises two mirror image circuits and two charge-discharge circuits, first charge-discharge circuit is connected with the first mirror image circuit, the second charge-discharge circuit is connected with the second mirror image circuit, the first image current that described first mirror image circuit produces and described first bias current is proportional, the second image current that described second mirror image circuit produces and described first bias current is proportional.
Described first charge-discharge circuit comprises the first electric capacity, the 7th PMOS and the 4th NMOS tube, the grid of described 7th PMOS and described 4th NMOS tube all connects the second feedback signal, the source electrode of described 7th PMOS connects the first image current output of described first mirror image circuit, described 7th PMOS is all connected the first end of described first electric capacity with the drain electrode of described 4th NMOS tube, the source ground of described 4th NMOS tube, the second end ground connection of described first electric capacity.
Described second charge-discharge circuit comprises the second electric capacity, the 8th PMOS and the 5th NMOS tube, the grid of described 8th PMOS and described 5th NMOS tube all connects the first feedback signal, the source electrode of described 8th PMOS connects the second image current output of described second mirror image circuit, described 8th PMOS is all connected the first end of described second electric capacity with the drain electrode of described 5th NMOS tube, the source ground of described 5th NMOS tube, the second end ground connection of described second electric capacity.
Described oscillation generating circuit also comprises two control signals and produces circuit, described first control signal produces circuit and comprises the 3rd PMOS and the second NMOS tube, the source electrode of described 3rd PMOS connects supply voltage, the grid of described 3rd PMOS connects the grid of described first PMOS, described 3rd PMOS is connected with the drain electrode of described second NMOS tube and as the output of the first control signal, the grid of described second NMOS tube connects the first end of described first electric capacity, the source ground of described second NMOS tube, the threshold voltage of described second NMOS tube equals the threshold voltage of described first NMOS tube, described in when the voltage of the first end of described first electric capacity is greater than the threshold voltage of described second NMOS tube, the first control signal is low level, described in when the voltage of the first end of described first electric capacity is less than the threshold voltage of described second NMOS tube, the first control signal is high level.
Described second control signal produces circuit and comprises the 4th PMOS and the 3rd NMOS tube, the source electrode of described 4th PMOS connects supply voltage, the grid of described 4th PMOS connects the grid of described first PMOS, described 4th PMOS is connected with the drain electrode of described 3rd NMOS tube and as the output of the second control signal, the grid of described 3rd NMOS tube connects the first end of described second electric capacity, the source ground of described 3rd NMOS tube, the threshold voltage of described 3rd NMOS tube equals the threshold voltage of described first NMOS tube, described in when the voltage of the first end of described second electric capacity is greater than the threshold voltage of described 3rd NMOS tube, the second control signal is low level, described in when the voltage of the first end of described second electric capacity is less than the threshold voltage of described 3rd NMOS tube, the second control signal is high level.
Described oscillation generating circuit also comprises an output circuit, described output circuit comprises 8 inverters and two NAND gate, the output of the first NAND gate connects the first input end of the second NAND gate, and the output of described second NAND gate connects the first input end of described first NAND gate; Be in series with two inverters between second input of described first control signal and described first NAND gate, between the second input of described second control signal and described second NAND gate, be in series with two inverters; The output of described first NAND gate is by being connected rear outputting oscillation signal with the inverter of two series connection; The output of described second NAND gate exports described first feedback signal by being connected with an inverter, and described first feedback signal exports described second feedback signal by being connected with an inverter.
Further improvement is, described first PMOS is identical with the breadth length ratio of the raceway groove of described second PMOS, the equal and opposite in direction of described first bias current and described second bias current.
Further improvement is, the equal and opposite in direction of described first image current and described first bias current, the equal and opposite in direction of described second image current and described first bias current.
Further improvement is, described first mirror image circuit is made up of the 5th PMOS, the grid of described 5th PMOS connects the grid of described first PMOS, and the source electrode of described 5th PMOS connects supply voltage, and the drain electrode of described 5th PMOS exports described first image current.
Further improvement is, described first PMOS is identical with the breadth length ratio of the raceway groove of described 5th PMOS, the equal and opposite in direction of described first bias current and described first image current.
Further improvement is, described second mirror image circuit is made up of the 6th PMOS, the grid of described 6th PMOS connects the grid of described first PMOS, and the source electrode of described 6th PMOS connects supply voltage, and the drain electrode of described 6th PMOS exports described second image current.
Further improvement is, described first PMOS is identical with the breadth length ratio of the raceway groove of described 6th PMOS, the equal and opposite in direction of described first bias current and described second image current.
Further improvement is, the equal and opposite in direction of described first electric capacity and described second electric capacity.
Further improvement is, by the frequency of oscillator signal described in the size adjustment that regulates described first resistance, described second resistance, described first electric capacity and described second electric capacity.
Further improvement is, described RC oscillator is integrated in same SOC.
RC oscillator of the present invention has following beneficial effect:
1, circuit of the present invention have employed 2 resistance and 2 electric capacity, other parts are all made up of NMOS tube or PMOS, structure of the present invention CMOS technology can be adopted to realize, so simply and easily on the same chip integrated, can be good at being applied in SOC.
2, the present invention is by the setting to the breadth length ratio of the raceway groove of the first NMOS tube in the second current path of offset generating circuit, and the first bias current of offset generating circuit can be made relevant with two resistance of offset generating circuit with the threshold voltage of size only with the first NMOS tube of the second bias current; The present invention is set to identical by the threshold voltage of NMOS tube and the threshold voltage of the first NMOS tube two of oscillation generating circuit control signals being produced circuit, frequency only with two resistance of the oscillator signal that whole circuit can be made to export are relevant with two electric capacity, eliminate supply voltage and each NMOS tube or PMOS to the impact of the frequency of oscillator signal, so the frequency of the oscillator signal exported has higher precision, and the adjustment of the frequency of oscillator signal just can be realized by adjustment two resistance or two electric capacity, the frequency adjustment of oscillator signal is convenient.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:
Fig. 1 is embodiment of the present invention circuit diagram.
Embodiment
As shown in Figure 1, be embodiment of the present invention circuit diagram.Embodiment of the present invention RC oscillator comprises offset generating circuit 1 and oscillation generating circuit 2.Be preferably, described RC oscillator is integrated in same SOC.
Described offset generating circuit 1 is for generation of bias current; Described offset generating circuit 1 comprises the first current path, the second current path and an operational amplifier 3, described first current path comprises the first PMOS mp1 and the first resistance R1, described second current path comprises the second PMOS mp2, the second resistance R2 and the first NMOS tube mn1, and the source electrode of described first PMOS mp1 and described second PMOS mp2 all connects the output that supply voltage VDD, grid all connect described operational amplifier 3; The first end of described first resistance R1 connects the drain electrode of described first PMOS mp1 and the first input end of described operational amplifier 3, the second end ground connection of the first resistance R1; The first end of the drain electrode of described second PMOS mp2, the grid of described first NMOS tube mn1 and described second resistance R2 links together, second end of described second resistance R2 connects the drain electrode of described first NMOS tube mn1 and the second input of described operational amplifier 3, the source ground of described first NMOS tube mn1, the first input end of described operational amplifier 3 and the second input are two anti-phase each other inputs.
The size ratio of the first bias current I1 of described first current path and the second bias current I2 of described second current path is determined by the ratio of the breadth length ratio of the breadth length ratio of the raceway groove of described first PMOS mp1 and the raceway groove of described second PMOS mp2; Be preferably, described first PMOS mp1 is identical with the breadth length ratio of the raceway groove of described second PMOS mp2, the equal and opposite in direction of described first bias current I1 and described second bias current I2.
Described first NMOS tube mn1 works in saturation region, the size of described first bias current I1 and described second bias current I2 is determined by the value of the grid voltage of described first NMOS tube mn1, described first resistance R1 and described second resistance R2, the grid voltage of described first NMOS tube mn1 approximates the threshold voltage of described first NMOS tube mn1, and the breadth length ratio being specially the raceway groove of described first NMOS tube mn1 meets makes the grid voltage of described first NMOS tube mn1 be in the scope of positive and negative 2% of the threshold voltage of described first NMOS tube mn1.The principle that the size of described first bias current I1 and described second biasing circuit is determined is described as follows:
Make V1 represent the voltage of the first end of described first resistance R1, V2 is the voltage of second end of described second resistance R2, and V3 is the voltage of the first end of described second resistance R2.
Having when described offset generating circuit 1 works: I1=I2, V1=V2, I1=V1/R1, I2=(V3-V2)/R2, following formula (1) can be obtained through deriving:
I=I1=I2=V3/(R1+R2) ------------------------(1)
I represents bias current, and from formula (1), the size of bias current is determined by the value of the grid voltage of described first NMOS tube mn1, described first resistance R1 and described second resistance R2.Formula (1) obtains when being identical with the breadth length ratio of the raceway groove of described second PMOS mp2 with described first PMOS mp1, when the breadth length ratio of the raceway groove of described first PMOS mp1 and described second PMOS mp2 is different thus when making to have certain ratio between described I1 and I2, only corresponding ratio need be added in formula (1), concrete derivation is no longer introduced, and the size of the last like this bias current obtained still is determined by the value of the grid voltage of described first NMOS tube mn1, described first resistance R1 and described second resistance R2.
Because the grid of the first NMOS tube mn1 described in the embodiment of the present invention is linked together by described second resistance R2 with drain electrode, described first NMOS tube mn1 can work in saturation region, by giving the described first NMOS tube mn1 breadth length ratio of suitable raceway groove, then the grid voltage of described first NMOS tube mn1 and V3 can approximate the threshold voltage vt hn of described first NMOS tube mn1, that is:
V3=Vthn --------------------------------(2)
Formula (2) gives situation when V3 equals Vthn, and in practical situation, V3 can change in certain scope, and the frequency of the oscillator signal Osc_out exported during V3 change also can change.Be preferably, the grid voltage of described first NMOS tube mn1 is in the scope of positive and negative 2% of the threshold voltage of described first NMOS tube mn1; Be improved to further, the grid voltage of described first NMOS tube mn1 is in the scope of positive and negative 1% of the threshold voltage of described first NMOS tube mn1.
Described oscillation generating circuit 2 comprises two mirror image circuits and two charge-discharge circuits, and the first charge-discharge circuit is connected with the first mirror image circuit, the second charge-discharge circuit is connected with the second mirror image circuit.
The first image current I3 that described first mirror image circuit produces and described first bias current I1 is proportional, the second image current I4 that described second mirror image circuit produces and described first bias current I1 is proportional.Be preferably, described first mirror image circuit is made up of the 5th PMOS mp5, the grid of described 5th PMOS mp5 connects the grid of described first PMOS mp1, the source electrode of described 5th PMOS mp5 connects supply voltage VDD, and the drain electrode of described 5th PMOS mp5 exports described first image current I3; Described first PMOS mp1 is identical with the breadth length ratio of the raceway groove of described 5th PMOS mp5, the equal and opposite in direction of described first bias current I1 and described first image current I3.Described second mirror image circuit is made up of the 6th PMOS mp6, the grid of described 6th PMOS mp6 connects the grid of described first PMOS mp1, the source electrode of described 6th PMOS mp6 connects supply voltage VDD, and the drain electrode of described 6th PMOS mp6 exports described second image current I4; Described first PMOS mp1 is identical with the breadth length ratio of the raceway groove of described 6th PMOS mp6, the equal and opposite in direction of described first bias current I1 and described second image current I4.
Described first charge-discharge circuit comprises the first electric capacity C1, the 7th PMOS mp7 and the 4th NMOS tube mn4, the grid of described 7th PMOS mp7 and described 4th NMOS tube mn4 all meets the second feedback signal fb_b, the source electrode of described 7th PMOS mp7 connects the first image current I3 output of described first mirror image circuit, described 7th PMOS mp7 is connected the first end of described first electric capacity C1 with the drain electrode of described 4th NMOS tube mn4, the source ground of described 4th NMOS tube mn4, the second end ground connection of described first electric capacity C1.
Described second charge-discharge circuit comprises the second electric capacity C2, the 8th PMOS mp8 and the 5th NMOS tube mn5, the grid of described 8th PMOS mp8 and described 5th NMOS tube mn5 all meets the first feedback signal fb_a, the source electrode of described 8th PMOS mp8 connects the second image current I4 output of described second mirror image circuit, described 8th PMOS mp8 is connected the first end of described second electric capacity C2 with the drain electrode of described 5th NMOS tube mn5, the source ground of described 5th NMOS tube mn5, the second end ground connection of described second electric capacity C2.Be preferably, the equal and opposite in direction of described first electric capacity C1 and described second electric capacity C2.
Described oscillation generating circuit 2 also comprises two control signals and produces circuit, described first control signal produces circuit and comprises the 3rd PMOS mp3 and the second NMOS tube mn2, the source electrode of described 3rd PMOS mp3 connects supply voltage VDD, the grid of described 3rd PMOS mp3 connects the grid of described first PMOS mp1, described 3rd PMOS mp3 is connected with the drain electrode of described second NMOS tube mn2 and as the output of the first control signal in1, the grid of described second NMOS tube mn2 connects the first end of described first electric capacity C1, the source ground of described second NMOS tube mn2, namely the threshold voltage that the threshold voltage of described second NMOS tube mn2 equals described first NMOS tube mn1 is all Vthn, described in when the voltage of the first end of described first electric capacity C1 is greater than the threshold voltage of described second NMOS tube mn2, the first control signal in1 is low level, described in when the voltage of the first end of described first electric capacity C1 is less than the threshold voltage of described second NMOS tube mn2, the first control signal in1 is high level.
Described second control signal produces circuit and comprises the 4th PMOS mp4 and the 3rd NMOS tube mn3, the source electrode of described 4th PMOS mp4 connects supply voltage VDD, the grid of described 4th PMOS mp4 connects the grid of described first PMOS mp1, described 4th PMOS mp4 is connected with the drain electrode of described 3rd NMOS tube mn3 and as the output of the second control signal in2, the grid of described 3rd NMOS tube mn3 connects the first end of described second electric capacity C2, the source ground of described 3rd NMOS tube mn3, the threshold voltage of described 3rd NMOS tube mn3 equals the threshold voltage of described first NMOS tube mn1, described in when the voltage of the first end of described second electric capacity C2 is greater than the threshold voltage of described 3rd NMOS tube mn3, the second control signal in2 is low level, described in when the voltage of the first end of described second electric capacity C2 is less than the threshold voltage of described 3rd NMOS tube mn3, the second control signal in2 is high level.
Described oscillation generating circuit 2 also comprises an output circuit 4, described output circuit 4 comprises 8 inverters 5 and two NAND gate, the output of the first NAND gate 6a connects the first input end of the second NAND gate 6b, and the output of described second NAND gate 6b connects the first input end of described first NAND gate 6a; Be in series with two inverters 5 between second input of described first control signal in1 and described first NAND gate 6a, between second input of described second control signal in2 and described second NAND gate 6b, be in series with two inverters 5; The output of described first NAND gate 6a is by being connected rear outputting oscillation signal Osc_out with the inverter 5 of two series connection; The output of described second NAND gate 6b exports described first feedback signal fb_a, described first feedback signal fb_a and exports described second feedback signal fb_b by being connected with an inverter 5 by being connected with an inverter 5.In the embodiment of the present invention, by the frequency of oscillator signal Osc_out described in the size adjustment that regulates described first resistance R1, described second resistance R2, described first electric capacity C1 and described second electric capacity C2.
Be that example illustrates that the operation principle of the embodiment of the present invention is as follows time now in a preferred embodiment thereof:
Known as mentioned above, when better embodiment, described first PMOS mp1, described second PMOS mp2, described 5th PMOS mp5 are identical with the breadth length ratio of the raceway groove of described 6th PMOS mp6, there is the size of described first bias current I1, described second bias current I2, described first image current I3 and described second image current I4 all equal like this, that is:
I=I3=I4=I1=I2 ---------------------------------(3)
In better embodiment, described first electric capacity C1 is also identical with the size of described second electric capacity C2, and the voltage of the first end of described first electric capacity C1 is Vn1, and the voltage of the first end of described second electric capacity C2 is Vn2.
If when Vn1 arrives Vthn from 0, the electric current of described second NMOS tube mn2 is far longer than the electric current of the 3rd PMOS mp3.Like this when Vn1 arrives Vthn from 0, in1 just changes to 0 from VDD rapidly; Similarly, when vn2 reaches Vthn from 0, in2 just changes to 0 from VDD rapidly.So when described RC oscillator operation, vn1 and vn2 changes between 0 and vthn.
As seen from Figure 1, described first NAND gate 6a and described second NAND gate 6b is connected to form a rest-set flip-flop structure; If in2 is 0, so, fb_b is also that 0, fb_a equals VDD, and this can make I3 charge to vn1, and described second electric capacity C2 is discharged to vn2 by described 5th NMOS tube mn5.When vn1 reaches Vthn from 0, in1 equals 0, in2 and equals VDD, and now, fb_a equals 0, fb_b and equals VDD, so vn1 starts electric discharge, vn2 starts charging.When vn2 reaches Vthn, in2 equals 0, in1 and equals VDD, and this can make fb_a uprise, fb_b step-down, and like this, vn1 starts charging, and vn2 starts electric discharge; Circulation like this, vibration just creates, and finally forms described oscillator signal Osc_out.
Vn1 and Vn2 constantly changes to VDD from 0, or changes to 0. within the half period of vibration from VDD:
I*t=Vthn*C ---------------------------------(4)
In conjunction with formula (1) ~ (4), obtain:
t=(R1+R2)*C
So the cycle of the described oscillator signal Osc_out of described RC oscillator is:
T=2t=2(R1+R2)×C --------------------------------(5)
Frequency of oscillation:
F=1/2п×T=1/[4п×(R1+R2)×C] -----------------------(6)
As can be seen from formula (6), the frequency of the described oscillator signal Osc_out of described RC oscillator is only relevant with passive device R with C.If we will obtain accurate frequency of oscillation, only need the value of regulating resistance or electric capacity just can obtain.
Equally, the embodiment of the present invention is when other execution mode, also the conclusion that the frequency of the described oscillator signal Osc_out of described RC oscillator is only relevant with passive device R with C can be obtained, each electric current I 1, I2, I3 and I4 are no longer equal, but proportional, as long as add corresponding ratio value in the formula of correspondence.When described first electric capacity C1 and described second electric capacity C2 not etc. time, the C in the t of two half periods of vibration replaces with C1 and C2 respectively.
Embodiment of the present invention circuit have employed 2 resistance and 2 electric capacity, and other parts are all made up of NMOS tube or PMOS, and CMOS technology can be adopted to realize, as:
Each described inverter 5 can adopt CMOS inverter, is connected to form by a PMOS and a NMOS tube.
Each described NAND gate can adopt two PMOS and two NMOS tube to be connected to form, two PMOS employing parallel, two NMOS tube adopt and are connected in series mode, and between the drain electrode that is connected in parallel on the cascaded structure of two NMOS tube of two PMOS and supply voltage, between the drain electrode that two NMOS tube are connected on the parallel-connection structure of two PMOS and ground.
Described operational amplifier 3 also can adopt multiple NMOS tube and PMOS to be connected to form.
As from the foregoing, embodiment of the present invention circuit structure simply and easily on the same chip integrated, can be good at being applied in SOC.
The embodiment of the present invention, by the setting to the breadth length ratio of the raceway groove of the first NMOS tube mn1 in the second current path of offset generating circuit 1, can make the first bias current I1 of offset generating circuit 1 relevant with two resistance R1 with R2 of offset generating circuit 1 with the threshold voltage vt hn of size only with the first NMOS tube mn1 of the second bias current I2, the present invention is set to identical by the threshold voltage two of oscillation generating circuit 2 control signals being produced the NMOS tube mn2 of circuit and the threshold voltage of mn3 and the first NMOS tube mn1, frequency only with two resistance R1 with R2 of the oscillator signal Osc_out that whole circuit can be made to export are relevant with two electric capacity C1 with C2, eliminate supply voltage VDD and each NMOS tube or PMOS to the impact of the frequency of oscillator signal Osc_out, so the frequency of the oscillator signal Osc_out exported has higher precision, and the adjustment of the frequency of oscillator signal just can be realized by adjustment two resistance R1 and R2 and two electric capacity C1 and C2, the frequency adjustment of oscillator signal is convenient.
Proved inventive embodiments the good oscillator signal Osc_out of frequency performance really can be obtained by emulation experiment.
Above by specific embodiment to invention has been detailed description, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (10)
1. a RC oscillator, is characterized in that, comprises offset generating circuit and oscillation generating circuit;
Described offset generating circuit is for generation of bias current; Described offset generating circuit comprises the first current path, the second current path and an operational amplifier, described first current path comprises the first PMOS and the first resistance, described second current path comprises the second PMOS, the second resistance and the first NMOS tube, and the source electrode of described first PMOS and described second PMOS all connects the output that supply voltage, grid all connect described operational amplifier; The first end of described first resistance connects the drain electrode of described first PMOS and the first input end of described operational amplifier, the second end ground connection of the first resistance; The first end of the drain electrode of described second PMOS, the grid of described first NMOS tube and described second resistance links together, second end of described second resistance connects the drain electrode of described first NMOS tube and the second input of described operational amplifier, the source ground of described first NMOS tube, the first input end of described operational amplifier and the second input are two anti-phase each other inputs;
The size ratio of the first bias current of described first current path and the second bias current of described second current path is determined by the ratio of the breadth length ratio of the breadth length ratio of the raceway groove of described first PMOS and the raceway groove of described second PMOS; Described first NMOS tube works in saturation region, the size of described first bias current and described second bias current is determined by the value of the grid voltage of described first NMOS tube, described first resistance and described second resistance, and the breadth length ratio of the raceway groove of described first NMOS tube meets makes the grid voltage of described first NMOS tube be in the scope of positive and negative 2% of the threshold voltage of described first NMOS tube;
Described oscillation generating circuit comprises two mirror image circuits and two charge-discharge circuits, first charge-discharge circuit is connected with the first mirror image circuit, the second charge-discharge circuit is connected with the second mirror image circuit, the first image current that described first mirror image circuit produces and described first bias current is proportional, the second image current that described second mirror image circuit produces and described first bias current is proportional;
Described first charge-discharge circuit comprises the first electric capacity, the 7th PMOS and the 4th NMOS tube, the grid of described 7th PMOS and described 4th NMOS tube all connects the second feedback signal, the source electrode of described 7th PMOS connects the first image current output of described first mirror image circuit, described 7th PMOS is all connected the first end of described first electric capacity with the drain electrode of described 4th NMOS tube, the source ground of described 4th NMOS tube, the second end ground connection of described first electric capacity;
Described second charge-discharge circuit comprises the second electric capacity, the 8th PMOS and the 5th NMOS tube, the grid of described 8th PMOS and described 5th NMOS tube all connects the first feedback signal, the source electrode of described 8th PMOS connects the second image current output of described second mirror image circuit, described 8th PMOS is all connected the first end of described second electric capacity with the drain electrode of described 5th NMOS tube, the source ground of described 5th NMOS tube, the second end ground connection of described second electric capacity;
Described oscillation generating circuit also comprises two control signals and produces circuit, described first control signal produces circuit and comprises the 3rd PMOS and the second NMOS tube, the source electrode of described 3rd PMOS connects supply voltage, the grid of described 3rd PMOS connects the grid of described first PMOS, described 3rd PMOS is connected with the drain electrode of described second NMOS tube and as the output of the first control signal, the grid of described second NMOS tube connects the first end of described first electric capacity, the source ground of described second NMOS tube, the threshold voltage of described second NMOS tube equals the threshold voltage of described first NMOS tube, described in when the voltage of the first end of described first electric capacity is greater than the threshold voltage of described second NMOS tube, the first control signal is low level, described in when the voltage of the first end of described first electric capacity is less than the threshold voltage of described second NMOS tube, the first control signal is high level,
Described second control signal produces circuit and comprises the 4th PMOS and the 3rd NMOS tube, the source electrode of described 4th PMOS connects supply voltage, the grid of described 4th PMOS connects the grid of described first PMOS, described 4th PMOS is connected with the drain electrode of described 3rd NMOS tube and as the output of the second control signal, the grid of described 3rd NMOS tube connects the first end of described second electric capacity, the source ground of described 3rd NMOS tube, the threshold voltage of described 3rd NMOS tube equals the threshold voltage of described first NMOS tube, described in when the voltage of the first end of described second electric capacity is greater than the threshold voltage of described 3rd NMOS tube, the second control signal is low level, described in when the voltage of the first end of described second electric capacity is less than the threshold voltage of described 3rd NMOS tube, the second control signal is high level,
Described oscillation generating circuit also comprises an output circuit, described output circuit comprises 8 inverters and two NAND gate, the output of the first NAND gate connects the first input end of the second NAND gate, and the output of described second NAND gate connects the first input end of described first NAND gate; Be in series with two inverters between second input of described first control signal and described first NAND gate, between the second input of described second control signal and described second NAND gate, be in series with two inverters; The output of described first NAND gate is by being connected rear outputting oscillation signal with the inverter of two series connection; The output of described second NAND gate exports described first feedback signal by being connected with an inverter, and described first feedback signal exports described second feedback signal by being connected with an inverter.
2. RC oscillator as claimed in claim 1, is characterized in that: described first PMOS is identical with the breadth length ratio of the raceway groove of described second PMOS, the equal and opposite in direction of described first bias current and described second bias current.
3. RC oscillator as claimed in claim 2, is characterized in that: the equal and opposite in direction of described first image current and described first bias current, the equal and opposite in direction of described second image current and described first bias current.
4. RC oscillator as claimed in claim 1 or 2, it is characterized in that: described first mirror image circuit is made up of the 5th PMOS, the grid of described 5th PMOS connects the grid of described first PMOS, the source electrode of described 5th PMOS connects supply voltage, and the drain electrode of described 5th PMOS exports described first image current.
5. RC oscillator as claimed in claim 4, is characterized in that: described first PMOS is identical with the breadth length ratio of the raceway groove of described 5th PMOS, the equal and opposite in direction of described first bias current and described first image current.
6. RC oscillator as claimed in claim 1 or 2, it is characterized in that: described second mirror image circuit is made up of the 6th PMOS, the grid of described 6th PMOS connects the grid of described first PMOS, the source electrode of described 6th PMOS connects supply voltage, and the drain electrode of described 6th PMOS exports described second image current.
7. RC oscillator as claimed in claim 6, is characterized in that: described first PMOS is identical with the breadth length ratio of the raceway groove of described 6th PMOS, the equal and opposite in direction of described first bias current and described second image current.
8. RC oscillator as claimed in claim 1, is characterized in that: the equal and opposite in direction of described first electric capacity and described second electric capacity.
9. RC oscillator as described in claim 1 or 8, is characterized in that: by the frequency of oscillator signal described in the size adjustment that regulates described first resistance, described second resistance, described first electric capacity and described second electric capacity.
10. RC oscillator as claimed in claim 1, is characterized in that: described RC oscillator is integrated in same SOC.
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| CN107241083A (en) * | 2017-06-05 | 2017-10-10 | 上海爱信诺航芯电子科技有限公司 | A kind of high-precision automatic biasing clock circuit and corresponding auto bias circuit |
| CN109525197A (en) * | 2018-11-28 | 2019-03-26 | 中国电子科技集团公司第四十七研究所 | Overriding high-precision rc oscillator |
| CN110719102A (en) * | 2019-10-23 | 2020-01-21 | 杭州士兰微电子股份有限公司 | Oscillation circuit and clock circuit |
| CN109286369B (en) * | 2017-07-21 | 2020-10-09 | 珠海格力电器股份有限公司 | Voltage-controlled oscillator, integrated chip and electronic equipment |
| CN116317951A (en) * | 2023-04-17 | 2023-06-23 | 江苏润石科技有限公司 | RC relaxation oscillator circuit |
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| CN107241083A (en) * | 2017-06-05 | 2017-10-10 | 上海爱信诺航芯电子科技有限公司 | A kind of high-precision automatic biasing clock circuit and corresponding auto bias circuit |
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| CN109525197B (en) * | 2018-11-28 | 2022-09-13 | 中国电子科技集团公司第四十七研究所 | High-precision RC oscillator capable of being modified and adjusted |
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| CN116317951B (en) * | 2023-04-17 | 2023-08-01 | 江苏润石科技有限公司 | RC relaxation oscillator circuit |
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