CN104575605B - Memory device and method for starting system by using nonvolatile memory - Google Patents

Abstract

A memory device and a method for booting a system using a non-volatile memory. A memory device according to an embodiment of the present invention comprises a non-volatile memory element, a status register, a control unit and a leakage current correction unit. The non-volatile memory element comprises a boot block and a plurality of data blocks, wherein the memory cells in the boot block and the memory cells in the plurality of data blocks are electrically connected to the same bit line. The status register is electrically connected to the non-volatile memory element and is configured to store a status flag, which is used to indicate whether a complete erase operation applied to the non-volatile memory element has been completed. The control unit is configured to read the flag value of the status flag after the memory device is powered on. The leakage current correction unit is electrically connected to the control unit and is configured to selectively execute a leakage current suppression program on the non-volatile memory element according to the flag value of the status flag.

Description

Memory device and method for booting system using non-volatile memory

technical field

The present invention relates to a memory device; in particular, to a method for booting a system using a non-volatile memory element and a related memory device.

Background technique

In the process of erasing a non-volatile memory, and more specifically, in the process of erasing a particular block within a non-volatile memory, unexpected interruptions, such as unexpected power interruptions, may occur . In this case, a full wipe operation cannot be successfully performed. For example, referring to FIG. 1, if a memory block has completed the preprogramming (preprogramming) step (step 12), but failed to complete the erase correction (Over EraseCorrection, OEC) step (step 16) when the power is interrupted, Then the leakage of the bit line may be caused due to the over-erase phenomenon. When the system is powered on again, the bit line leakage caused by the memory block that failed the OEC step may affect the associated memory blocks sharing the same bit line. If the associated memory block is used to store a booting code, the system may not be able to read the booting code when the system executes the booting procedure after power is turned on again. This can result in long boot times, or the system may fail to boot.

With the vigorous development of handheld electronic devices, system stability is an important issue in many consumer products. In addition, more and more memory blocks are incorporated into high-capacity memory devices. Therefore, there is a need for a solution to the above-mentioned bit line leakage phenomenon.

Contents of the invention

A method for booting a system using a non-volatile memory element according to an embodiment of the present invention includes the following steps: when the system is powered on, reading at least one corresponding to the non-volatile memory element A status flag of the memory block, the flag value of the status flag indicates whether a complete erasing operation applied to the memory block has been completed; the corresponding memory block is selectively executed according to the flag value of the status flag a leakage current suppression program; and booting the system according to a boot code stored in the non-volatile memory element.

A memory device according to an embodiment of the present invention includes a non-volatile memory element, a status register, a control unit and a leakage current correction unit. The non-volatile memory device includes a plurality of memory blocks. The status register is electrically connected to the non-volatile memory element and is configured to store a status flag indicating a complete erase applied to at least one memory block in the non-volatile memory element Whether the removal operation has been completed. The control unit is configured to read the flag value of the status flag after the memory device is powered on. The leakage current correction unit is electrically connected to the control unit, and is configured to selectively execute a leakage current suppression program on the memory blocks according to the flag value of the state flag.

Description of drawings

FIG. 1 shows a flow chart of a known complete erasing operation.

FIG. 2 shows a block diagram of a memory device incorporating an embodiment of the present invention.

FIG. 3 shows a schematic diagram of two memory blocks sharing a same bit line.

FIG. 4 shows a flowchart of a complete erase operation of the non-volatile memory device according to an embodiment of the invention.

FIG. 5 shows a flow chart of a method for booting a system using a non-volatile memory device according to an embodiment of the invention.

FIG. 6 shows a flowchart of a method for booting a system using a non-volatile memory device according to another embodiment of the present invention

【Symbol Description】

10-18 steps

200 memory devices

202 non-volatile memory elements

204 Status Register Bank

206 OR gate circuit

208 control unit

210 Leakage current correction unit

212 First bias voltage generator

214 second bias voltage generator

216 Re-erase unit

32 boot blocks

34 data blocks

36 Sense amplifier

400 full wipe operation

402-414 steps

500 boot method

502-512 steps

600 boot method

602-612 steps

BL bit line

detailed description

FIG. 2 shows a block diagram of a memory device 200 incorporating an embodiment of the present invention. Referring to FIG. 2 , the memory device 200 includes a non-volatile memory element 202 , a state register bank 204 , an OR gate circuit 206 , a control unit 208 and a leakage current correction unit 210 . The leakage current correction unit 210 includes a first bias voltage generator 212 , a second bias voltage generator 214 and a re-erase unit 216 .

Referring to FIG. 2, the non-volatile memory device 202 includes N memory blocks [0] to memory blocks [N-1] for storing normal data or boot codes, wherein N is a positive integer. For example, in this embodiment, the memory cells in the memory block [0] are configured to store normal data, and the memory cells in the memory block [1] are configured to store boot codes. In addition, the memory cells in the memory block [0] and the memory cells in the memory block [1] are electrically connected to the same bit line. In order to reduce the chip area of the memory element 202, the memory cells in the memory block [0] and the memory cells in the memory block [1] do not have isolation elements between each other.

Please refer to FIG. 3 , which shows a schematic diagram of two memory blocks sharing the same bit line BL, wherein the boot block 32 is used to store boot codes, and the data block 34 is used to store normal data. Assuming that the memory cells in the data block 34 are over-erased and the power is interrupted when the OEC step cannot be completed, since the memory cells in the boot block 32 and the memory cells in the data block 34 share the same bit line , when the boot procedure is carried out after power transmission, the boot code will fail to be read when reading the boot code from the boot block 32. This is due to the bit line leakage (Ileak>0μA) caused by the over-erase phenomenon, so that the sense amplifier (SenseAmplifier, SA) 36 senses when reading the logic "0" data of the selected unit cell in the power-on block 32 To the wrong current, and then read the wrong data value. This can result in long boot times, or the system may fail to boot.

Referring to FIG. 2 , in this embodiment, the status register library 204 includes N status registers [0] to [N-1]. These registers [0] to [N-1] are used to store state flags FL[0] to FL[N-1], wherein each state flag is used to indicate the corresponding memory area in the non-volatile memory element 202 Whether the block has successfully completed a full erase operation. For example, FL[0] indicates whether memory block [0] has successfully completed a complete erase operation, and FL[1] indicates whether memory block [1] has successfully completed a complete erase operation, according to And so on. However, the present invention should not be limited thereto. In other embodiments the status register bank 204 may include less than N status registers. That is, there may be multiple memory blocks allocated to a status flag.

FIG. 4 shows a flowchart of a complete erase operation 400 of the non-volatile memory device 202 according to an embodiment of the present invention. Referring to FIG. 4 , at first step 402 is performed, wherein at least one specific block in the non-volatile memory device 202 is ready to be erased. Next, in step 404 , the status flag FL of the register corresponding to the at least one specific block in the status register bank 204 is set to logic “1”. In step 406, a pre-programming operation is performed on the memory cells in the specific blocks. In step 408, an erase operation is performed on the memory cells in the specific blocks. In step 406, an over-erase correction operation is performed on the memory cells in the specific blocks. After the memory cells in the specific blocks have been pre-programmed 406, erased 408 and over-erased corrected 410 in sequence, registers in the state register bank 204 corresponding to the specific blocks are The flag value of the status flag FL is set to logic "0".

FIG. 5 shows a flowchart of a method 500 for booting a system using a non-volatile memory device according to an embodiment of the invention. Those skilled in the art should realize that the implementation of the present invention is not limited to implementing each step in FIG. 5 one by one or exactly. For example, intermediate steps may be added or local modifications may be made between each step in FIG. 5 .

Referring to FIG. 5 , step 502 is first performed, and power is provided to the memory device 200 in step 502 . Next, in step 504 , an overall status flag OFL corresponding to all memory blocks [0] to [N−1] in the nonvolatile memory device 202 is read. Afterwards, in step 506, it is judged whether the sign value of this overall status flag OFL is logic "1", if not, start the boot according to the boot code stored in this non-volatile memory element 202; if yes, check each The status flag FL is used to confirm which flag value is logic "1".

In step 508, if the value of the state flag FL is logic "1", it means that the corresponding block has not completed a complete erasing operation, for example, the OEC operation has not yet been performed. Therefore, in step 510 , a leakage current suppression procedure must be performed on the block corresponding to the state flag value of logic “1”. Then, in step 512, the booting can be performed according to the boot code stored in the non-volatile memory element 202 .

Referring to FIG. 2 , the overall status flag OFL is generated by the OR gate circuit 206 . The overall status flag OFL is used to indicate whether any incomplete erase operation has occurred. If the flag value of the overall state flag OFL is logic "1", it means that there is one or more than one memory block that has not completed the erasing method 400, so the control unit 208 will sequentially read the corresponding memory block [0] To [N-1] the flag value of the status flag to find the block corresponding to the flag value of logic "1". Then, a leakage current suppression process is applied to the unselected memory cells in the found block, so as to ensure that the sense amplifier in FIG. 3 will not sense wrong current when performing the power-on process.

The details of the leakage current suppression program will be described in detail below with examples. When the flag value of the overall state flag OFL is logic "0", it means that all the memory blocks [0] to [N-1] in the non-volatile memory element 202 have completely performed the pre-programming operation, erased operation and OEC operation. In this case, the first bias voltage generator 212 in FIG. 2 will apply a first bias voltage, that is, a normal bias voltage will be applied to the unselected memory crystals in the memory blocks. cell. On the contrary, when the flag value of the overall status flag OFL is logic “1”, it indicates that at least one memory block in the non-volatile memory element 202 has not completed a complete erasing operation. In this case, the second bias voltage generator 214 in FIG. 2 will apply a second bias voltage, that is, a suppression bias voltage will be applied to all unselected memories in the memory blocks. cells, or at least all unselected memory cells in the power-on block. In this embodiment, the second bias voltage is a negative voltage, and the voltage value is sufficient to cut off an over-erased memory cell. In step 512 , the system is powered on according to the boot code stored in the non-volatile memory element 202 . After the system is powered on successfully, the memory block corresponding to the flag value of the state flag FL with a logic “1” will be repaired or maintained at the original state.

FIG. 6 shows a flowchart of a method 600 for booting a system using a non-volatile memory device according to another embodiment of the present invention. Those skilled in the art should realize that the implementation of the present invention is not limited to implementing each step in FIG. 6 one by one or exactly. For example, intermediate steps may be added or local modifications may be made between each step in FIG. 6 .

Referring to FIG. 6 , step 602 is first performed, and power is provided to the memory device 200 in step 602 . Next, in step 604 , an overall status flag OFL corresponding to all memory blocks [0] to [N−1] in the nonvolatile memory device 202 is read. Afterwards, in step 606 , check whether the flag value of the overall state flag OFL is logic “1”, if yes, go to step 608 , if not, go to step 612 . In step 608, the flag value of each of the status flags FL[0] to FL[N-1] is checked. In step 610 , a leakage repair operation is performed on the memory block corresponding to the flag value of logic “1”. In step 612 , the system is powered on according to the boot code stored in the non-volatile memory element 202 .

Referring to FIG. 2 , the overall status flag OFL is generated by the OR gate circuit 206 . The overall status flag OFL is used to indicate whether any incomplete erase operation has occurred. In step 604, the flag value of the overall status flag OFL is read. In step 606, if the flag value of the overall state flag OFL is logic "0", step 612 will be performed; if the flag value of the overall state flag OFL is logic "1", in step 608, the control unit 208 will A checking operation is further performed on each of the status flags FL[0] to FL[N−1]. This is because if the flag value of the overall state flag OFL is logic "1", it means that at least one memory block in the non-volatile memory element 202 has not completed the complete erasing step, so the control unit 208 will find out The block corresponding to the flag value of logic "1". Then, the leakage current correction unit 210 performs a leakage repair operation on all memory cells of the found block, so as to ensure that the sense amplifier in FIG. 3 does not occur when the system tries to read the associated block. Misjudgment situation. More specifically, when the overall status flag OFL indicates that at least one memory block has not completed a complete erasing step, the re-erase unit 216 performs a re-erase operation on all memory cells in the memory block.

Therefore, the potential problem of starting up in the prior art can be avoided through the method disclosed in the present invention. The stability of the system can be improved, and the associated memory blocks sharing the same bit line will not have the phenomenon of bit line leakage.

The technical content and technical features of the present invention have been disclosed above, but those skilled in the art may still make various substitutions and modifications based on the teaching and disclosure of the present invention without departing from the spirit of the present invention. Therefore, the protection scope of the present invention should not be limited to those disclosed in the embodiments, but should include various replacements and modifications that do not depart from the present invention, and should be covered by the protection scope of the appended claims.

Claims (11)

1. a kind of method booted up using a non-volatile memory device to a system, the non-volatile memory device Include boot block and multiple data blocks, wherein depositing in the memory crystal cell and the plurality of data block in the boot block Reservoir structure cell is electrically connected to identical bit line, and this method includes：

When the system power supply, reading corresponds to the boot block and the plurality of data block in the non-volatile memory device A Status Flag, the value of statistical indicant instruction of the Status Flag applies to a complete fortune of erasing of the non-volatile memory device Whether work has been completed；

One is optionally performed to the corresponding boot block and the plurality of data block according to the value of statistical indicant of the Status Flag Drain current suppressing program；And

A boot code according to being stored in the boot block boots up to the system.

2. the method as described in claim 1, wherein this is according to the value of statistical indicant of Status Flag start area corresponding to this Block and the plurality of data block optionally perform the step of drain current suppressing program and included：

When the complete running of erasing that Status Flag instruction applies to the non-volatile memory device has been completed, apply Non-selected memory crystal cell in one first bias voltage to boot block and the plurality of data block；And

When the complete running of erasing that Status Flag instruction applies to the non-volatile memory device does not complete, apply Non-selected memory crystal cell in one second bias voltage to boot block and the plurality of data block；

Wherein, the magnitude of voltage of second bias voltage is less than the magnitude of voltage of first bias voltage.

3. method as claimed in claim 2, wherein second bias voltage are a negative voltage, and magnitude of voltage is enough to end a mistake Erasing memory structure cell.

4. the method as described in claim 1, also include：

After the system boot, leakage current reparation running is performed to the plurality of data block.

5. the method as described in claim 1, wherein this is according to the value of statistical indicant of Status Flag start area corresponding to this Block and the plurality of data block optionally perform the step of drain current suppressing program and included：

When the complete running of erasing that Status Flag instruction applies to the non-volatile memory device does not complete, to this Memory crystal cell in multiple data blocks is erased running again.

6. start area that the method as described in claim 1, the wherein reading are corresponded in the non-volatile memory device The step of block and the Status Flag of the plurality of data block, includes：

Read a Status Flag of each data block in the non-volatile memory device；And

By performing one or computing to all Status Flags of the data block, use and obtain a total Status Flag；And the party Method also includes：

Total Status Flag is checked to confirm whether there is an at least data block not complete in the non-volatile memory device Complete step of erasing.

7. a kind of storage arrangement, including：

One non-volatile memory device, comprising boot block and multiple data blocks, the memory crystal cell in the boot block Identical bit line is electrically connected to the memory crystal cell in the plurality of data block；

One status register, the non-volatile memory device is electrically connected to, it is configured to store a Status Flag, the state Indicate to indicate to apply to the complete running of erasing of one in the non-volatile memory device whether completed；

One control unit, it is configured to read the value of statistical indicant of the Status Flag after storage arrangement power supply；And

One Leakage Current Calibration Method unit, is electrically connected to the control unit, and it is configured with the value of statistical indicant according to the Status Flag to institute State non-volatile memory device and optionally perform a drain current suppressing program, to complete boot program.

8. storage arrangement as claimed in claim 7, wherein the Leakage Current Calibration Method unit include：

One first bias voltage generator, it is configured with when Status Flag instruction applies into the non-volatile memory device The complete running of erasing when having completed, apply one first bias voltage into the boot block and the plurality of data block Non-selected memory crystal cell；And

One second bias voltage generator, it is configured with when Status Flag instruction applies into the non-volatile memory device The complete running of erasing when not completing, apply and be not chosen in one second bias voltage to the non-volatile memory device The memory crystal cell selected；

Wherein, the magnitude of voltage of second bias voltage is less than the magnitude of voltage of first bias voltage.

9. storage arrangement as claimed in claim 8, wherein second bias voltage are a negative voltage, and magnitude of voltage is enough to cut Only one cross erasing memory structure cell.

10. storage arrangement as claimed in claim 7, wherein the Leakage Current Calibration Method unit include：

Erased cell again and again, its configure with when Status Flag instruction apply in the non-volatile memory device this is complete Erase running do not complete when, running of being erased again and again to the plurality of data interval.

11. storage arrangement as claimed in claim 7, is also included：

Multiple status registers；And

One OR circuit, the status register is electrically connected to, it is configured to produce a total Status Flag；

Wherein, the control unit reads the value of statistical indicant of total Status Flag after storage arrangement power supply, and works as total state Mark indicate the non-volatile memory device do not complete it is complete erase running when, the control unit individually reads the shape State register does not complete the data block of complete running of erasing to find out.