CN104536504B - A kind of self-starting reference circuit - Google Patents

Abstract

The invention discloses a kind of self-starting reference circuit.Reference circuit is the module that mimic channel is conventional; the present invention is a kind of reference circuit containing self-starting; " degeneracy " bias point problem that usual reference circuit exists; when namely powering on, the electric current of all crystals pipe transmission is the problem of zero; self-start circuit can by biasing circuit from power on time " zero current " mode boot to normal mode of operation; and this start-up circuit structure is simple, the electric current of consumption is extremely low, namely achieves a kind of low-power consumption self-starting reference circuit.

Description

A kind of self-starting reference circuit

Technical field

The present invention relates generally to the design field of reference circuit, refers in particular to a kind of self-starting reference circuit.

Background technology

For Analogous Integrated Electronic Circuits, the quality of its performance depends on several factors, and the stability of reference voltage, reference current is also one of them very important factor.The circuit form of reference voltage, reference current is a lot, respectively there are relative merits, bootstrap reference is wherein a kind of circuit form, it is by the voltage generation current on active device, and with the electric current of this circuit as this active device, the reference voltage irrelevant with supply voltage and reference current so can be obtained.But this biasing circuit had nothing to do with power supply of such as bootstrap reference has a very important problem, the i.e. existence of " degeneracy " bias point, this is that himself electric circuit characteristic determines, when namely powering on, the electric current of all crystals pipe transmission is zero, and circuit a kind ofly can keep this state.This characteristic of biasing circuit makes circuit probably lose efficacy, and this just needs a start-up circuit, the object of this circuit be exactly when biasing circuit powers on by it from " zero current " mode boot to normal mode of operation.

Summary of the invention

The problem to be solved in the present invention is just: the technical matters existed for prior art, proposes a kind of self-starting reference circuit.

The solution that the present invention proposes is: the present invention is a kind of reference circuit containing self-starting; " degeneracy " bias point problem that usual reference circuit exists; when namely powering on, the electric current of all crystals pipe transmission is the problem of zero; self-start circuit can by biasing circuit from power on time " zero current " mode boot to normal mode of operation; and this start-up circuit structure is simple; the electric current consumed is extremely low, namely achieves a kind of low-power consumption self-starting reference circuit.

Accompanying drawing explanation

Fig. 1 is circuit theory schematic diagram of the present invention.

Embodiment

Below with reference to accompanying drawing and concrete enforcement, the present invention is described in further details.

As shown in Figure 1, the PMOS M in bootstrap reference circuit ₆and M ₇measure-alike, PMOS M ₈, M ₉, M ₁₀measure-alike, suppose M ₈, M ₉, M ₁₀leakage current I _dSbe respectively I ₁, I ₂and I ₃, then electric current I ₁=I ₂=I ₃, and this current value depends on threshold voltage and the resistance R of metal-oxide-semiconductor ₀resistance and metal-oxide-semiconductor technological parameter; Namely

$I_1\∝\frac{k}{{\mathrm{\μ}}_n{C}_{\mathrm{ox}}\frac{W}{L}}\·\frac{1}{R_0^2}$

I can be found out ₁have nothing to do with power vd D, then reference voltage also has nothing to do with power supply.But this benchmark exists a very serious problem, namely there is " degeneracy " bias point, namely when circuit powers on, all metal-oxide-semiconductors in bootstrap reference all may transmit zero current, i.e. I ₁=I ₂=I ₃=0, and this state can keep always, thus circuit cannot normally be worked, " zero current " mode boot when now just to need bootstrap reference circuit from power on, to normal mode of operation, namely as the start-up circuit in Fig. 1, works as I ₁=I ₂=I ₃when=0, NMOS tube M ₃grid voltage is 0, M ₃, M ₁₁and M ₁₂all end, PMOS M ₆, M ₇, M ₈, M ₉, M ₁₀electric current be all 0, PMOS M ₁, M ₂conducting, then NMOS tube M ₄, M ₅grid be high level, M ₄, M ₅conducting, PMOS M ₆, M ₇, M ₈, M ₉, M ₁₀conducting, the electric current that now just existence one is non-vanishing is through PMOS M ₆, M ₇, M ₈, M ₉, M ₁₀, so far, bootstrap reference is broken away from from " zero current ", and NMOS tube M ₃enter conducting state, due to PMOS M ₁, M ₂all be down than pipe, i.e. W/L<1, namely conducting resistance is very large, M ₃conducting makes M ₃drain voltage reduces, and finally makes M ₄, M ₅cut-off, since then, bootstrap reference enters normal therefrom pattern.In addition, due to PMOS M ₁, M ₂w/L<<1, so electric current is extremely low on this branch road, negligible.

In sum, this circuit can by bootstrap reference circuit from power on time " zero current " mode boot to normal mode of operation, and this start-up circuit structure is simple, and the electric current of consumption is extremely low, namely achieves a kind of self-starting reference circuit.

Claims (1)

1. a self-starting reference circuit, is characterized in that:

Circuit is made up of start-up circuit and bootstrap reference; Start-up circuit is by PMOS M ₁, PMOS M ₂, NMOS tube M ₃, NMOS tube M ₄, NMOS tube M ₅composition, PMOS M1, M2 are down than pipe, wherein PMOS M ₁, M ₂grounded-grid, PMOS M ₁source electrode meets power vd D, and drain electrode meets PMOS M ₂source electrode, PMOS M ₂drain electrode meets NMOS tube M ₃drain electrode and NMOS tube M ₄, M ₅grid, NMOS tube M ₃, M ₄, M ₅source ground; NMOS tube M ₄drain electrode be connected to PMOS M ₆grid, drain electrode and PMOS M ₈source electrode; NMOS tube M ₅drain electrode be connected to PMOS M ₁₀grid, drain electrode and PMOS M ₈, M ₉grid and NMOS tube M ₁₂drain electrode; The M of PMOS ₈drain electrode is connected to resistance R ₀one end, R ₀other end ground connection; PMOS M ₉source electrode is connected to M ₇drain electrode, M ₉drain electrode be connected to NMOS tube M ₁₁drain electrode, grid and NMOS tube M ₁₂, M ₃grid, NMOS tube M ₁₁and M ₁₂source ground, PMOS M ₆, M ₇, M ₁₀source electrode meet power vd D.