CN102468646A

CN102468646A - Overvoltage protection circuit used for USB analog switch under charged/uncharged condition

Info

Publication number: CN102468646A
Application number: CN2010105315885A
Authority: CN
Inventors: 鞠建宏; 郝跃国
Original assignee: DIOO MICROELECTRONIC Co Ltd
Current assignee: DIOO MICROELECTRONIC Co Ltd
Priority date: 2010-11-04
Filing date: 2010-11-04
Publication date: 2012-05-23

Abstract

The invention discloses an overvoltage protection circuit used for a USB analog switch under a charged/uncharged condition. A source electrode of a first P type field effect transistor is connected with the source electrode of a third P type field effect transistor and then is connected with the signal input terminal of the USB analog switch. The grid electrode of the first P type field effect transistor is connected with a power supply voltage, a drain electrode is connected with the substrate of the first P type field effect transistor itself and the signal output terminal of the USB analog switch. The grid electrode of a second P type field effect transistor is simultaneously connected with the drain electrodes of a third P type field effect transistor and a N type field effect transistor, and the source electrode is connected with the power supply voltage and the drain electrode is connected with the substrate of the second P type field effect transistor itself and the signal output terminal. The grid electrode of the third P type field effect transistor is connected with the power supply voltage and the substrate is connected with the signal output terminal. The grid electrode of the N type field effect transistor is connected with the power supply voltage and the source electrode is connected with the substrate of the N type field effect transistor itself. By using the circuit of the invention, a leakage current situation caused by opening of a parasitic diode can be prevented.

Description

Be used for the overvoltage crowbar under the charged/power-down conditions of USB analog switch

Technical field

The present invention relates to a kind of overvoltage crowbar, more particularly, is the overvoltage crowbar under a kind of charged/power-down conditions of the USB of being suitable for analog switch.

Background technology

In the USB analog switch that adopts the CMOS structure to design, the power of voltage ratio voltage (VCC) of input/output port under the normal operation (like A among Fig. 1 or B) is low, like this can assurance figure in two parasitic diodes of PMOS be in reverse blocking state.If under charged situation; It is high that the power of voltage ratio voltage of input/output port is wanted, and perhaps promptly do not have under the situation of supply voltage in power down, and input/output port still has bigger voltage; This moment, the parasitic diode of PMOS will be in the forward conduction state; Promptly have very big leakage current to flow out through these two parasitic diodes, this is can not be received, therefore needs the generation that special protective circuit prevents this situation.

Requirement to this protective circuit is, need the voltage and the supply voltage of input/output port be compared, from wherein selecting higher N trap (n-well) bias voltage as cmos switch.A patent No. is 6; 163; Solution like Fig. 2 has been proposed in 199 the United States Patent (USP); It selects both among higher voltage Pvcc after relatively with the PMOS of pair of cross coupling between supply voltage VCC and input/output port A (or B), the N trap (n-well) of managing in order to PMOS inside the biasing cmos switch.The disadvantage of this way is; When the voltage of the voltage of input/output port and VCC does not have obviously difference; The comparing function of circuit will disappear, and the actual Pvcc that obtains will be voltage or the VCC that has passed through the drain terminal/input/output port that the substrate parasitic diode passes among the cross-linked PMOS, i.e. Pvcc ≈ A (perhaps B; Or VCC)-and 0.7V, still can cause very big leakage current in this case.

Summary of the invention

Owing to the problems referred to above that prior art exists, the objective of the invention is to propose a kind of overvoltage crowbar of the USB of being used for analog switch, it can effectively solve the problem that prior art exists.

For realizing above-mentioned purpose; Overvoltage crowbar under the charged/power-down conditions that is used for the USB analog switch that the present invention proposes; Comprise first, second, third P type FET and a N type FET; After linking to each other, the source electrode of the source electrode of a said P type FET and the 3rd P type FET links to each other with the signal input part of USB analog switch; And a P type FET grid link to each other with supply voltage, drain electrode links to each other with the substrate of itself and the signal output part of USB analog switch simultaneously; The grid of the 2nd P type FET links to each other with the drain electrode of the 3rd P type FET, N type FET simultaneously, and its source electrode links to each other with supply voltage, and the while that drains links to each other with said signal output part with the substrate of itself; The grid of said the 3rd P type FET links to each other with supply voltage, and its substrate links to each other with said signal output part; The grid of said N type FET links to each other with supply voltage, and its source electrode links to each other with the substrate of itself.

Owing to adopt above technical scheme; Overvoltage crowbar under the charged/power-down conditions of the USB of being used for analog switch of the present invention can be that the N trap of the PMOS the inside of cmos switch provides correct bias voltage under any input/output port voltage and supply voltage situation, and can not take place to open the leakage current that causes because of parasitic diode.

Description of drawings

Fig. 1 is for adopting the USB analog switch line map of CMOS structure;

Fig. 2 is the line map of 6163199 United States Patent (USP)s for the patent No.;

Fig. 3 is a line map of the present invention;

Fig. 4 is a specific embodiment of the present invention.

Embodiment

According to accompanying drawing and specific embodiment the present invention is described further below:

As shown in Figure 3; Overvoltage crowbar under the charged/power-down conditions that is used for the USB analog switch that the present invention proposes; Comprise first, second, third P type FET (being respectively M1 among Fig. 5, M2, M3) and a N type FET M4; After linking to each other, the source electrode of the source electrode of the one P type FET M1 and the 3rd P type FET M3 links to each other with the signal input part A of USB analog switch; And a P type FET M1 grid link to each other with supply voltage VCC, drain electrode links to each other with the substrate of itself and the signal output part of USB analog switch simultaneously; The grid of the 2nd P type FET M2 links to each other with the drain electrode of the 3rd P type FET M3, N type FET M4 simultaneously, and its source electrode links to each other with supply voltage VCC, and the while that drains links to each other with signal output part PVCC with the substrate of itself; The grid of the 3rd P type FET M3 links to each other with supply voltage, and its substrate links to each other with signal output part PVCC; The grid of N type FET links to each other with supply voltage VCC, and its source electrode links to each other with the substrate of itself.

Requirement to this protective circuit of the present invention need compare the voltage and the supply voltage of input/output port exactly, from wherein selecting the N trap bias voltage of the higher person as cmos switch.As shown in Figure 3, in line map of the present invention, the ingenious realization of the antilogical that is VCC of most critical.We are the power supply of the voltage of input/output port as the inverter that is made up of M3 and M4, thereby have obtained the antilogical of VCC, like this; When VCC＞A, M1 turn-offs, simultaneously; Because inverter is output as low level, make M2 open, VCC has just passed to PVCC through M2 like this; When VCC＜A, because inverter output is high level (high level at this moment is exactly A), M2 turn-offs, and M1 opens, so A has just passed to PVCC through M1.When seeing VCC=A again, this moment, M1 turn-offed, was output as low level owing to inverter, thus M2 open, thereby VCC just passes to PVCC through M2.Therefore, under any circumstance, there is not the situation of parasitic diode forward conduction, fundamentally eliminated the generation of leakage current.

Fig. 4 is a specific embodiment of the present invention; M5 and M6 are that a pair of cmos switch is in order to pass through usb signal; Is when M5 protects utilizing the present invention to wherein PMOS pipe; Therefore need consider that at this moment supply voltage VCC has directly been received M1, on the grid of M3 and M4, need add that ESD resistance protects grid; Equally,,, can not bear bigger ESD electric current, also need add esd protection resistance it because the size of M1 own is less because input/output port A this moment has received the source end of M1.

But above-mentioned embodiment is exemplary, is to be the restriction that this patent is comprised scope in order better to make those skilled in the art can understand this patent, can not to be interpreted as; So long as according to spirit that this patent discloses done anyly be equal to change or modify, all fall into the scope that this patent comprises.

Claims

1. the overvoltage crowbar under the charged/power-down conditions that is used for the USB analog switch; It is characterized in that: comprise first, second, third P type FET and a N type FET; After linking to each other, the source electrode of the source electrode of a said P type FET and the 3rd P type FET links to each other with the signal input part of USB analog switch; And a P type FET grid link to each other with supply voltage, drain electrode links to each other with the substrate of itself and the signal output part of USB analog switch simultaneously; The grid of the 2nd P type FET links to each other with the drain electrode of the 3rd P type FET, N type FET simultaneously, and its source electrode links to each other with supply voltage, and the while that drains links to each other with said signal output part with the substrate of itself; The grid of said the 3rd P type FET links to each other with supply voltage, and its substrate links to each other with said signal output part; The grid of said N type FET links to each other with supply voltage, and its source electrode links to each other with the substrate of itself.