CN104517830B - A kind of manufacture method of semiconductor devices - Google Patents
A kind of manufacture method of semiconductor devices Download PDFInfo
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- CN104517830B CN104517830B CN201310454692.2A CN201310454692A CN104517830B CN 104517830 B CN104517830 B CN 104517830B CN 201310454692 A CN201310454692 A CN 201310454692A CN 104517830 B CN104517830 B CN 104517830B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 61
- 238000000034 method Methods 0.000 title claims abstract description 52
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 49
- 150000004767 nitrides Chemical class 0.000 claims abstract description 39
- 230000003647 oxidation Effects 0.000 claims abstract description 37
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 37
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 36
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 36
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 29
- 239000011248 coating agent Substances 0.000 claims abstract description 26
- 238000000576 coating method Methods 0.000 claims abstract description 26
- 230000008569 process Effects 0.000 claims abstract description 24
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 20
- 238000000151 deposition Methods 0.000 claims abstract description 6
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 56
- 239000000463 material Substances 0.000 claims description 37
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 27
- 239000007789 gas Substances 0.000 claims description 27
- 229910021529 ammonia Inorganic materials 0.000 claims description 24
- 229910052757 nitrogen Inorganic materials 0.000 claims description 13
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 12
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 claims description 12
- 238000003860 storage Methods 0.000 claims description 12
- 238000002955 isolation Methods 0.000 claims description 10
- 238000007667 floating Methods 0.000 claims description 9
- 230000014759 maintenance of location Effects 0.000 claims description 9
- 239000001307 helium Substances 0.000 claims description 7
- 229910052734 helium Inorganic materials 0.000 claims description 7
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims description 7
- 229910052786 argon Inorganic materials 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 6
- 239000001301 oxygen Substances 0.000 claims description 6
- 229910052760 oxygen Inorganic materials 0.000 claims description 6
- 150000001875 compounds Chemical class 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 127
- 229910052751 metal Inorganic materials 0.000 description 10
- 239000002184 metal Substances 0.000 description 10
- 229910000069 nitrogen hydride Inorganic materials 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 7
- 239000000470 constituent Substances 0.000 description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 5
- 229910021332 silicide Inorganic materials 0.000 description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- 238000010276 construction Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 229910003978 SiClx Inorganic materials 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical group [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- UGACIEPFGXRWCH-UHFFFAOYSA-N [Si].[Ti] Chemical compound [Si].[Ti] UGACIEPFGXRWCH-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- HTXDPTMKBJXEOW-UHFFFAOYSA-N iridium(IV) oxide Inorganic materials O=[Ir]=O HTXDPTMKBJXEOW-UHFFFAOYSA-N 0.000 description 1
- 238000003701 mechanical milling Methods 0.000 description 1
- QSHDDOUJBYECFT-UHFFFAOYSA-N mercury Chemical compound [Hg] QSHDDOUJBYECFT-UHFFFAOYSA-N 0.000 description 1
- 229910052753 mercury Inorganic materials 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000006396 nitration reaction Methods 0.000 description 1
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- -1 wherein Inorganic materials 0.000 description 1
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Abstract
The present invention provides a kind of manufacture method of semiconductor devices, including：Semiconductor substrate is provided；Implement the first Rapid Thermal Nitrided, the first silicon nitride layer is formed in the region at the close top of Semiconductor substrate；Implement rapid thermal oxidation, silicon oxide layer is formed in the Semiconductor substrate below the first silicon nitride layer；Implement the second Rapid Thermal Nitrided, the second silicon nitride layer is formed in the Semiconductor substrate below silicon oxide layer.According to the present invention, tunnel oxidation layer is constituted without forming extra oxide skin(coating) on a semiconductor substrate by epitaxial growth or depositing operation, so as to reduce process costs, simultaneously, Semiconductor substrate is implemented twice processed by rapid thermal nitridation to form the top nitride layer and bottom nitride layer of tunnel oxidation layer respectively, the control problem of the interfacial characteristics between bottom nitride layer and tunnel oxidation layer can effectively be solved, the plasma nitrided control problem for forming the N doping depth that top nitride layer is brought of dipole is avoided passing through, it is simple and easy to apply.
Description
Technical field
The present invention relates to semiconductor fabrication process, in particular to a kind of tunnel oxygen of formation NAND flash storages
Change layer（tunnel oxide）Method.
Background technology
NAND flash storages are one kind of flash storage, and it is internal using non-linear macroelement pattern, is solid-state
The realization of Large Copacity internal memory provides cheap effective solution.NAND flash storages have capacity larger, rewrite speed
The advantages of spending fast, it is adaptable to the storage of mass data, thus in the industry cycle obtained increasingly being widely applied, such as by NAND
Flash storage is applied to embedded product, including digital camera, MP3 walkmans memory card, USB flash disk of compact etc..
With the increasingly decline of semiconductor fabrication process node, for the important component tunnel of NAND flash storages
For road oxide layer, the reduction of its characteristic size and the reduction of the reliability produced therewith are badly in need of as semiconductor fabrication process
The important topic of solution.The existing technique for forming tunnel oxidation layer comprises the following steps：
First, as shown in Figure 1A there is provided Semiconductor substrate 100, the constituent material of Semiconductor substrate 100, which can be used, not to be mixed
Miscellaneous monocrystalline silicon, the monocrystalline silicon doped with impurity, silicon-on-insulator（SOI）Deng.
Then, as shown in Figure 1B, oxide skin(coating) 101 is formed on a semiconductor substrate 100 using epitaxial growth technology.Oxidation
The preferred silica of material of nitride layer 101（SiO2）.
Then, as shown in Figure 1 C, using going dipole plasma nitrided（decoupled plasma nitridation）Work
Skill implements N doping in the region at the top of it of oxide skin(coating) 101, then carries out post-nitridation anneal (post nitration
Anneal) handle, finally form top nitride layer 102 in the region at the top of it of oxide skin(coating) 101.
Then, as shown in figure iD, aoxidized using quick hot nitrogen（rapid thermal nitridation oxidation）
Technique is in the region at the top of it of Semiconductor substrate 100（Neighbouring Semiconductor substrate 100 and oxygen i.e. in Semiconductor substrate 100
The region at the interface between compound layer 101）Form bottom nitride layer 102 '.
Nitride layer, the nitride are respectively provided with the top and bottom of the tunnel oxidation layer formed by above-mentioned technical process
Layer can greatly improve the reliability of tunnel oxidation layer.But, the cost for implementing above-mentioned technical process is higher, forms top nitride
What nitride layer 102 was implemented goes dipole plasma nitridation process to there is control problem of N doping depth etc., forms bottom nitride
There is control problem of interfacial characteristics between bottom nitride layer 102 ' and oxide skin(coating) 101 etc. in layer 102 '.
It is, therefore, desirable to provide a kind of method, to solve the above problems.
The content of the invention
In view of the shortcomings of the prior art, the present invention provides a kind of manufacture method of semiconductor devices, including：Semiconductor is provided
Substrate；Implement the first Rapid Thermal Nitrided, the first silicon nitride layer is formed in the region at the close top of the Semiconductor substrate；Implement
Rapid thermal oxidation, silicon oxide layer is formed in the Semiconductor substrate below first silicon nitride layer；Implement the second quick hot nitrogen
Change, the second silicon nitride layer is formed in the Semiconductor substrate below the silicon oxide layer.
Further, the semiconductor devices is NAND flash storages.
Further, the silicon oxide layer constitutes the tunnel oxidation layer of the NAND flash storages, first nitridation
Silicon layer and second silicon nitride layer respectively constitute the top nitride layer and bottom nitride layer of the tunnel oxidation layer.
Further, the process conditions of first Rapid Thermal Nitrided are：600-1100 DEG C of temperature, pressure 0.5-760torr,
At least one in combination of the gas component selected from ammonia, ammonia and argon gas, the combination of ammonia and nitrogen, the combination of ammonia and helium
Kind, gas flow 500sccm-50slm, processing time 5-300s.
Further, the process conditions of second Rapid Thermal Nitrided are：900-1100 DEG C of temperature, pressure 0.5-760torr,
Gas component is selected from the combination of combination, the combination of ammonia and nitrogen, ammonia and the helium of nitric oxide, ammonia, ammonia and argon gas
At least one of, gas flow 500sccm-50slm, processing time 5-300s.
Further, the process conditions of the rapid thermal oxidation are：600-1100 DEG C of temperature, pressure 0.5-760torr, gas
Component is selected from least one of oxygen, nitric oxide, gas flow 500sccm-50slm, processing time 5-300s.
Further, before implementing first Rapid Thermal Nitrided, be additionally included in the Semiconductor substrate sequentially form every
The step of from structure and well region.
Further, after implementing second Rapid Thermal Nitrided, be additionally included in the Semiconductor substrate formed floating boom and
The step of control gate.
Further, the step of forming the floating boom and the control gate includes：Sunk successively on first silicon nitride layer
Product first grid material layer, the first oxide skin(coating), nitride layer, the second oxide skin(coating) and second grid material layer；Etch successively
The second grid material layer, second oxide skin(coating), the nitride layer, first oxide skin(coating), the first grid
Pole material layer, first silicon nitride layer, the silicon oxide layer and second silicon nitride layer.
Further, the floating boom is by the first grid material layer being laminated from top to bottom, first silicon nitride layer, institute
State silicon oxide layer and second silicon nitride layer to constitute, the control gate is by the second grid material that is laminated from top to bottom
Layer, second oxide skin(coating), the nitride layer and first oxide skin(coating) are constituted.
According to the present invention, without forming extra oxide skin(coating) on a semiconductor substrate by epitaxial growth or depositing operation
Constitute tunnel oxidation layer, so as to reduce process costs, meanwhile, Semiconductor substrate is implemented twice processed by rapid thermal nitridation with respectively
The top nitride layer and bottom nitride layer of tunnel oxidation layer are formed, bottom nitride layer and tunnel oxidation can be effectively solved
The control problem of interfacial characteristics between layer, it is to avoid by going dipole is plasma nitrided to form the nitrogen that top nitride layer is brought
The control problem of doping depth, it is simple and easy to apply.
Brief description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, for explaining the principle of the present invention.
In accompanying drawing：
The device that obtains respectively of the step of Figure 1A-Fig. 1 D is implement according to the technique of existing formation tunnel oxidation layer successively
The schematic cross sectional view of part；
Fig. 2A-Fig. 2 D are the device that is obtained respectively the step of implementation successively according to the method for exemplary embodiment of the present
Schematic cross sectional view；
Fig. 3 is the flow chart that tunnel oxidation layer is formed according to the method for exemplary embodiment of the present.
Embodiment
In the following description, a large amount of concrete details are given to provide more thorough understanding of the invention.So
And, it is obvious to the skilled person that the present invention can be able to without one or more of these details
Implement.In other examples, in order to avoid obscuring with the present invention, do not enter for some technical characteristics well known in the art
Row description.
In order to thoroughly understand the present invention, detailed step will be proposed in following description, to explain proposition of the present invention
Formation tunnel oxidation layer method.Obviously, execution of the invention is not limited to the technical staff of semiconductor applications and is familiar with
Specific details.Presently preferred embodiments of the present invention is described in detail as follows, but in addition to these detailed descriptions, the present invention can be with
With other embodiment.
It should be appreciated that when using term "comprising" and/or " comprising " in this manual, it is indicated in the presence of described
Feature, entirety, step, operation, element and/or component, but do not preclude the presence or addition of other one or more features, entirety,
Step, operation, element, component and/or combinations thereof.
[exemplary embodiment]
Below, reference picture 2A- Fig. 2 D and Fig. 3 form tunnel oxidation to describe method according to an exemplary embodiment of the present invention
The detailed step of layer.
Reference picture 2A- Fig. 2 D, illustrated therein is method according to an exemplary embodiment of the present invention and implement the step of institute successively
The schematic cross sectional view of the device obtained respectively.
First, as shown in Figure 2 A there is provided Semiconductor substrate 200, the constituent material of Semiconductor substrate 200, which can be used, not to be mixed
Miscellaneous monocrystalline silicon, the monocrystalline silicon doped with impurity, silicon-on-insulator（SOI）Deng.As an example, in the present embodiment, semiconductor
The constituent material of substrate 200 selects monocrystalline silicon.
Next, isolation structure is formed in Semiconductor substrate 200, to put it more simply, being omitted in diagram.As showing
Example, isolation structure is that shallow trench isolates (STI) structure or selective oxidation silicon (LOCOS) isolation structure.In the present embodiment, every
It is fleet plough groove isolation structure from structure, its forming process generally includes following steps：Hard mask is formed on semiconductor substrate 200
Layer, the various suitable technology formation hard mask layers being familiar with using those skilled in the art, such as chemical vapor deposition
Technique, the preferred silicon nitride of material of hard mask layer；Patterned hard mask layer, shallow trench isolation is constituted to be formed in hard mask layer
The opening of the pattern of structure, the process includes：The photoresist of the pattern with fleet plough groove isolation structure is formed on hard mask layer
Layer, using the photoresist layer as mask, etching hard mask layer is until expose Semiconductor substrate 200, using cineration technics removal institute
State photoresist layer；Using the hard mask layer of patterning as mask, etch in the semiconductor substrate for forming shallow trench isolation junction
The groove of structure；Depositing isolation material in the trench and on hard mask layer, the isolated material is usually oxide, this reality
Apply in example, the isolated material is HARP；Chemical mechanical milling tech is performed to grind the isolated material, is covered firmly until exposing
Film layer；Hard mask layer is removed by etching.
Then, trap (well) area is formed in Semiconductor substrate 200, to put it more simply, being omitted in diagram.Form well region
Process generally include following steps：The photoresist layer with well region pattern, completely obscured institute are formed on semiconductor substrate 200
State fleet plough groove isolation structure；Using the photoresist layer as mask, implement well region injection to form trap in Semiconductor substrate 200
Area；The photoresist layer is removed using cineration technics.
Then, as shown in Figure 2 B, the first Rapid Thermal Nitrided is implemented（rapid thermal nitridation）, partly leading
The region at the close top of body substrate 200 forms the first silicon nitride layer 201.The process conditions of first Rapid Thermal Nitrided are：
600-1100 DEG C of temperature, pressure 0.5-760torr, gas component is selected from ammonia（NH3）, ammonia and argon gas combination（NH3/Ar）、
The combination of ammonia and nitrogen（NH3/N2）, ammonia and helium（NH3/He）At least one of combination, gas flow 500sccm-
50slm, wherein processing time 5-300s, torr represent millimetres of mercury, and sccm represents cc/min, slm representatives liter/min
Clock.
Then, as shown in Figure 2 C, rapid thermal oxidation is implemented（rapid thermal oxidation）, in silicon nitride layer 201
Silicon oxide layer 202 is formed in the Semiconductor substrate 200 of lower section.The process conditions of the rapid thermal oxidation are：Temperature 600-1100
DEG C, pressure 0.5-760torr, gas component is selected from oxygen（O2）, nitric oxide（NO）At least one of, gas flow
500sccm-50slm, processing time 5-300s.
Then, as shown in Figure 2 D, implement in the second Rapid Thermal Nitrided, the Semiconductor substrate 200 below silicon oxide layer 202
Form the second silicon nitride layer 201 '.The process conditions of second Rapid Thermal Nitrided are：900-1100 DEG C of temperature, pressure 0.5-
760torr, gas component is selected from nitric oxide（NO）, ammonia（NH3）, ammonia and argon gas combination（NH3/Ar）, ammonia and nitrogen
Combination（NH3/N2）, ammonia and helium（NH3/He）At least one of combination, gas flow 500sccm-50slm, processing
Time 5-300s.
So far, the processing step that method according to an exemplary embodiment of the present invention is implemented is completed, silicon oxide layer 202 is constituted
The tunnel oxidation layer of NAND flash storages, the first silicon nitride layer 201 constitutes the top nitride layer of tunnel oxidation layer, second
Silicon nitride layer 201 ' constitutes the bottom nitride layer of tunnel oxidation layer.
Next, it is possible to implement conventional semiconductor devices front end fabrication process：
In an exemplary embodiment, first, be sequentially depositing on the first silicon nitride layer 201 first grid material layer,
First oxide skin(coating), nitride layer, the second oxide skin(coating) and second grid material layer.
The constituent material of first grid material layer and second grid material layer includes polysilicon, metal, conductive metal nitrogen
One or more in compound, conductive metal oxide and metal silicide, wherein, metal can be tungsten（W）, nickel（Ni）Or
Titanium（Ti）；Conductive metal nitride includes titanium nitride（TiN）；Conductive metal oxide includes yttrium oxide（IrO2）；Metal
Silicide includes titanium silicide（TiSi）.It is preferred that composition material of the polysilicon as first grid material layer and second grid material layer
Material, now can select low-pressure chemical vapor deposition (LPCVD) technique formation gate material layers, and its process conditions includes：Reaction gas
Body is silane (SiH4), its flow is 100~200sccm, preferably 150sccm；Temperature in reaction chamber is 700~750 DEG C；Instead
The pressure for answering intracavitary is 250~350mTorr, preferably 300mTorr；The reacting gas can also include buffer gas, described
Buffer gas is helium (He) or nitrogen（N2）, its flow is 5~20 liters/min (slm), preferably 8slm, 10slm or 15slm.
The preferred silicon nitride of constituent material of nitride layer, the preferred silica of the constituent material of the first oxide skin(coating) and the second oxide skin(coating).
Next, etching second grid material layer, the second oxide skin(coating), nitride layer, the first oxide skin(coating), first successively
Gate material layers, the first silicon nitride layer 201, the silicon nitride layer 201 ' of silicon oxide layer 202 and second, with semiconductor substrate 200
Formed by the first grid material layer being laminated from top to bottom, the first silicon nitride layer 201, the silicon nitride layer of silicon oxide layer 202 and second
201 ' constitute floating booms and by the second grid material layer being laminated from top to bottom, the second oxide skin(coating), nitride layer and the first oxygen
The control gate that compound layer is constituted.
Then, the side wall construction against floating boom and control gate is formed in the both sides of floating boom and control gate, its constituent material is
SiO2, one kind or combinations thereof in SiN, SiON.Then, using side wall construction as mask, LDD injections are performed, in side wall
LDD injection regions are formed in the Semiconductor substrate 200 of structure both sides.Side wall knot is abutted next, being formed in the both sides of side wall construction
The offset side wall of structure, as an example, offset side wall includes at least one layer of oxide skin(coating) and/or nitride layer.Then, to offset side
Wall is mask, performs source/drain region injection, source/drain region is formed in the Semiconductor substrate 200 of offset side wall both sides.
Then, implement self-alignment silicide technology, autoregistration silication is formed on the top and source/drain region of control gate
Thing.Then, sequentially form and be situated between with the contact etch stop layer and interlayer that can produce stress characteristics on semiconductor substrate 200
Electric layer, forms contact of the connection positioned at the top of control gate and the self-aligned silicide on source/drain region in interlayer dielectric layer
Hole, fills metal（Usually tungsten）The contact plug of connection interconnecting metal layer and the self-aligned silicide is formed in contact hole.
Next, it is possible to implement conventional semiconductor devices back end fabrication, including：The shape of multiple interconnecting metal layers
Into generally being completed using dual damascene process；The formation of metal pad, for implementing wire bonding during device encapsulation.
According to the present invention, without forming extra oxidation on semiconductor substrate 200 by epitaxial growth or depositing operation
Nitride layer constitutes tunnel oxidation layer, so that process costs are reduced, meanwhile, Semiconductor substrate 200 is implemented at Rapid Thermal Nitrided twice
Manage to form the top nitride layer and bottom nitride layer of tunnel oxidation layer respectively, can effectively solve bottom nitride layer with
The control problem of interfacial characteristics between tunnel oxidation layer, it is to avoid by going dipole is plasma nitrided to form top nitride layer institute
The control problem for the N doping depth brought, it is simple and easy to apply.
Reference picture 3, illustrated therein is the flow chart of method formation tunnel oxidation layer according to an exemplary embodiment of the present invention,
Flow for schematically illustrating whole manufacturing process.
There is provided Semiconductor substrate in step 301；
In step 302, implement the first Rapid Thermal Nitrided, the first nitrogen is formed in the region at the close top of Semiconductor substrate
SiClx layer；
In step 303, implement rapid thermal oxidation, silica is formed in the Semiconductor substrate below the first silicon nitride layer
Layer；
In step 304, implement the second Rapid Thermal Nitrided, the second nitrogen is formed in the Semiconductor substrate below silicon oxide layer
SiClx layer.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and the purpose of explanation, and be not intended to limit the invention in described scope of embodiments.In addition people in the art
Member according to the teachings of the present invention it is understood that the invention is not limited in above-described embodiment, can also make more kinds of
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (10)
1. a kind of manufacture method of semiconductor devices, including：
Semiconductor substrate is provided；
Implement the first Rapid Thermal Nitrided, the first silicon nitride layer is formed in the region at the close top of the Semiconductor substrate；
Implement rapid thermal oxidation, silicon oxide layer is formed in the Semiconductor substrate below first silicon nitride layer；
Implement the second Rapid Thermal Nitrided, the second silicon nitride layer is formed in the Semiconductor substrate below the silicon oxide layer, wherein,
First silicon nitride layer, the silicon oxide layer and second silicon nitride layer are laminated from top to bottom.
2. according to the method described in claim 1, it is characterised in that the semiconductor devices is NAND flash storages.
3. method according to claim 2, it is characterised in that the silicon oxide layer constitutes the NAND flash storages
Tunnel oxidation layer, first silicon nitride layer and second silicon nitride layer respectively constitute the top nitrogen of the tunnel oxidation layer
Compound layer and bottom nitride layer.
4. according to the method described in claim 1, it is characterised in that the process conditions of first Rapid Thermal Nitrided are：Temperature
600-1100 DEG C, pressure 0.5-760torr, gas component is selected from the group of ammonia, the combination of ammonia and argon gas, ammonia and nitrogen
At least one of combination of conjunction, ammonia and helium, gas flow 500sccm-50slm, processing time 5-300s.
5. according to the method described in claim 1, it is characterised in that the process conditions of second Rapid Thermal Nitrided are：Temperature
900-1100 DEG C, pressure 0.5-760torr, gas component be selected from nitric oxide, ammonia, the combination of ammonia and argon gas, ammonia and
At least one of combination of the combination of nitrogen, ammonia and helium, gas flow 500sccm-50slm, processing time 5-300s.
6. according to the method described in claim 1, it is characterised in that the process conditions of the rapid thermal oxidation are：Temperature 600-
1100 DEG C, pressure 0.5-760torr, gas component is selected from least one of oxygen, nitric oxide, gas flow 500sccm-
50slm, processing time 5-300s.
7. according to the method described in claim 1, it is characterised in that implement before first Rapid Thermal Nitrided, be additionally included in
The step of isolation structure and well region are sequentially formed in the Semiconductor substrate.
8. according to the method described in claim 1, it is characterised in that implement after second Rapid Thermal Nitrided, be additionally included in
The step of floating boom and control gate being formed in the Semiconductor substrate.
9. method according to claim 8, it is characterised in that the step of forming the floating boom and the control gate includes：
First grid material layer, the first oxide skin(coating), nitride layer, the second oxide skin(coating) are sequentially depositing on first silicon nitride layer
With second grid material layer；The second grid material layer, second oxide skin(coating), the nitride layer, institute are etched successively
State the first oxide skin(coating), the first grid material layer, first silicon nitride layer, the silicon oxide layer and second nitridation
Silicon layer.
10. method according to claim 9, it is characterised in that the floating boom is by the first grid that is laminated from top to bottom
Pole material layer, first silicon nitride layer, the silicon oxide layer and second silicon nitride layer are constituted, and the control gate is by from upper
And the second grid material layer, second oxide skin(coating), the nitride layer and first oxide skin(coating) of lower stacking
Constitute.
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| CN101290886A (en) * | 2007-04-20 | 2008-10-22 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of grid dielectric layer and grid |
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