CN104465794B - Semiconductor device - Google Patents

Abstract

The present invention provides a semiconductor device which has a structure for improving withstand voltage in an outer peripheral region and which can suppress damage to a semiconductor element formed in the element region. The semiconductor device has: a first semiconductor region of the first conductivity type, which is arranged in the element region and an outer peripheral region; an upper surface of a semiconductor region having an inner diameter of 0.5 μm to 20 μm; a third semiconductor region of a second conductivity type arranged on an upper surface of the first semiconductor region in an outer peripheral region surrounding the element region; and a first electrode, which is in contact with The second semiconductor region and the upper surfaces of the third semiconductor region are arranged on the first semiconductor region in contact with upper surfaces, and form a Schottky junction with the second semiconductor region.

Description

Semiconductor device

technical field

The present invention relates to a semiconductor device in which a structure for improving withstand voltage is formed in an outer peripheral region.

Background technique

In order to improve the withstand voltage of a semiconductor device including a semiconductor element such as a Schottky barrier diode (SBD), various techniques are employed. For example, electric field relaxation is realized by distributing p ⁺ regions or arranging p ⁺ regions in stripes in the outer peripheral region surrounding the element region where SBDs are arranged (for example, refer to Patent Document 1).

[Patent Document 1] Japanese Patent Laid-Open No. 2000-312011

However, although forming a structure for increasing the withstand voltage in the peripheral region can increase the withstand voltage, on the other hand, there is a problem that avalanche current concentrates in the peripheral region after breakdown. Concentration of the avalanche current in the peripheral region causes the temperature of the semiconductor device to rise locally, thereby damaging the semiconductor element.

Contents of the invention

In view of the above problems, an object of the present invention is to provide a semiconductor device that has a structure for increasing withstand voltage in the peripheral region and can suppress damage to semiconductor elements formed in the element region.

According to one aspect of the present invention, there is provided a semiconductor device having an element region in which a semiconductor element is arranged and an outer peripheral region arranged around the element region, wherein the semiconductor device has: (a) a first semiconductor of a first conductivity type; region, which is configured in the element region and the peripheral region; (b) a plurality of the second semiconductor regions of the second conductivity type, which are arranged in dots on the upper surface of the first semiconductor region of the element region at intervals, and the inner diameter is 0.5 μm to 20 μm; (c) a third semiconductor region of the second conductivity type, which is arranged on the upper surface of the first semiconductor region in the peripheral region around the element region; and (d) a first electrode, which is connected to the second semiconductor region The region is arranged on the first semiconductor region in contact with the upper surface of the third semiconductor region, and forms a Schottky junction with the second semiconductor region.

According to the present invention, it is possible to provide a semiconductor device that has a structure for increasing withstand voltage in the peripheral region and that can suppress damage to a semiconductor element formed in the element region.

Description of drawings

FIG. 1 is a schematic cross-sectional view showing the structure of a semiconductor device according to an embodiment of the present invention.

2 is a graph showing the relationship between the curvature of the second semiconductor region and the breakdown voltage of the semiconductor device according to the embodiment of the present invention.

3 is a graph showing the relationship between the inner diameter of the second semiconductor region and the breakdown voltage of the semiconductor device according to the embodiment of the present invention.

4 is a schematic plan view of an arrangement example of a second semiconductor region of the semiconductor device according to the embodiment of the present invention.

FIG. 5 is a graph showing the relationship between withstand voltage and current related to the semiconductor device according to the embodiment of the present invention and a comparative example.

6 is a schematic cross-sectional view showing an example of a breakdown position of a semiconductor device.

7 is a schematic cross-sectional view showing a structural example of a second semiconductor region of the semiconductor device according to the embodiment of the present invention.

Label description

1: semiconductor device; 10: first semiconductor region; 20: second semiconductor region; 30: third semiconductor region; 40: first electrode; 50: insulating film; 60: substrate; 70: second electrode; 101: element area; 102: peripheral area.

Detailed ways

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the description of the drawings below, the same or similar reference numerals are attached to the same or similar parts. However, it should be noted that the drawings are schematic drawings, and thickness ratios of respective layers and the like are different from actual ones. Therefore, the specific thickness and size should be judged with reference to the following description. In addition, it is needless to say that there are parts where mutual dimensional relationships and ratios are different among the drawings.

In addition, the embodiments shown below are examples of devices and methods for realizing the technical idea of the present invention, and the embodiments of the present invention do not limit the materials, shapes, structures, arrangements, etc. the following. Various modifications can be added to the embodiments of the present invention within the scope of the claims.

As shown in FIG. 1 , a semiconductor device 1 according to an embodiment of the present invention has an element region 101 in which a semiconductor element is arranged, and an outer peripheral region 102 arranged around the element region 101 . The semiconductor device 1 has: a first semiconductor region 10 of a first conductivity type arranged in an element region 101 and an outer peripheral region 102; a plurality of second semiconductor regions 20 of a second conductivity type arranged in an element region at intervals from each other. The upper surface of the first semiconductor region 10 at 101; the third semiconductor region 30 of the second conductivity type, which surrounds the element region 101 and is arranged on the upper surface of the first semiconductor region 10 in the peripheral region 102; and the first electrode 40, It is arranged on the first semiconductor region 10 in contact with the upper surfaces of the second semiconductor region 20 and the third semiconductor region 30 . As will be described later, the second semiconductor region 20 is arranged in a dot shape when viewed from above. The second semiconductor region 20 is a tubular semiconductor region buried in such a manner that an end surface is exposed on the upper portion of the first semiconductor region 10 , and has an inner diameter r of 0.5 μm to 20 μm.

In addition, the first conductivity type and the second conductivity type are opposite to each other. That is, if the first conductivity type is n-type, the second conductivity type is p-type, and if the first conductivity type is p-type, the second conductivity type is n-type. Hereinafter, a case where the first conductivity type is n-type and the second conductivity type is p-type will be described.

The first electrode 40 is made of a metal film or the like forming a Schottky junction with the second semiconductor region 20 . For the first electrode 40, for example, an aluminum film or the like can be used. In addition, the first electrode 40 and the third semiconductor region 30 are in low-resistance contact. In addition, an insulating film 50 is disposed on the upper surface of the first semiconductor region 10 at the outermost edge of the outer peripheral region 102 , and an end portion of the first electrode 40 is disposed on the insulating film 50 . The insulating film 50 is, for example, a silicon dioxide film or the like.

On the back surface of the first semiconductor region 10 opposite to the upper surface on which the first electrode 40 is arranged, the second electrode 70 is arranged via the n-type substrate 60 . That is, Schottky barrier diodes (SBDs) each having the first electrode 40 and the second electrode 70 as an anode electrode and a cathode electrode are formed in the element region 101 as a semiconductor element. The second electrode 70 uses a metal film or the like that is in low-resistance contact with the substrate 60 , for example, a titanium (Ti)/nickel (Ni) film or the like can be used.

The third semiconductor region 30 functions as a guard ring or an FLR arranged to increase a withstand voltage. For example, as shown in FIG. 1 , in order for the third semiconductor region 30 to function as a guard ring, the third semiconductor region 30 is arranged in a ring shape around the element region 101 .

In the semiconductor device 1 , the inner diameter of the second semiconductor region 20 constituting the SBD is set to 0.5 μm to 20 μm. This is to make the breakdown voltage of the SBD lower than the breakdown voltage of structures for increasing withstand voltage such as guard rings formed in the outer peripheral region 102 (hereinafter referred to as “voltage-resistant structures”). That is, by reducing the inner diameter of the dot-shaped second semiconductor region 20 , the curvature of the second semiconductor region 20 is reduced, so that the breakdown voltage is lower than that of the withstand voltage structure in the outer peripheral region 102 . In addition, assuming that the inner diameter of the second semiconductor region 20 is r, the thickness is X, and the curvature is represented by r/X.

FIG. 2 shows the relationship between the curvature of the second semiconductor region 20 and the breakdown voltage. Point A in FIG. 2 is the withstand voltage determined only by the withstand voltage structure when breakdown in the second semiconductor region 20 is not considered. The characteristic B is a breakdown voltage determined by the breakdown of the second semiconductor region 20 . In the semiconductor device 1 , the size of the second semiconductor region 20 is defined so that breakdown occurs according to the curvature of the second semiconductor region 20 represented by the characteristic B. FIG.

The inventors of the present invention obtained the following new insight: when the inner diameter r of the second semiconductor region 20 is 0.5 μm to 20 μm as shown in FIG. The breakdown of the second semiconductor region 20 definitely determines the withstand voltage of the semiconductor device 1 . When out of this range, the pressure structure may be broken down.

In addition, the withstand voltage of the semiconductor device 1 is reliably set lower than the withstand voltage of the withstand voltage structure depending on the outer peripheral region 102, and a plurality of second semiconductor regions 20 are arranged in order to reduce the operating resistance, thereby improving the performance of the SBD. Avalanche tolerance.

As shown in FIG. 4 , the second semiconductor regions 20 are arranged in dots when viewed from a planar view. FIG. 4 is a plan view seen through the first electrode 40 . In the example shown in FIG. 4 , the p-type second semiconductor region 20 and its surrounding n-type peripheral region are configured as one hexagonal unit cell 200 . That is, a plurality of unit cells 200 are adjacently arranged in the device region 101 . The peripheral region is the remaining region of the first semiconductor region 10 other than the region where the second semiconductor region 20 is formed. In addition, FIG. 1 is a sectional view along the II direction of FIG. 4 .

FIG. 4 shows an example in which the plan view shape of the second semiconductor region 20 viewed from the plan view direction is circular. However, the planar shape of the second semiconductor region 20 may be a polygon such as a quadrangle or a hexagon. That is, the second semiconductor region 20 may be formed in a columnar shape with a circular or polygonal cross section.

In addition, FIG. 4 shows an example in which the second semiconductor region 20 is arranged so as to be located at the apex of an equilateral triangle as viewed from a plan view. However, the second semiconductor regions 20 may be regularly arranged in other shapes such as a positive direction. The distance R between the second semiconductor regions 20 in plan view is constant.

The second semiconductor regions 20 are arranged such that the mutual interval R of the second semiconductor regions 20 satisfies the following formula (1):

{(r/2+0.8×X)/(R/2)} ² <0.5 · · · (1).

The inventors of the present invention found through repeated experiments and studies that by setting the interval R to a value equal to or greater than the value satisfying the relationship of the formula (1), breakdown can be achieved in accordance with the curvature of the second semiconductor region 20 .

In addition, in order to secure a withstand voltage at the boundary between the second semiconductor region 20 and the voltage-resistant structure, it is preferable that the outer edge shape of the device region 101 side of the voltage-resistant structure viewed from the planar direction is the same as that of the outermost edge of the device region 101 disposed on the side of the voltage-resistant structure. The shape of the outer edge of the second semiconductor region 20 matches the outer edge. That is, the third semiconductor region is arranged such that the distance between the outer edge of the third semiconductor region 30 on the element region 101 side and the outer edge of the second semiconductor region 20 disposed on the outermost edge of the element region 101 is constant. 30. For example, in the example shown in FIG. 4 , the outer edge of the third semiconductor region 30 on the element region 101 side extends in a wave shape matching the outer edge of the element region 101 where the hexagonal unit cells 200 are continuously formed.

The first semiconductor region 10 is formed on the n-type base body 60 by epitaxial growth or the like, for example. The impurity concentration of the first semiconductor region 10 is lower than that of the base body 60 , for example, 1E17/cm ³ or less. Furthermore, the thickness of the first semiconductor region 10 is 5 μm to 15 μm. According to investigations by the present inventors, by setting the impurity concentration and thickness of the first semiconductor region 10 to the above-mentioned values, the following good results were obtained: the breakdown voltage of the SBD can be lower than that of the withstand voltage structure, and it is not caused by the withstand voltage structure. The breakdown of the semiconductor device 1 is determined by the breakdown of the second semiconductor region 20, but the withstand voltage of the semiconductor device 1 is determined exactly by the breakdown of the second semiconductor region 20.

The second semiconductor region 20 and the third semiconductor region 30 are formed by, for example, selective ion implantation and diffusion into the first semiconductor region 10 using a mask formed by photolithography. The impurity concentration of the second semiconductor region 20 is 5E17/cm ³ to 1E19/cm ³ . The thickness of the second semiconductor region is 0.5 μm to 1 μm.

Furthermore, it is preferable that the thickness X of the second semiconductor region 20 is 20% to 60% of the thickness D of the first semiconductor region 10 . It is found through experiments that when the range is out of range, the pressure-resistant structure may be broken down.

In addition, by simultaneously forming the second semiconductor region 20 and the third semiconductor region 30 , the manufacturing process of the semiconductor device 1 can be shortened. In this case, the second semiconductor region 20 and the third semiconductor region 30 have the same thickness.

FIG. 5 shows the relationship between the withstand voltage and the current with respect to the semiconductor device 1 and the comparative example. The comparative example is a semiconductor device whose withstand voltage is not determined by the breakdown based on the curvature of the second semiconductor region 20 but by the breakdown of the withstand voltage structure. In FIG. 5 , the characteristic S1 is the characteristic of the semiconductor device 1 , and the characteristic S2 is the characteristic of the comparative example.

P1 to P3 shown in FIG. 5 indicate characteristic change points when breakdown occurs at positions P1 to P3 of the semiconductor device shown in FIG. 6 . That is, in the comparative example, a new finding was obtained by simulation that a current starts to flow due to breakdown at the position P2 of the outer edge of the third semiconductor region 30 functioning as a guard ring. When the current increases, the flow pattern of the current is deviated due to the breakdown at the position P1 which is the inner edge of the third semiconductor region 30 and the breakdown at the position P3 in the center of the third semiconductor region 30 . As a result, a disordered waveform like the characteristic S2 is obtained. It is easily expected that this deviation occurs not only in the lateral direction of the paper but also in the depth direction. In the comparative example of only the withstand voltage structure, heat generation due to current concentration was generated, thereby damaging the semiconductor element.

On the other hand, in the semiconductor device 1 having the element region 101 , a breakdown current flows in the element region 101 and a plurality of second semiconductor regions 20 are arranged. Therefore, after the current starts to flow due to the breakdown at the position P1, as shown as the characteristic S1, the disturbance of the waveform does not occur. Therefore, even when the same magnitude of current flows, although the semiconductor device of the comparative example is damaged, the semiconductor device 1 is not damaged. That is, the avalanche withstand capacity of the semiconductor device 1 is greater than that of the comparative example. In this way, in the semiconductor device 1, since current concentration does not occur, damage to the semiconductor element is suppressed.

As described above, according to the semiconductor device 1 according to the embodiment of the present invention, the withstand voltage of the semiconductor device 1 is not determined by the breakdown of the withstand voltage structure such as the guard ring arranged in the outer peripheral region 102, but by the breakdown voltage of the device arranged in the element. The breakdown of the second semiconductor region 20 in the region 101 determines the withstand voltage of the semiconductor device 1 . Therefore, current concentration or the like in the third semiconductor region 30 does not occur, and the avalanche resistance is improved. As a result, damage to the semiconductor element arranged in the element region 101 can be suppressed. That is, it is possible to provide the semiconductor device 1 that has a structure for increasing the withstand voltage in the outer peripheral region and that can suppress damage to the semiconductor element.

＜Modifications＞

FIG. 1 shows an example in which the position of the upper surface of the second semiconductor region 20 coincides with the position of the upper surface of the first semiconductor region 10 . However, as shown in FIG. 7 , the position of the upper surface of the second semiconductor region 20 may be lower than the position of the upper surface of the first semiconductor region 10 .

For example, a part of the upper surface of the first semiconductor region 10 is selectively etched and removed in advance for the position where the second semiconductor region 20 is arranged. Then, p-type impurities are selectively implanted into the concave portion of the upper surface of the first semiconductor region 10 formed by etching, thereby forming the second semiconductor region 20 into the shape shown in FIG. 7 .

By making the upper surface position of the second semiconductor region 20 lower than the upper surface position of the first semiconductor region 10 , p-type impurities can be implanted deeply into the semiconductor device 1 . For example, the distance t from the upper surface position of the first semiconductor region 10 to the upper surface position of the second semiconductor region 20 is set to about 0.05 μm to 1 μm. The breakdown depends on the distance W from the bottom of the second semiconductor region 20 to the first semiconductor region 10 of the base 60 in addition to the curvature of the second semiconductor region 20 . That is, by deeply implanting p-type impurities and narrowing the distance W, the second semiconductor region 20 can be broken down and a breakdown current can flow in the element region 101 .

(Other implementations)

As mentioned above, although this invention was described by embodiment, it should be understood that the description and drawing which make a part of this indication do not limit this invention. Various alternative embodiments, examples, and operating techniques can be known to those skilled in the art from this disclosure.

For example, the above description shows an example in which the guard ring is arranged in the outer peripheral region 102 , but a field limiting ring (Field Limiting Ring: FLR) may be arranged in the outer peripheral region 102 as a withstand voltage structure.

As such, the present invention naturally includes various embodiments and the like not described here. Therefore, the technical scope of the present invention should be determined only by invention-specific matters related to the claims reasonably obtained from the above description.

Claims (9)

1. a kind of semiconductor device has the element area configured with semiconductor element and configures the week in the element area The outer region enclosed, the semiconductor device are characterized in that having：

1st semiconductor regions of the 1st conductivity type are configured in the element area and the outer region；

2nd semiconductor regions of multiple 2nd conductivity types, they are in dotted configuration spaced apart from each other in the element area The internal diameter of the upper surface of 1st semiconductor regions, the 2nd semiconductor regions is 0.5 μm~20 μm；

3rd semiconductor regions of the 2nd conductivity type are configured round the element area the described 1st of the outer region The upper surface of semiconductor regions；And

1st electrode is contiguously configured with the upper surface of the 2nd semiconductor regions and the 3rd semiconductor regions described On 1st semiconductor regions, schottky junction is formed with the 2nd semiconductor regions,

If the internal diameter of the 2nd semiconductor regions is r, the thickness of the 2nd semiconductor regions is X, the 2nd semiconductor regions Spaced R meet the relationship of following formula：

{(r/2+0.8×X)/(R/2)}²＜ 0.5.

2. semiconductor device according to claim 1, which is characterized in that

The impurity concentration of 2nd semiconductor regions is 5E17/cm³~1E19/cm³。

3. semiconductor device according to claim 2, which is characterized in that

The thickness of 2nd semiconductor regions is the 20%~60% of the thickness of the 1st semiconductor regions.

4. according to the semiconductor device described in any one in claims 1 to 3, which is characterized in that

The outer rim shape that the slave overlook direction of the element area side of 3rd semiconductor regions is observed is with configuration described The outer rim shape of the 2nd semiconductor regions of the outer most edge of element area matches.

5. semiconductor device according to claim 4, which is characterized in that

The shape that the slave overlook direction of 2nd semiconductor regions is observed is any one in circle, quadrangle, hexagon It is a.

6. semiconductor device according to claim 4, which is characterized in that

Multiple 2nd semiconductor regions are configured to be located at the top of square or equilateral triangle from overlook direction Point.

7. according to the semiconductor device described in any one in claims 1 to 3, which is characterized in that

The upper surface location of 2nd semiconductor regions is lower 0.05 μm~1 μ than the upper surface location of the 1st semiconductor regions m。

8. according to the semiconductor device described in any one in claims 1 to 3, which is characterized in that

The thickness of 2nd semiconductor regions is 0.5 μm~1 μm.

9. according to the semiconductor device described in any one in claims 1 to 3, which is characterized in that

The semiconductor device also have the 2nd electrode, the 2nd electrode configuration the 1st semiconductor regions with configured with On the opposite back side in the upper surface of 1st electrode, the semiconductor element is respectively by the 1st electrode and the 2nd electricity Schottky-barrier diode of the pole as positive electrode and negative electrode.