JP2003158259A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) [Problem] To provide a semiconductor device capable of effectively lowering a forward ON voltage without impairing reverse characteristics such as a withstand voltage and a leakage current, and a method for manufacturing the same. SOLUTION: A silicon film is formed on an upper surface of a silicon carbide substrate, and a refractory metal film is formed thereon with a stoichiometric composition ratio of 1: 2.
(= High melting point metal: silicon). And 600 to 11 in a vacuum or an inert gas atmosphere.
By performing a heat treatment at a temperature of 00 ° C., a silicide film is generated only from a silicide reaction between the silicon film and the high melting point metal film. In forming the silicide film, silicon atoms in the silicon carbide substrate are not consumed, and a Schottky contact with a sharp change in composition is formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor power device using SiC and a manufacturing method thereof.

[0002]

2. Description of the Related Art One of semiconductor power devices is a junction barrier Schottky diode (hereinafter, referred to as
"JBS diode"). The JBS diode has a structure in which a plurality of p ⁺ regions are buried under the Schottky electrode in a normal n-type Schottky diode. The JBS diode is characterized in that, in the reverse direction characteristic, the depletion layer extends from each p ⁺ region and pinches off, thereby relaxing the electric field applied to the Schottky interface and suppressing the reverse direction leak current. On the other hand, in the forward characteristic, since a plurality of P ⁺ regions are buried under the Schottky electrode, the region through which carriers pass is effectively reduced, and as a result, the forward on-voltage increases. There is a problem.

Therefore, in order to reduce the on-state voltage in the forward direction, it has been considered to use a metal having a low barrier height as a Schottky electrode material. Generally, in a Schottky barrier diode including a JBS diode, the forward ON-state voltage largely depends on the height of the Schottky barrier height. That is, when the barrier height is low, the majority electrons are easily emitted from the semiconductor side to the metal side by thermoelectrons, so that the forward current is significantly increased. In other words, in order to obtain the same forward current, the lower the barrier height, the smaller the on-voltage can be. Therefore, if a metal having a low barrier height is used as the Schottky electrode material, the forward ON voltage can be effectively reduced.

Here, JB using SiC (silicon carbide), which is expected as a semiconductor for next-generation power devices, is used.
Consider an S diode. SiC has a bandgap three times that of Si (silicon) and a breakdown electric field strength of about 10
It has excellent physical properties such as double the thermal conductivity and approximately three times the thermal conductivity, and by utilizing this characteristic, it is possible to realize a power device that can operate at high temperature with ultra-low loss. When a Schottky connection is formed by using SiC, it is generally known that the barrier height has almost linear linearity with respect to the work function of metal. Therefore, if a metal having a low work function is used as the material for the Schottky electrode, the Schottky barrier bite can be reduced, and as a result, the forward ON voltage can be lowered.

In the conventional JBS diode using SiC, a Schottky electrode film of nickel (Ni) or the like is directly formed on a SiC substrate, and Si and Ni are subjected to a silicide reaction to form a nickel silicide film (Ni ₂ Si). ) Was formed (see, for example, Patent Document 1).

[0006]

[Patent Document 1] Japanese Patent Laid-Open No. 2000-236099

[0007]

However, the actual JBS
In the diode, even if any metal having a small work function such as Ti (titanium) is simply used as the Schottky electrode material, the SiC surface before contact formation is
The surface defects increase due to exposure to repeated processes such as cleaning and oxidation steps, and the flatness of the SiC surface also remarkably decreases. As a result, it was extremely difficult to make the Schottky barrier height substantially 0.7 eV or less.

Further, in the JBS diode described in Patent Document 1, the composition change at the Schottky connection interface between Ni ₂ Si and SiC becomes slow. That is, Ni ₂
A Ni carbide layer is formed at the interface between Si and SiC to increase the density of interface states. With the increase of the interface level, the Fermi level of SiC near the interface is pinned deep from the lower end of the conduction band. As a result, the barrier height rises and the forward ON voltage of the JBS diode increases.

The present invention has been made to solve the above-mentioned problems of the prior art.
It is an object of the present invention to provide a semiconductor device that can effectively reduce the on-voltage in the forward direction without impairing the reverse characteristics such as leakage current, and a manufacturing method thereof.

[0010]

In order to achieve the above object, a first feature of the present invention is to provide a silicon carbide substrate having a first conductivity type and high resistance, and a second conductivity type formed on the silicon carbide substrate. Region, a second conductivity type junction termination region formed outside the second conductivity type region on the silicon carbide substrate, and a first conductivity type low termination region formed outside the junction termination region on the silicon carbide substrate. A depletion layer limiting region of resistance, an anode electrode connected to the second conductivity type region and the junction terminating region and Schottky connected to the upper surface of the silicon carbide substrate exposed inside the junction terminating region, and a depletion layer limiting region That is, the semiconductor device has a depletion layer limiting electrode ohmic-connected to and a cathode electrode ohmic-connected to the lower surface of the silicon carbide substrate. The anode electrode has a refractory metal silicide film disposed at least at the Schottky connection interface.

A second feature of the present invention is (1) a step of preparing a silicon carbide substrate having a first conductivity type and high resistance, and (2) a second conductivity type impurity being selectively diffused on the silicon carbide substrate. A step of forming the second conductivity type region, and (3) selectively diffusing the second conductivity type impurity in the upper portion of the silicon carbide substrate,
Forming a junction termination region outside the second electrode region;
(4) a step of selectively diffusing a first conductivity type impurity at a high concentration over the silicon carbide substrate to form a depletion layer restriction region outside the junction termination region; and (5) a second conductivity type region, A step of forming a silicon film on the upper surface of the junction termination region and on the upper surface of the silicon carbide substrate exposed inside the junction termination region; and (6) on the silicon film, a refractory metal film having a stoichiometric composition ratio is formed. 1: 2 (= high melting point metal: silicon), and (7) predetermined heat treatment is performed to form a silicide film serving as an anode electrode from the silicide reaction between the silicon film and the high melting point metal film. A semiconductor device having a step of forming, a step (8) of forming a depletion layer limiting electrode that makes ohmic contact with a depletion layer limiting region, and a step of (9) forming a cathode electrode that makes ohmic connection to the lower surface of a silicon carbide substrate. By being a manufacturing method That.

According to the second feature of the present invention, the silicon film and the refractory metal film are coated on the silicon carbide substrate so that the stoichiometric composition ratio is 1: 2 (= refractory metal: silicon). By forming the silicide film by performing a predetermined heat treatment after the deposition, the silicide film is generated only by the silicide reaction between the silicon film and the refractory metal, and does not consume silicon atoms in the silicon carbide substrate. As a result, the barrier height can be kept low in the Schottky connection. Further, the contact resistance can be suppressed low in the ohmic connection.

A third feature of the present invention is that the first conductivity type high resistance silicon carbide substrate is embedded in the upper portion of the silicon carbide substrate,
A first anode electrode Schottky connected to the upper surface of the silicon carbide substrate, and a second conductivity type junction termination region formed outside the first anode electrode in the upper portion of the silicon carbide substrate,
A junction terminating electrode connected to the junction terminating region, and a second anode electrode Schottky connected to the upper surface of the silicon carbide substrate exposed inside the junction terminating region and connected to the first anode electrode and the junction terminating electrode. , A first conductivity type low resistance depletion layer limiting region formed outside the junction termination region in the upper portion of the silicon carbide substrate, a depletion layer limiting electrode ohmic-connected to the depletion layer limiting region, and a lower surface of the silicon carbide substrate. That is, the semiconductor device has a cathode electrode that is ohmic-connected. The second anode has a refractory metal silicide film arranged at least at the Schottky connection interface. Further, the barrier height of the silicon carbide substrate at the Schottky connection interface with the first anode electrode is higher than the barrier height of the silicon carbide substrate at the Schottky connection interface with the second anode electrode.

A fourth feature of the present invention is: (1) a step of preparing a silicon carbide substrate of the first conductivity type and high resistance; and (2) a diffusion of the second conductivity type impurity selectively onto the silicon carbide substrate. Then, the step of forming the junction termination region, and (3) the first conductivity type impurity is selectively diffused into the upper portion of the silicon carbide substrate at a high concentration to form the depletion layer limiting region outside the junction termination region. And (4) a step of selectively forming a silicon film on the upper surface of the silicon carbide substrate exposed inside the junction termination region,
(5) The refractory metal film has a stoichiometric composition ratio of 1: 2 (= refractory metal: silicon) on the upper surface of the silicon film, the junction termination region, and the silicon carbide substrate exposed inside the junction termination region.
And (6-1) performing a predetermined heat treatment to form a first anode electrode and a junction termination electrode by a silicide reaction between the silicon carbide substrate and the junction termination region and the refractory metal film. At the same time as forming the silicide film of
(6-2) A step of forming a second silicide film to be the second anode electrode from a silicidation reaction between the silicon film and the refractory metal film, and (7) a depletion layer limiting electrode which is ohmic-connected to the depletion layer limiting region. It is a method for manufacturing a semiconductor device, which includes a step of forming and a step (8) of forming a cathode electrode in ohmic contact with the lower surface of the silicon carbide substrate.

According to the fourth aspect of the present invention, a silicon film and a refractory metal film are coated on a silicon carbide substrate so that the stoichiometric composition ratio is 1: 2 (= refractory metal: silicon). After the deposition, a predetermined heat treatment is performed to form the second silicide film, so that the second silicide film is generated only by the silicidation reaction between the silicon film and the refractory metal, thereby removing the silicon atoms in the silicon carbide substrate. Never consume. As a result, the barrier height can be kept low in the Schottky connection. Further, the contact resistance can be suppressed low in the ohmic connection. On the other hand, the first silicide film is formed by forming a refractory metal film directly on the silicon carbide substrate and performing a silicidation reaction between silicon in the silicon carbide substrate and the refractory metal. Therefore, the composition change at the Schottky connection interface becomes slow, and the barrier height increases.

A fifth feature of the present invention is that the first conductivity type high resistance silicon carbide substrate, the first conductivity type low resistance source region formed on the silicon carbide substrate, and the silicon carbide substrate upper part. A second conductivity type gate region formed outside the source region, a second conductivity type junction termination region formed outside the gate region on the silicon carbide substrate, and a junction termination region above the silicon carbide substrate. A first-conductivity-type low-resistance depletion layer confined region formed outside, a source electrode ohmic-connected to the source region, a gate electrode ohmic-connected to the gate region, and an ohmic-connection depleted layer-restricted region. This is a semiconductor device having a depletion layer limiting electrode and a drain electrode ohmic-connected to the lower surface of the silicon carbide substrate. The source electrode and the gate electrode each include a refractory metal silicide film disposed at least at the ohmic contact interface.

A sixth feature of the present invention is (1) a step of preparing a silicon carbide substrate having a first conductivity type and high resistance, and (2) a step of selectively increasing a first conductivity type impurity in an upper portion of the silicon carbide substrate. A step of diffusing to a concentration to form a source region, and (3) a step of selectively diffusing a second conductivity type impurity in an upper portion of the silicon carbide substrate to form a gate region outside the source region,
(4) A step of selectively diffusing a second conductivity type impurity in the upper portion of the silicon carbide substrate to form a junction termination region outside the gate region, and (5) first selectively in the upper portion of the silicon carbide substrate.
A step of diffusing a conductivity type impurity in a high concentration to form a depletion layer limiting region outside the junction termination region; and (6) a step of forming a silicon film on the source region and the gate region.
(7) A step of forming a refractory metal film on the silicon film so that the stoichiometric composition ratio is 1: 2 (= refractory metal: silicon), and (8) performing a predetermined heat treatment. A step of forming a silicide film to be a source electrode and a gate electrode from a silicide reaction between a silicon film and a refractory metal film, and (9) a step of forming a depletion layer limiting electrode ohmic-connected to the depletion layer limiting region, (10) A method of manufacturing a semiconductor device, including the step of forming a drain electrode that makes ohmic contact with the lower surface of the silicon carbide substrate.

According to the sixth feature of the present invention, the composition changes sharply at the ohmic contact interface between the source region and the source electrode and the ohmic contact interface between the gate region and the gate electrode, and this interface structure is reflected. The barrier height can be kept low.

A seventh characteristic of the present invention is that the first conductivity type high resistance silicon carbide substrate, the first conductivity type low resistance source region formed on the silicon carbide substrate, and the silicon carbide substrate upper part. In the silicon carbide substrate at the outer side of the source region, the gate region of the second conductivity type formed at the bottom of the recess, and the second conductive region at the upper part of the silicon carbide substrate outside the gate region. Type junction termination region, a first conductivity type low resistance depletion layer limiting region formed outside the junction termination region in the upper portion of the silicon carbide substrate, a source electrode ohmic-connected to the source region, and an ohmic contact to the gate region. A semiconductor device having a connected gate electrode, a depletion layer limiting electrode ohmic-connected to the depletion layer limiting region, and a drain electrode ohmic-connected to the lower surface of the silicon carbide substrate. That. The source electrode and the gate electrode are
Each has a refractory metal silicide film disposed at least at the ohmic contact interface. When the refractory metal is M, the silicide film is a disilicide film having an MSi ₂ structure.

An eighth feature of the present invention is: (1) a step of preparing a silicon carbide substrate having a first conductivity type and high resistance; and (2) a step of selectively adding a first conductivity type impurity to the upper portion of the silicon carbide substrate. A step of diffusing to a concentration to form a source region, (3) a step of selectively removing the upper portion of the silicon carbide substrate to form a recess outside the source region, and (4) a selection from the bottom of the recess. A step of selectively diffusing the second conductivity type impurity to form a gate region, and (5) selectively diffusing the second conductivity type impurity above the silicon carbide substrate to form a junction termination region outside the gate region. And (6) a step of (6) selectively diffusing the first-conductivity-type impurity into a high concentration on the silicon carbide substrate to form a depletion layer limiting region outside the junction termination region, and (7)
A step of selectively forming a silicon film on the exposed source region and gate region, and (8) forming a refractory metal film on the silicon film, with a stoichiometric composition ratio of 1: 2 (= high (Melting point metal: silicon), and (9)
A step of performing a predetermined heat treatment to generate a silicide film to be a source electrode and a gate electrode from a silicidation reaction between a silicon film and a refractory metal film; and (10) a depletion layer limiting electrode ohmic-connected to a depletion layer limiting region. And a step (11) of forming a drain electrode for ohmic connection on the lower surface of the silicon carbide substrate.

According to the eighth feature, silicon atoms in the silicon carbide substrate are not consumed in the silicidation reaction between the silicon film and the refractory metal film. Therefore, the composition change at the ohmic contact interface between the source region and the gate region becomes sharp, and the barrier height can be suppressed to a low level by reflecting this interface structure. Further, a silicide film can be formed in a self-aligned manner by selectively forming a silicon film on the exposed source region and gate region and then causing a silicide reaction with a refractory metal.

[0022]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. In the description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and width of layers, the ratio of the thickness of each layer, and the like are different from actual ones. Further, it is needless to say that the drawings include parts in which dimensional relationships and ratios are different from each other.

(First Embodiment) <Structure and Operation of JBS Diode> The semiconductor device according to the first embodiment is a typical first-conductivity-type Schottky diode in which a Schottky electrode (anode electrode) is used.
Is a JBS diode in which a plurality of second conductivity type impurity regions are formed in the first conductivity type semiconductor region below.

FIG. 1 is a sectional view showing the structure of a JBS diode according to the first embodiment of the present invention. As shown in FIG. 1, the JBS diode includes a first conductivity type (n type) high resistance silicon carbide substrate (SiC substrate) 14 and a second conductivity type region (p type low resistance) formed on the SiC substrate 14. Resistance region 3), a second conductivity type junction termination region (guard ring) 8 formed outside the p-type low resistance region 3 on the SiC substrate 14, and outside the guard ring 8 on the SiC substrate 14. The first conductivity type low resistance depletion layer limiting region 4, the p type low resistance region 3 and the guard ring 8
Connected to the inside and exposed inside the guard ring 8
It has at least an anode electrode 7a Schottky connected to the upper surface of the C substrate 14, a depletion layer limiting electrode 7b ohmic connected to the depletion layer limiting region 4, and a cathode electrode 5 ohmic connected to the lower surface of the SiC substrate 14. . In all the embodiments of the present invention, the case where the first conductivity type / second conductivity type is n-type / p-type will be described.

The SiC substrate 14 is a low resistance substrate 1 made of SiC to which an n-type impurity such as nitrogen (N) or phosphorus (P) is added at a high concentration, and a low resistance substrate disposed on the low resistance substrate 1. The n-type high resistance layer 2 has a lower n-type impurity concentration than the substrate 1. The p-type low resistance region 3, the guard ring 8 and the depletion layer restriction region 4 are respectively arranged on the n-type high resistance layer 2 of the SiC substrate 14 and exposed on the upper surface of the SiC substrate 14. The cathode electrode 5 is ohmic-connected to the lower surface of the SiC substrate 14 via the low resistance substrate 1. If there is another means for ohmic-connecting the cathode electrode 5 to the n-type high resistance layer 2, the low resistance substrate 1 becomes unnecessary, and the SiC substrate 14 may be composed of only the n type high resistance layer 2.

One or more p-type low resistance regions 3 are arranged at intervals of about 2 μm. p-type low resistance region 3
The width of itself is about 2 μm. In addition, the p-type low resistance region 3
Is a region in which a p-type impurity such as boron (B) is added at a high concentration, and is a feature of the JBS diode.

The guard ring 8 is a portion that forms a junction termination structure for increasing the breakdown voltage of the device. The guard ring 8 is arranged outside the p-type low resistance region 3 at a distance of about 2 μm from the p-type low resistance region 3, and like the p-type low resistance region 3, a p-type impurity is added at a high concentration. Area.

The depletion layer limiting region 4 is a region used to limit the depletion layer extending laterally from the Schottky connection interface described later. The depletion layer restriction region 4 is a region which is arranged outside the guard ring 8 at a predetermined distance from the guard ring 8 and in which an n-type impurity such as N or P is added at a high concentration.

The anode electrode 7a is made of a refractory metal silicide film. In the first embodiment, when Ni (nickel) is used as the refractory metal, and when the silicide film is M, the disilicide film formed with the MSi ₂ structure as the main constituent element is used. A case will be described. Further, the anode electrode 7 a is ohmic-connected to the p-type low resistance region 3 and the guard ring 8, but is Schottky connected to the high resistance layer 2 exposed inside the guard ring 8. The Schottky function of the JBS diode is realized by the Schottky connection between the high resistance layer 2 and the anode electrode 7a. Here, in the “high resistance layer 2 exposed inside the guard ring 8”, a portion exposed between the p-type low resistance region 3 and the guard ring 8
A portion exposed between the p-type low resistance regions 3 is included. The anode electrode 7a may be Schottky connected to the p-type low resistance region 3 and the guard ring 8.

The depletion layer limiting electrode 7b is made of a refractory metal silicide film and has the same film structure as the anode electrode 7a. That is, the depletion layer limiting electrode 7b is a disilicide film having a NiSi ₂ structure. Depletion layer limiting electrode 7
By ohmic-connecting b to the depletion layer limiting region 4, the potential in the depletion layer limiting region 4 is kept more uniform, and the depletion layer limiting function of the depletion layer limiting region 4 is further improved. Between the anode electrode 7a and the depletion layer limiting electrode 7b,
An insulating film (SiO ₂ film) 6 is formed.

FIG. 2 is a top view showing the planar shape of the JBS diode shown in FIG. In FIG. 2, SiC
In order to show the planar shape of each semiconductor region (3, 4, 8) on the substrate 14, the electrodes (7a, 7b) and the insulating film 6 arranged on the SiC substrate 14 are not shown. Also,
The cross-sectional view shown in FIG. 1 is a cross-sectional view taken along the line AA ′ shown in FIG. As shown in FIG. 2, the SiC substrate 14
Each of the semiconductor regions (3, 4, 8) arranged on the upper portion has a concentric rectangular shape. The first p-type low resistance region 3 is arranged in the central portion, and the second ring-shaped p-type low resistance region 3 is arranged so as to surround the first p-type low resistance region 3. A ring-shaped guard ring 8 is arranged so as to surround the ring-shaped p-type low resistance region 3, and a ring-shaped depletion layer limiting region 4 is further arranged outside thereof. Although not shown, the high resistance layer 2 is exposed between the semiconductor regions (3, 4, 8). Here, each semiconductor region (3,
4 and 8) show the case of a rectangular shape, but the shape is not limited to this, and other shapes such as a circular shape, an elliptical shape, and a rhombic shape may be used. For example, as shown in FIG. 11, each semiconductor region (3, 4, 8) may have a striped planar shape.

The operation of the JBS diode shown in FIGS. 1 and 2 will be described. First, the operation when a forward voltage is applied between the cathode electrode 5 and the anode electrode 7a, that is, when a negative voltage with respect to the anode electrode 7a is applied to the cathode electrode 5 will be described. The forward voltage is applied to the Schottky interface between the n-type high resistance layer 2 and the anode electrode 7a, and the built-in potential of the n-type high resistance layer 2 is relaxed. As a result, majority carriers (electrons) in the n-type high resistance layer 2 get over the potential barrier and flow into the anode electrode 7a, and a forward current flows through the JBS diode. At this time, the p-type low resistance region 3 and n
A forward voltage is also applied to the pn junction between the high resistance layers 2 of the mold,
The current flowing through the pn junction also contributes to the forward current of the JBS diode.

On the other hand, the cathode electrode 5 and the anode electrode 7a
When a reverse voltage is applied between the p-type low resistance region 3 and the n-type low resistance region 3
A reverse voltage is also applied to the pn junction between the mold high resistance layers 2. As a result, the depletion layer mainly extends into the n-type high resistance layer 2 having a relatively low impurity concentration, and the n-type high resistance layer 2 sandwiched between the p-type low resistance region 3 and the guard ring 8 is pinched off. By forming the pinch-off, the electric field applied to the Schottky interface is relaxed, and the reverse leak current at the Schottky interface can be reduced.

<Method for Manufacturing JBS Diode> Next, a method for manufacturing the JBS diode shown in FIGS. 1 and 2 will be described with reference to FIG.
And FIG. 4 will be described. 3 and 4 are process cross-sectional views showing main manufacturing steps in manufacturing a JBS diode.

(A) First, as shown in FIG. 3A, an n-type high resistance SiC substrate 14 is prepared. Specifically, the n-type impurity concentration is 1 × 10 ¹⁹ cm ⁻³ and the thickness is 30.
An n-type high resistance layer 2 having an impurity concentration of 5 × 10 ¹⁵ cm ⁻³ and a thickness of 10 μm is formed on the low resistance substrate 1 made of 0 μm SiC by an epitaxial method. Where n
Nitrogen (N) is used as the type impurity, but other n-type impurities such as phosphorus (P) may be used. Alternatively, these may be mixed and used.

(B) Next, as shown in FIG.
A p-type impurity is selectively diffused on the upper part of the high-resistance layer 2 to form the p-type low resistance region 3, and at the same time, a guard ring 8 is formed outside the p-type low resistance region 3.

Specifically, first, a mask 10 made of an oxide film or a metal is formed on the upper surface of the n-type high resistance layer 2. Then, by using the ion implantation method, the p of boron (B) etc.
Type impurity ions are selectively implanted into the upper portion of the n-type high resistance layer 2 through the mask 10. Finally, heat treatment at about 1600 ° C. is applied to activate the implanted ions, whereby the p-type low resistance region 3 and the guard ring 8 are formed. here,
B ions are implanted in a region of a depth of about 0.5 μm from the surface of the n-type high resistance layer 2 by multi-stage implantation with an acceleration energy of 10 to 250 keV and a total dose of 5 × 10 ¹⁴ cm ⁻² . As a result, p with an impurity concentration of 1 × 10 ¹⁹ cm ⁻³
The mold low resistance region 3 and the guard ring 8 are formed. The conditions of the active heat treatment are adjusted so that the width of the p-type low resistance region 3 becomes about 2 μm and the width of the Schottky junction near the surface sandwiched by the p-type low resistance region 3 becomes about 2 μm.

However, it is not always necessary to form the p-type low resistance region 3 and the guard ring 8 at the same time, and both (3,
8) may be formed in different steps. That is,
A mask having a window on the p-type low resistance region 3 and a mask having a window on the guard ring may be prepared and ion implantation may be performed, and different activation heat treatments may be performed. n
The p-type low resistance region 3 and the guard ring 8 can have different depths from the surface of the high resistance layer 2 of the type, impurity concentrations, activation heat treatment conditions, and the like.

(C) Next, as shown in FIG.
An n-type impurity is selectively diffused into the upper portion of the high-resistance layer 2 at a high concentration to form a depletion layer limiting region 4 outside the guard ring 8. Specifically, a mask 11 is formed on the upper surface of the n-type high resistance layer 2, and n-type impurity ions such as P (phosphorus) are selectively implanted into the upper portion of the n-type high resistance layer 2 through the mask 11. . Then, the implanted ions are activated by the active heat treatment at about 1600 ° C., and the depletion layer restricted region 4 is formed. Here, the P (phosphorus) ion has an acceleration energy of 10 to 250.
It is implanted into a region having a depth of about 0.3 μm from the surface of the n-type high resistance layer 2 by multi-stage implantation with keV and total dose of 5 × 10 ¹⁵ cm ⁻² . As a result, the impurity concentration is 1 × 10 ²⁰
A depletion layer confined region 4 of cm ⁻³ is formed.

Here, the p-type impurity ions and the n-type impurity ions are activated by different active heat treatments, but the activation heat treatments are not limited to this and may be performed simultaneously. Further, although boron (B) ions were used as the p-type impurity ions and phosphorus (P) was used as the n-type impurity ions, it is not necessary to specify these, and aluminum (Al) is used as the p-type impurity ions and n-type impurity ions are used. Nitrogen (N) may be used as each ion.
Further, the order of forming the p-type low resistance region 3, the guard ring 8 and the depletion layer limiting region 4 is not particularly limited, and they may be freely replaced.

(D) Next, as shown in FIG.
A cathode electrode 5 is formed on the lower surface of the low resistance substrate 1 in ohmic contact. Specifically, a nickel (Ni) film having a thickness of about 1 μm is formed on the lower surface of the n-type low resistance substrate 1, and
The cathode electrode 5 is formed by performing a sintering process at about 00 ° C.

(E) Next, as shown in FIG. 4B, the photolithography method and the RIE method are applied to the upper surface of the n-type high resistance layer 2 exposed between the guard ring 8 and the depletion layer limiting region 4. And the like are used to selectively form the insulating film 6 such as an oxide film (SiO ₂ film). The insulating film 6 may be formed at least on the upper surface of the n-type high resistance layer 2, and the insulating film 6 may be formed on the guard ring 8 or the depletion layer restricted region 4 near the n-type high resistance layer 2. A part may be formed.

(V) Next, as shown in FIG. 4 (c), p
On the upper surface of the n-type high resistance layer 2 exposed between the p-type low resistance region 3, the guard ring 8 and between the p-type low resistance region 3 and the guard ring 8 and between the p-type low resistance regions 3.
A film) 12 is formed. In practice, the S film having a film thickness of about 330 nm is formed on the entire upper surface of the SiC substrate 14 without using a mask.
The i film 12 is formed. Therefore, the Si film 12 is also formed on the depletion layer limiting region 4 and the insulating film 6. Si film 12
The crystal state of is not particularly limited. That is, the Si film 12 may be an amorphous film, a polycrystalline film, or another film. When the film is an amorphous film or a polycrystalline film, a CVD method, a sputtering method, or the like can be used.

(G) Next, a refractory metal film (Ni film) 13 having a stoichiometric composition ratio of 1: 2 (= N) is formed on the Si film 12.
i: Si). It should be noted that "to make the stoichiometric composition ratio 1: 2" means that Si is performed next.
In the silicide reaction between the film 12 and the Ni film 13, Ni
The purpose is to form a disilicide film having a composition of Si ₂ without excess or deficiency. Here, the Ni film 13 having a film thickness of 110 nm is formed on the Si film 12 having a film thickness of 330 nm so that the stoichiometric composition ratio becomes 1: 2.

(H) Next, a predetermined heat treatment is performed to form Si.
Only by the silicidation reaction between the film 12 and the Ni film 13, the disilicide film (NiSi ₂
Membrane). Further, by the above heat treatment, at the same time as the anode electrode 7a, the disilicide film (NiS) which becomes the depletion layer limiting electrode 7b which makes ohmic contact with the depletion layer limiting region 4 is formed.
i ₂ film) is also formed. The "predetermined heat treatment" is
600 to 1100 ℃ in vacuum or inert gas atmosphere
It is a heat treatment at the temperature of. More preferably 900 ° C
The reason is that a silicide reaction is caused by a heat treatment of a certain degree. Here, the “inert gas” is at least one of nitrogen gas (N ₂ gas) or a rare gas such as Ar, He, and Ne, and a plurality of gases may be mixed and used. The NiSi ₂ film formed in this step is generated only by the silicidation reaction of the Si film 12 and the Ni film 13 stacked on the n-type high resistance layer 2, and the NiSi ₂ film in the n-type high resistance layer 2 is formed during the silicidation reaction. It does not consume Si atoms.

(I) Finally, the photolithography method and
NiSi using RIE method etc. _Two Membrane (12, 13)
Patterning is performed. Specifically, firstly the anode electrode
7a and a region where the depletion layer confined region 4 is formed selectively
An etching mask is formed. And through this mask
On the insulating film 6_Two The membrane (12, 13)
Of the anode electrode 7a and the space shown in FIG.
The poor layer limiting region 4 is formed. Through the above steps,
And the JBS diode shown in FIG. 2 is completed.

<Electrical Characteristics of JBS Diode> The results of evaluating the electrical characteristics of the JBS diode manufactured by the above manufacturing method are as follows. That is, the barrier height at the Schottky connection interface between the n-type high resistance layer 2 and the NiSi ₂ film (anode electrode) 7a was a very low value of 0.4 eV. In addition, the depletion layer restricted region 4 and NiS
Even in the ohmic connection with the i ₂ film (depletion layer limiting electrode) 7b, the contact resistance could be made extremely low at 1 × 10 ⁻⁶ Ωcm ² or less. On the other hand, S according to the conventional technique
The barrier height at the Schottky connection interface between the iC substrate and the Ni ₂ Si film was as high as 1.3 eV.

Specifically, in a JBS diode having a withstand voltage of 1000 V, the reverse current when a reverse voltage of 700 V is applied is 1 × 10 ⁻⁶ A / cm ² , and the forward current density is 100 A / cm ^2. The direction ON voltage was 1.0V. On the other hand, in the JBS diode having the same breakdown voltage (1000 V) using the conventional Ni Schottky connection, the barrier height is as high as about 1.4 eV, so that the forward on-voltage at the forward current density of 100 A / cm ² is It was around 2.0V. That is, when the same refractory metal (nickel) was used, the JBS diode according to the first embodiment was able to realize a reduction in on-voltage of about 1.0V. The reason why the forward on-voltage can be reduced by about 1.0 V is that the barrier height (built-in potential) at the Schottky connection interface between the silicon carbide (SiC) substrate 14 and the NiSi ₂ film is 0.4 eV, which is a very low value. It is due to becoming.

Nickel (Ni) is used as the refractory metal.
Not only when Ti, V, Cr, Co, Zr,
Even when another refractory metal such as Nb, Mo, Hf, Ta or W is used, the anode electrode 7a having the disilicide structure can be produced by the same method, and the same evaluation result can be obtained. I was able to. Specifically, when M is a refractory metal other than Ni, the barrier height at the Schottky connection interface between the disilicide structure (MSi ₂ ) and silicon carbide is 0.65e even if large.
V, which was a very low value as compared with the conventional value (1.4 eV).

Therefore, the Si film 1 is formed on the SiC substrate 14.
2 and the refractory metal film 13 are sequentially formed, and then heat treatment is performed in a vacuum or an inert gas in the range of 600 to 1100 ° C. to form the metal disilicide film (7a, 7b). It was verified that the barrier height of the contact can be significantly reduced, and as a result, the forward ON voltage can be effectively reduced without impairing the reverse characteristics such as breakdown voltage and leakage current in the JBS diode.

As described above, the Ni film 13 and the Si film 12 are laminated so that the stoichiometric composition ratio is 1: 2 (= Ni: Si), and a predetermined heat treatment is performed. As a result, the disilicide film having the NiSi ₂ structure is
It is generated only by the silicidation reaction between the Si film 12 and the Ni film 13, and does not consume Si atoms in the SiC substrate 14. Therefore, the n-type high resistance layer (SiC) 2 and NiSi
The compositional change at the Schottky connection interface with the _two films (anode electrode) 7a becomes sharp, and the Fermi level of the n-type high resistance layer 2 is pinned to a position shallow from the bottom of the conduction band, reflecting the interface structure, and the barrier height is This is a very low value of 0.4 eV.

The depletion layer limiting region 4 formed at the same time
Also in the ohmic connection between the NiSi ₂ film and the NiSi ₂ film (depletion layer limiting electrode) 7b, the contact resistance is low and very good ohmic characteristics can be obtained due to the effect that the barrier height is very low.

(Second Embodiment) <Structure of Schottky Diode> FIG. 5 is a sectional view showing a structure of a semiconductor device according to a second embodiment of the present invention. The semiconductor device according to the second embodiment is a Schottky diode in which the first anode electrode 22 having a relatively high Schottky barrier height is formed instead of the p-type low resistance region 3 in the JBS diode shown in FIG. is there.

As shown in FIG. 5, the Schottky diode comprises a SiC substrate composed of an n-type low resistance substrate 1 and an n-type high resistance layer 2, and a first anode embedded above the n-type high resistance layer 2. The electrode 22, the p-type guard ring 8 formed on the n-type high resistance layer 2 outside the first anode electrode 22, and the junction termination electrode (guard ring electrode) 23 formed on the guard ring 8. And the first anode electrode 2
2 and the guard ring electrode 23 and the first anode electrode 2
The upper surface of the n-type high resistance layer 2 exposed between the two, the second anode electrode 21 connected to the first anode electrode 22 and the guard ring electrode 23, respectively, and the guard on the upper part of the n-type high resistance layer 2. N formed outside the ring electrode 23
A low-resistance depletion layer limiting region 4, a depletion layer limiting electrode 7b ohmic-connected to the depletion layer limiting region 4, and a cathode electrode 5 ohmic-connected to the lower surface of the low-resistance substrate 1.

The first anode electrode 22, the guard ring electrode 23, and the second anode electrode 21 are made of a refractory metal silicide film. The first anode electrode 22 and the second anode electrode 21 are Schottky connected to the n-type high resistance layer 2. The barrier height of the n-type high resistance layer 2 at the Schottky connection interface with the first anode electrode 22 is higher than the barrier height of the n-type high resistance layer 2 at the Schottky connection interface with the second anode electrode 21.

One or more first anode electrodes 22 are arranged at intervals of about 2 μm. The width of the first anode electrode 22 itself is about 2 μm. The first anode electrode 22 is formed of a Ni (nickel) disilicide film (NiS).
i ₂ film).

Guard ring 8 and guard ring electrode 23
Is a portion forming a junction termination structure for increasing the breakdown voltage of the device. The guard ring 8 and the guard ring electrode 23 are ohmic-connected. The guard ring 8 and the guard ring electrode 23 are arranged outside the first anode electrode 22 with a distance of about 2 μm from the first anode electrode 22. The guard ring electrode 23, like the first anode electrode 22, is made of a Ni disilicide film. The guard ring 8 and the guard ring electrode 23 may be Schottky connected.

As in the case of the JBS diode according to the first embodiment, the depletion layer limiting region 4 is a region used to limit the depletion layer extending laterally from the Schottky connection interface, and is a guard ring. 8 and the guard ring electrode 23 are arranged at a predetermined distance from the guard ring electrode 23. The depletion layer restriction region 4 is N or P
Is a region to which an n-type impurity such as is added at a high concentration.

The second anode electrode 21, like the first anode electrode 22, is made of a Ni disilicide film. The composition change at the Schottky connection interface between the second anode electrode 21 and the n-type high resistance layer 2 is relatively steep, and the Fermi level of the n-type high resistance layer 2 is pinned to a position shallower from the lower end of the conduction band, and the barrier height. Is low. On the other hand, the composition change at the Schottky connection interface between the first anode electrode 22 and the n-type high resistance layer 2 is relatively slow, and the Fermi level of the n-type high resistance layer 2 is pinned deep from the lower end of the conduction band. The barrier height is also high.

As in the case of the JBS diode according to the first embodiment, the depletion layer limiting electrode 7b is made of a refractory metal silicide film and has the same film structure as the second anode electrode 21.

The plan shape of the Schottky diode is such that the p-type low resistance region 3 shown in FIG.
It is the same as the one replaced with. Detailed description is omitted.

<Method of Manufacturing Schottky Diode> Next, a method of manufacturing the Schottky diode shown in FIG. 5 will be described with reference to FIGS. 6 and 7. 6 and 7 are process cross-sectional views showing main manufacturing steps for manufacturing the Schottky diode.

(A) First, as shown in FIG. 6A, the n-type impurity concentration is 1 × 10 ¹⁹ cm ⁻³ and the thickness is 30.
An n-type high resistance layer 2 having an impurity concentration of 5 × 10 ¹⁵ cm ⁻³ and a thickness of 10 μm is formed on the low resistance substrate 1 made of 0 μm SiC by an epitaxial method.

(B) Next, as shown in FIG.
A guard ring 8 is formed by selectively diffusing p-type impurities on the high-resistance layer 2 of the mold.

(C) Next, as shown in FIG.
An n-type impurity is selectively diffused into the upper portion of the high-resistance layer 2 at a high concentration to form a depletion layer limiting region 4 outside the guard ring 8.

(D) Next, as shown in FIG.
A cathode electrode 5 is formed on the lower surface of the low resistance substrate 1 in ohmic contact. The above steps are similar to those in the first embodiment, and detailed description thereof will be omitted. Then, the insulating film 6 is selectively formed on the upper surface of the n-type high resistance region 2 exposed between the guard ring 8 and the depletion layer restriction region 4 by using the photolithography method and the RIE method.

(E) Next, as shown in FIG. 7B, the upper surface of the n-type high resistance region 2 in the region where the second anode electrode 21 is formed is formed by using the photolithography method and the RIE method. The Si film 24 having a thickness of about 330 nm is selectively formed. At this time, the Si film 24 is also formed on the depletion layer restricted region 4.

(E) Next, as shown in FIG.
The n-type high resistance layer 2 exposed between the i film 24 and the Si film 24,
The Ni film 2 is formed on the guard ring 8 so that the stoichiometric composition ratio with the Si film 24 is 1: 2 (= Ni: Si).
5 is selectively formed. Here, S with a film thickness of 330 nm
A Ni film 25 having a film thickness of 110 nm is formed on the i film 24.

(G) Next, a predetermined heat treatment is performed to simultaneously form a first silicide film and a second silicide film shown below. That is, the first silicide film is a film formed by the silicide reaction between the n-type high resistance layer 2 or the guard ring 8 and the Ni film 25, and forms the first anode electrode 22 and the guard ring electrode 23. On the other hand, the second silicide film is a film generated only by the silicide reaction between the Si film 24 and the Ni film 25, and the second anode electrode 21.
And the depletion layer limiting electrode 7b is formed. In the formation of the second silicide film, Si atoms in the n-type high resistance layer 2 are not consumed. The “predetermined heat treatment” is a heat treatment at a temperature of 600 to 1100 ° C. in an atmosphere of vacuum or an inert gas. More preferably, a silicide reaction is caused by heat treatment at about 900 ° C. The Schottky diode shown in FIG. 5 is completed through the above steps.

As described above, the Ni film 25 and the Si film 24 are laminated so that the stoichiometric composition ratio is 1: 2 (= Ni: Si), and a predetermined heat treatment is performed. As a result, the second silicide film becomes the Si film 24 and the Ni film 25.
It is generated only by the silicidation reaction with and does not consume Si atoms in the SiC substrate (n-type high resistance layer 2) during the silicidation reaction. Therefore, the n-type high resistance layer (Si
C) The composition change at the Schottky connection interface between 2 and the second anode electrode 21 becomes sharp, and the barrier height (built-in potential) is 0.4 eV, which is a very low value.

On the other hand, the first silicide film is made of SiC.
A Ni film 25 is formed directly on (2, 8) and S in SiC is added.
It is generated from the silicide reaction between i and Ni. That is, the first silicide film is formed by the method according to the conventional technique. Therefore, the composition change at the Schottky connection interface between the n-type high resistance layer (SiC) 2 and the first anode electrode 22 becomes slow, and the barrier height (built-in potential) is 1.3e.
Rise to V.

Therefore, the anode electrodes (21, 22)
When a reverse voltage is applied between the cathode and the cathode electrode 5,
The depletion layer extending from the first anode electrode 22 having a high barrier height NiSi structure into the n-type high resistance layer 2 is a Schottky of the second anode electrode 21 having a low barrier height NiSi ₂ structure and the n-type high resistance layer 2. Relaxes the electric field strength at the interface. Therefore, the reverse leakage current can be made extremely low. For example, when a reverse voltage of 700 V is applied to a Schottky diode having a breakdown voltage of 1000 V, a reverse leakage current of 1 × 10 ⁻⁶ A /
It can be suppressed to about cm ² .

Also in the ohmic connection between the depletion layer limiting region 4 and the depletion layer limiting electrode 7b, the contact resistance is 1 × 10 ⁻⁶ Ω because of the effect that the barrier height is very low.
It can be suppressed to as low as cm ² or less, and very good ohmic characteristics can be obtained.

(Third Embodiment) <Structure of Static Induction Transistor> FIG. 8 shows a third embodiment of the present invention.
3 is a cross-sectional view showing the configuration of the semiconductor device according to the embodiment of FIG. The semiconductor device according to the third embodiment is an electrostatic induction transistor in which a gate region is formed outside a source region, and a junction termination region 43 and a depletion layer limiting region 4 are formed outside the gate region.

As shown in FIG. 8, the static induction transistor is composed of an n-type low resistance substrate 1 and an n-type high resistance layer S.
The iC substrate, the n-type low resistance source region 32 formed on the n-type high resistance layer 2, and the p-type gate region 31 formed outside the source region 32 on the n-type high resistance layer 2. And the gate region 31 in the upper part of the n-type high resistance layer 2.
Of the junction termination region 43 formed outside the junction termination region 43, the n-type low resistance depletion layer limiting region 4 formed outside the junction termination region 43 in the upper portion of the n-type high resistance layer 2, and the source region 32. Source electrode 34 and gate region 31
A gate electrode 33 ohmic-connected to the depletion layer limiting electrode 7b ohmic-connected to the depletion layer limiting region 4;
It has a drain electrode ohmic-connected to the lower surface of the low resistance substrate 1. The source electrode 34, the gate electrode 33, and the depletion layer limiting electrode 7b are made of a refractory metal silicide film.

Gate electrode 33 and depletion layer limiting electrode 7b
Has a film structure similar to that of the source electrode 34. In the third embodiment, as the refractory metal silicide film, a Co (cobalt) disilicide film (CoSi ₂
The case of using a membrane will be described.

The junction termination region 43 is a portion having a junction termination structure for increasing the breakdown voltage of the device. The junction termination region 43 is one or more semiconductor regions to which p-type impurities are added. In the third embodiment, three gate regions 31 and three depletion layer limited regions 4 are formed. An insulating film 37 is arranged on the upper surface of the n-type high resistance layer 2 exposed between the source region 32, the gate region 31, and the depletion layer limiting region 4, and the insulating film 37 allows each electrode (3
2, 33, 7b) is insulated from the n-type high resistance layer 2 or the junction main end region 43.

The planar shape of the static induction transistor is shown in FIG.
The two p-type low resistance regions 3 shown in FIG.
2 and the guard ring 8 is replaced with the gate region 31. In the static induction transistor, three junction termination regions 4 in a ring shape (rectangular shape) are provided between the gate region 31 and the depletion layer limiting region 4.
3 is arranged.

<Method of Manufacturing Static Induction Transistor> Next, a method of manufacturing the static induction transistor shown in FIG. 8 will be described with reference to FIGS. 9 and 10. 9 and 10 are process cross-sectional views showing main manufacturing steps in manufacturing the static induction transistor.

(A) First, as shown in FIG. 9A, the n-type impurity concentration is 1 × 10 ¹⁹ cm ⁻³ and the thickness is 30.
An n-type high resistance layer 2 having an impurity concentration of 5 × 10 ¹⁵ cm ⁻³ and a thickness of 10 μm is formed on the low resistance substrate 1 made of 0 μm SiC by an epitaxial method. Then, the source region 32 is formed by selectively diffusing the n-type impurity into the upper portion of the n-type high resistance layer 2 at a high concentration through the mask 38. Here, P (phosphorus) ions are used as the acceleration energy 10
Depth of 0.3 μm from the surface of the n-type high resistance layer 2 by multi-step implantation of ˜250 keV and total dose of 5 × 10 ¹⁵ cm ^−2.
Inject into the region of degree. The active heat treatment of 1600 ° C., the impurity concentration of 1 × ¹⁰ 20 cm ^{- 3} in the source region 3
2 is formed.

(B) Next, as shown in FIG. 9B, p is selectively formed on the n-type high resistance layer 2 through the mask 39.
The type impurities are diffused at a high concentration to form the gate region 31 outside the source region 32. Here, B (boron)
Ions are implanted into the region having a depth of about 0.8 μm from the surface of the n-type high resistance layer 2 by multi-stage implantation with an acceleration energy of 10 to 400 keV and a total dose of 1 × 10 ¹⁵ cm ⁻² .
Impurity concentration 1 × 10 by activation treatment at 1600 ℃
^{A 19} cm ⁻³ gate region 31 is formed.

(C) Next, as shown in FIG. 9C, p is selectively formed on the n-type high resistance layer 2 through the mask 44.
The type impurities are diffused at a high concentration to form the junction termination region 43 outside the gate region 31.

(D) Next, as shown in FIG.
Through the mask 40, n-type impurities are selectively diffused into the upper portion of the n-type high resistance layer 2 at a high concentration to form the depletion layer limiting region 4 outside the junction termination region 43. Although the source region 32, the gate region 31, the junction termination region 43, and the depletion layer limiting region 4 are formed by different activation heat treatments here, these diffusion regions may be activated simultaneously. The order of forming the source region 32, the gate region 31, the junction termination region 43, and the depletion layer limiting region 4 is not particularly limited, and they may be freely replaced. Then, Ni having a thickness of 1 μm is vapor-deposited on the lower surface of the n-type low-resistance substrate 1, and 1000
The drain electrode 36 is formed by performing a sintering process at about ° C.

(E) Next, as shown in FIG.
An insulating film 37 is formed on the n-type high resistance region 2 and the junction termination region 43 exposed between the source region 32, the gate region 31, and the depletion layer limiting region 4 by using the photolithography method and the RIE method. Selectively formed.

(V) Next, as shown in FIG.
The Si film 41 and the Co film 42 are selectively formed on the entire upper surface of the SiC substrate so that the stoichiometric composition ratio is 1: 2 (= Co: Si). Here, first, the Si film 41 having a film thickness of 330 nm is vapor-deposited on the entire upper surface of the SiC substrate, and then,
A Co film 42 having a film thickness of 100 nm is deposited.

(G) Next, a predetermined heat treatment is performed to form Si.
Only by the silicidation reaction between the film 41 and the Co film 42, the disilicide film (Co) that will become the respective electrodes (33, 34, 7b) is formed.
A Si ₂ film). The "predetermined heat treatment" is
600 to 1100 ℃ in vacuum or inert gas atmosphere
It is a heat treatment at the temperature of. More preferably 900 ° C
The reason is that a silicide reaction is caused by a heat treatment of a certain degree. In addition, each semiconductor region (3
No Si atoms in 1, 32, 4) are consumed.

(H) Finally, the photolithography method and
By using RIE method or the like, CoSi _Two Membrane patterning
The source electrode 34 and the gate electrode 3 shown in FIG.
3 and the depletion layer limiting electrode 7b are formed at the same time. More than
Through the process, the electrostatic induction transistor shown in Fig. 8 is completed.
To do.

As described above, the CoSi ₂ film is
It is generated only by the silicidation reaction between the Si film 41 and the Co film 42, and does not consume Si atoms in the SiC substrate (n-type high resistance layer 2) during the silicidation reaction. As a result, the source region 32 and the source electrode (CoSi ₂ ) 3
The composition change at the ohmic contact interface with 4 becomes sharp, and the barrier height is 0.5 eV reflecting this interface structure.
The value is very low. As a result, the contact resistance of ohmic connection is 1 × 10 ⁻⁶ Ωcm ² or less, which is a very good ohmic characteristic. Also in the ohmic contact between the gate region 31 and the gate electrode (CoSi ₂ ) 33 which are formed at the same time, the contact resistance is 1 × 10 ⁻⁶ Ωcm ² or less, which is a very good ohmic characteristic, reflecting the similarly steep interface structure. Can be obtained.

On the other hand, according to the conventional method, the composition change at the interface is changed.
Becomes slower and the barrier height is as high as 1.2 eV.
Will end up. As a result, the source region 32 and the gate region 3
1 ohmic contact between CoSi film and CoSi film
However, the contact resistance is 1 × 10 ^-3 Ω cm^Two Degree and very
It also becomes high and exhibits Schottky-like characteristics.

<Electrical Characteristics of Static Induction Transistor> The results of evaluating the electrical characteristics of the static induction transistor manufactured by the above manufacturing method are as follows. Pressure resistance 10
In the static induction transistor of 00V, when the gate voltage (-25V) and the drain voltage (600V) were applied, the drain current showed a very low value of 1 × 10 ⁻⁶ A / cm ² . And forward current density 100 A / c
The forward ON voltage at m ² was 1.5V.

On the other hand, in the static induction transistor using CoSi ohmic contact according to the conventional method,
Comparing elements with the same breakdown voltage (1000 V), CoSi
Contact resistance of ohmic contact is 1 × 10 ^-3 Ωc
It is very high, around m ² . Further, since it exhibits Schottky-like characteristics, the forward ON voltage is around 2.5V.
Therefore, even if the same electrode material is used, the on-voltage of about 1.0 V can be reduced in the static induction transistor according to the third embodiment. Therefore, by adopting the above configuration, in the electrostatic induction transistor, without impairing the gate breakdown voltage characteristics such as breakdown voltage and leakage current,
The forward ON voltage can be effectively reduced.
Although the case where Co is used as the electrode material is shown here as an example, the gate electrode and the source electrode having the disilicide structure are formed by the same method when other materials such as Ti, V, and Cr are used. It was possible to obtain the same effect.

As a modification of the third embodiment,
The present invention can also be applied to an electrostatic induction thyristor. In the case of the static induction thyristor, the polarity of the low resistance substrate 1 shown in FIG. 8 may be p type.

(Fourth Embodiment) <Structure of Trench Type Static Induction Transistor> In a semiconductor device according to a fourth embodiment, a trench type gate region 51 is formed outside a source region 52. This is a trench type static induction transistor in which a junction termination region 58 and a depletion layer confined region 4 are formed outside thereof.

As shown in FIG. 12, the trench type static induction transistor is formed on the SiC substrate 14 composed of the n-type low resistance substrate 1 and the n-type high resistance layer 2 and on the n-type high resistance layer 2. The n-type low resistance source region 52, the concave portion (trench) 59 of the n-type high resistance layer 2 formed outside the source region 52 above the n-type high resistance layer 2, and the bottom surface 63 of the trench 59. P-type gate region 51,
A p-type guard ring 58 formed outside the gate region 51 on the n-type high resistance layer 2 and an n-type low resistance depletion formed on the outside of the guard ring 58 on the n-type high resistance layer 2. The layer limiting region 4, the source electrode 54 ohmic-connected to the source region 52, and the gate region 5
1 and the gate electrode 53 ohmic-connected to the depletion layer limiting electrode 55 ohmic-connected to the depletion layer limiting region 4
And a drain electrode 56 ohmic-connected to the lower surface of the low resistance substrate 1. Source electrode 54, gate electrode 5
3 and the depletion layer limiting electrode 55 are each made of a refractory metal silicide film.

The gate electrode 53, the depletion layer limiting electrode 55 and the source electrode 54 have the same film structure. In the fourth embodiment, a case where a Ni disilicide film (NiSi ₂ film) is used as the “refractory metal silicide film” will be described.

The trench 59 is arranged adjacent to the outside of the source region 52, and the source region 52 is exposed on the side surface of the trench 59. The gate electrode 53 is a trench 59.
Is ohmic-connected to the gate region 51 via the bottom surface 63 of the. The first insulating film 57 is formed on the side surface of the trench 59.
a is arranged. The first insulating film 57a insulates the gate electrode 53 from the n-type high resistance layer 2 and the gate electrode 53 from the source region 52.

The guard ring 58 is the JBS shown in FIG.
Similar to the case of a diode, this is a portion that forms a junction termination structure for increasing the breakdown voltage of the device. Guard ring 58
Is about 2 μm from the trench 59 outside the gate region 51.
It is composed of two regions which are arranged at intervals of and in which a p-type impurity is added at a high concentration.

The depletion layer limiting region 4 is a region used for limiting the depletion layer extending laterally in the n-type high resistance layer 2 from the pn junction interface between the n-type high resistance layer 2 and the gate region 51. . The depletion layer restriction region 4 is a region which is arranged at a predetermined distance from the guard ring 58 and in which an n-type impurity such as N or P is added at a high concentration. Depletion layer limiting electrode 55
Is ohmic-connected to the depletion layer limiting region 4, the potential inside the depletion layer limiting region 4 is kept more uniform, and the depletion layer limiting function of the depletion layer limiting region 4 is further improved.

A second insulating film 57b is disposed on the guard ring 58 and the n-type high resistance layer 2 exposed between the gate region 51 and the depletion layer limiting region 4. The second insulating film 57b is formed continuously with the first insulating film 57a.

The planar shape of the trench type static induction transistor is substantially the same as that of the two p type low resistance regions 3 shown in FIG. 2 replaced with one source region 52 and the guard ring 8 replaced with a gate region 51. Is the same as In the trench static induction transistor, a ring-shaped (rectangular) guard ring 58 is arranged between the gate region 51 and the depletion layer restricted region 4. Each electrode region is not limited to the ring shape shown in FIG. 2 and may be the stripe shape shown in FIG.

<Manufacturing Method of Trench Type Static Induction Transistor> Next, a manufacturing method of the trench type static induction transistor shown in FIG. 12 will be described with reference to FIGS. 13 and 14. It is needless to say that the method of manufacturing the trench-type static induction transistor described below can be realized by various manufacturing methods other than this.

(A) First, the n-type impurity concentration is 1 × 10.¹⁹
cm^-3, Low resistance substrate made of 300 μm thick SiC
1 has an impurity concentration of 1x by an epitaxial growth method.
10 ¹⁶cm^-3, N-type high resistance layer 2 having a thickness of 8 μm is formed
To do. This prepares the n-type high resistance SiC substrate 14.
To be done.

(B) Next, as shown in FIG.
A mask 60 made of an oxide film, a nitride film, a metal film, or the like is formed on the upper surface of the n-type high resistance layer 2. Using the mask 60, n-type impurity ions are selectively implanted into the upper portion of the n-type high resistance layer 2. Here, phosphorus (P) ions are used at an acceleration energy of 10 to 250 keV and a total dose of 5 × 10 ¹⁵ cm.
^{-2 in} a multi-step implantation process is performed from the upper surface of the n-type high resistance layer 2 to a region having a depth of about 0.3 μm. By performing activation heat treatment at about 1600 ° C., an impurity concentration of 1 × 10 ²⁰
A cm ⁻³ n ⁺ region 61 and a depletion layer confined region 4 are formed. The n ⁺ region 61 is a region including the source region 52 of FIG.

As the n-type impurity ions, nitrogen (N) ions may be used instead of P ions. Also, P ions and N ions may be used in combination. Here, the case where the n ⁺ region 61 and the depletion layer limiting region 4 are formed at the same time has been described, but they may be formed by different ion implantation steps and heat treatment steps.

(C) Next, as shown in FIG.
A mask 62 made of an oxide film or a metal film having an opening is formed in a region where the trench 59 of FIG. 12 is formed. Anisotropic etching such as RIE is performed using the mask 62 to selectively remove the n ⁺ region 61 and a part of the n-type high resistance layer 2. A trench 59 penetrating the source region 52 and having a bottom surface 63 reaching the n-type high resistance layer 2 is formed.

(D) Next, an oxide film is formed on the bottom surface 63 and side surfaces of the trench 59 and the upper surface of the n-type high resistance layer 2.
Then, the trench 5 is formed by anisotropic etching such as RIE.
The oxide film in the region where the bottom surface 63 of 9 and the guard ring 58 are formed is selectively removed to form a mask 64 as shown in FIG.

(E) Next, using the mask 64, p-type impurity ions are selectively implanted into the n-type high resistance layer 2. Here, the boron (B) ion has an acceleration energy of 10 to 40.
Multi-stage implantation is performed under the conditions of 0 keV and a total dose of 1 × 10 ¹⁴ cm ⁻² . After removing the mask 64, activation heat treatment at about 1600 ° C. is performed to form the gate region 51 on the bottom surface 63 of the trench 59 as shown in FIG. 14A, and the guard ring 58 is formed outside the gate region 51. Is formed. The gate region 51 and the guard ring 58 are formed in a region having a depth of 0.8 μm with an impurity concentration of 1 × 10 ¹⁸ cm ⁻³ .

It should be noted that aluminum (Al) ions may be used as the p-type impurity ions instead of B ions. Further, B ions and Al ions may be used in combination. Here, the case where the gate region 51 and the guard ring 58 are formed at the same time has been described, but they may be formed by different ion implantation steps and heat treatment steps. In addition, the n ⁺ region 61 and the depletion layer limiting region 4 in FIG. 13A, the trench in FIG. 13B, and FIG. 14A.
The formation order of the gate region 51 and the guard ring 58 of
The present invention is not limited to the one shown here, and may be replaced.

(F) Next, an insulating film such as an oxide film and a nitride film is formed on the bottom surface and the side surface of the trench 59 and the upper surface of the n-type high resistance layer 2 by the CVD method. Then, a mask is formed in the region where the second insulating film 57b of FIG. 12 is formed. The insulating film is selectively removed through this mask by anisotropic etching such as RIE. As shown in FIG. 14B, the first insulating film 57a and the second insulating film 57b are formed, and the source region 52, the gate region 51, and the depletion layer restricted region 4 are exposed. At this time, the etching conditions for anisotropic etching are set so that the first insulating film 57 is formed on the side surface of the trench.
a is formed.

(G) Next, as shown in FIG.
A silicon (Si) film 65 having a thickness of about 100 nm is selectively formed on the exposed source region 52, gate region 51, and depletion layer limiting region 4 by the vapor phase selective growth method. At this time, as a raw material gas for the Si film 65, for example, SiH ₂ Cl
A mixed gas of ₂ gas and HCl gas diluted with H ₂ gas is used. The pressure is set to a low pressure on the order of 10 Torr, for example. As the source gas, SiH ₄ gas or Si ₂ H ₆ gas may be used instead of SiH ₂ Cl ₂ gas. The thickness of the Si film 65 is set so that the Si film does not grow on the first and second insulating films 57a and 57b.
It should be 100 nm or less.

(H) Next, as shown in FIG.
A thickness 33 is formed on the bottom surface and the side surface of the trench 59 and on the upper surface of the n-type high resistance layer 2 by a vacuum deposition method or a sputtering method.
A Ni film 66 having a thickness of nm is deposited. Here, the thickness of the Si film 65 (100 nm) and the thickness of the Ni film 66 (33 nm)
Are selected such that the stoichiometric composition ratio is 1: 2 (= Ni: Si). After that, heat treatment is performed at 600 ° C. to 1100 ° C., preferably about 900 ° C. in a vacuum or an inert gas to cause the Si film 65 and the Ni film 66 to undergo a silicide reaction without excess or deficiency. A Ni disilicide film (NiSi ₂ film) is formed on the source region 52, the gate region 51, and the depletion layer limiting region 4. By chemically cleaning the upper surface of the n-type high resistance layer 2, the unreacted Ni film 6
Remove 6. That is, the first and second insulating films 57
The Ni film 66 deposited on a and 57b is removed.

(I) Finally, a thickness of about 1 is formed on the back surface of the n-type low resistance substrate 1 by using the vacuum evaporation method or the sputtering method.
A μm Ni film is deposited. A drain electrode 56 is formed as shown in FIG. 14C by a sintering process at about 1000 ° C. Through the above steps, the trench static induction transistor shown in FIG. 12 is completed.

By combining the selective growth technique of the Si film 65 on the source region 52, the gate region 51, and the depletion layer confined region 4, and the subsequent silicide process technique, the disilicide film (NiSi ₂ film) is removed. The source electrode 54, the gate electrode 53, and the depletion layer limiting electrode 55 can be simultaneously formed in a self-aligned manner.

As described above, the source electrode 54, the gate
The gate electrode 53 and the depletion layer limiting electrode 55 are the Si film 65.
Produced only by the silicide reaction between Ni and Ni film 66
Si _TwoSince it is a film, the SiC substrate during the silicide reaction
It does not consume the Si atoms in 14. For this reason,
Ohmic connection interface between the source region 52 and the source electrode 54
The composition change in the
The barrier height is as low as 0.5 eV.
It As a result, the contact between the source region 52 and the source electrode 54
Touch resistance is 1x10^-6Ω cm^TwoVery good with
Ohmic characteristics can be obtained. In addition, the game formed simultaneously
On the ohmic connection interface between the gate region 51 and the gate electrode 53.
In addition, the contact resistance also reflects the steep interface structure.
1x10^{− 6}Ω cm^TwoVery good ohmi
It is possible to obtain the characteristics.

On the other hand, in the prior art, the compositional change at the interface becomes slow and the barrier height becomes as high as about 1.2 eV. As a result, the contact resistance is 1 × 10 ⁻² Ωcm particularly in the ohmic connection between the gate region and the Ni ₂ Si film.
^It becomes extremely high at ² or more, and also exhibits Schottky-like characteristics.

<Electrical Characteristics of Trench Type Static Induction Transistor> The results of evaluating the electrical characteristics of the trench type static induction transistor manufactured by the above manufacturing method are as follows. In a trench type static induction transistor having a breakdown voltage of 1000V, when a gate voltage of -40V and a drain voltage of 600V are applied, the drain current is 1x10.
^It showed a very low value of ⁻⁶ A / cm ² . Further, when the forward current density was 100 A / cm ² , the forward ON voltage was 1.5V.

On the other hand, the trench type static induction transistor using the Ni ₂ Si ohmic contact according to the prior art has a very high contact resistance of the gate electrode of 1 × 10 ⁻² Ωcm ² or more and shows Schottky-like characteristics. Will end up. Therefore, even if a negative bias is applied to the gate electrode 53, an electric field is held at the connection interface between the gate electrode 53 and the gate region 51, and no voltage is applied to the gate region 51 itself, so that a satisfactory off operation cannot be performed.

Therefore, according to the trench type static induction transistor of the fourth embodiment, by using the NiSi ₂ film for the source electrode 54, the gate electrode 53, and the depletion layer limiting electrode 55, the breakdown voltage and the leakage current are reduced. The forward ON voltage can be effectively reduced without impairing the gate breakdown voltage characteristics such as In addition, the electric field is not retained at the connection interface between the gate electrode 53 and the gate region 51, and
A gate voltage is applied to itself, and a satisfactory off operation can be performed at high speed. Therefore, the switching speed of the device is improved. Here, N is used as the electrode material of the refractory metal.
Although an example using i is shown, other materials such as Ti,
Even when V, Cr, Ni, Zr, Nb, Mo, Hf, Ta or W is used, the gate electrode 53 and the source electrode 54 having the disilicide structure can be formed by the same method, and similar results can be obtained. did it.

Further, as a modification of the fourth embodiment,
The present invention can also be applied to an electrostatic induction thyristor. In the case of the static induction thyristor, the conductivity type of the low resistance substrate 1 shown in FIG. 12 may be p type.

(Fifth Embodiment) <Structure of Bipolar Transistor> In a semiconductor device according to a fifth embodiment, a mesa-shaped base layer and an emitter layer are formed on a SiC substrate including a collector layer. Further, it is a bipolar transistor in which a junction termination region and a depletion layer limiting region are formed outside the base layer above the collector layer.

As shown in FIG. 15, the bipolar transistor includes an n-type high resistance SiC substrate 14 and an SiC substrate 1.
4, a mesa-shaped p-type base layer 79 formed on
The mesa-shaped n-type emitter layer 72 formed on the base layer 79 and the emitter layer 7 on the base layer 79.
2 and a p-type low resistance base contact region 71 formed outside the base layer 79 and the base layer 79 on the SiC substrate 14.
P-type junction termination region 78 formed on the outside of the
The n-type depletion layer limiting region 4 formed outside the junction termination region 78 in the upper portion of the substrate 14, the emitter electrode 74 ohmic-connected to the emitter layer 72, and the base electrode 73 ohmic-connected to the base contact region 71.
And at least a depletion layer limiting electrode 55 ohmic-connected to the depletion layer limiting region 4, and a collector electrode 76 ohmic-connected to the lower surface of the SiC substrate 14. The emitter electrode 74 and the base electrode 73 each include a refractory metal silicide film disposed at least at the ohmic contact interface.

In the fifth embodiment, the bipolar transistor is the first transistor formed on the side surface of the emitter layer 72.
Of the side wall insulating film 77a, the side surface of the base layer 79, the junction termination region 78, and the upper surface of the SiC substrate 14.
And a side wall insulating film 77b. SiC substrate 14
Is a low resistance substrate 1 made of SiC to which an n-type impurity such as nitrogen (N) or phosphorus (P) is added at a high concentration, and a low resistance substrate 1 arranged on the low resistance substrate 1 And an n-type high resistance collector layer 80 having a low n-type impurity concentration.

The base layer 79 is arranged on a part of the collector layer 80. The junction termination region 78 and the depletion layer limiting region 4 are arranged on the collector layer 80 where the base layer 79 is not arranged and exposed on the upper surface of the collector layer 80.

The emitter layer 72 is arranged on a part of the base layer 79. The first side wall insulating film 77 a is arranged on a part of the base layer 79 along the side surface of the emitter layer 72. The base contact region 71 is arranged on the base layer 79 where the emitter layer 72 and the first sidewall insulating film 77a are not arranged.

The emitter electrode 74, the base electrode 73 and the depletion layer limiting electrode 55 are each made of a refractory metal silicide film. As the “high melting point metal silicide film”, a Ni disilicide film (NiSi ₂ film) is used.

The collector electrode 76 is ohmic-connected to the lower surface of the low resistance substrate 1. If there is another means for ohmic-connecting the collector electrode 76 to the collector layer 80,
The low resistance substrate 1 is unnecessary, and the SiC substrate 14 may be composed of only the collector layer 80.

The first sidewall insulating film 77a is formed of the emitter layer 7
2 and the base electrode 73 and between the emitter layer 72 and the base contact region 71 are insulated. The second sidewall insulating film 77b is formed on the side surface of the base layer 79 and the junction termination region 78.
And the upper surface of the collector layer 80. That is, the second sidewall insulating film 77b is arranged in the side surface of the base layer 79 and in the area from the side surface of the base layer 79 to the depletion layer restriction region 55.

The junction termination region 78 is a portion which constitutes a junction termination structure for increasing the withstand voltage of the device. Here, the junction termination extension (J
TE) structure is used. The depletion layer restricted region 4 is the same as the depletion layer restricted region 4 shown in FIG.

The planar shape of the bipolar transistor is substantially the same as that shown in FIG. 2 in which the two p-type low resistance regions 3 are replaced by one emitter layer 72 and the guard ring 8 is replaced by the base contact region 71. is there. In addition,
In the bipolar transistor, a ring-shaped (rectangular) junction termination region 78 is arranged between the base contact region 71 and the depletion layer restriction region 4. Each electrode region is not limited to the ring shape shown in FIG. 2 and may be the stripe shape shown in FIG.

<Method of Manufacturing Bipolar Transistor> Next, a method of manufacturing the bipolar transistor shown in FIG. 15 will be described with reference to FIGS. It is needless to say that the bipolar transistor manufacturing method described below can be realized by various manufacturing methods other than this.

(A) First, the n-type impurity concentration is 1 × 10 ¹⁹
An n-type high-resistance collector layer 80 having an n-type impurity concentration of 1 × 10 ¹⁶ cm ⁻³ and a thickness of 8 μm is formed on the low-resistance substrate 1 made of SiC and having a thickness of cm ⁻³ and a thickness of 300 μm by an epitaxial growth method. As a result, n-type high resistance Si
The C substrate 14 is prepared.

(B) Next, as shown in FIG.
P is formed on the collector layer 80 by an epitaxial growth method.
A base layer 79 having a type impurity concentration of 3 × 10 ¹⁸ cm ⁻³ and a thickness of 0.1 μm is formed. Similarly, an n-type impurity concentration of 1 × 10 ¹⁹ cm ⁻³ and a thickness of 0.4 μm are formed on the base layer 79.
An n-type low resistance emitter layer 72 is formed.

(C) Next, as shown in FIG.
An oxide film or a metal film having the shape of the base layer 79 shown in FIG. RI using an oxide film or a metal film as a mask
The emitter layer 72 and the base layer 79 are processed into a mesa shape by anisotropic etching such as E. Next, after removing the mask, an oxide film or a metal film having the shape of the emitter layer 72 shown in FIG. 15 is formed on the emitter layer 72. The emitter layer 72 is processed into a mesa shape by anisotropic etching such as RIE using the oxide film or the metal film as a mask. Note that the emitter layer 72 and the base layer 79 may be performed by changing the order of mesa processing. As a result, FIG.
As shown in (b), a mesa-shaped emitter layer 72 and a base layer 79 are formed on the SiC substrate 14.

(D) Next, the emitter layer 72 and the base layer 7
An oxide film is formed on the collector layer 80 and the collector layer 80. The oxide film is selectively removed by using the photolithography method and the RIE method, and as shown in FIG. 16C, a mask 81 having openings in the base contact region 71 and the junction termination region 78 is formed. Base layer 7 through mask 81
9 and the collector layer 80 are selectively aluminum (Al)
P-type impurity ions such as ions are implanted. here,
Al ion, acceleration energy 20 keV, dose 2
Ion implantation is performed under the condition of x10 ¹⁵ cm ^-2 . Mask 8
After 1 is removed, activation heat treatment at about 1600 ° C. is performed. As shown in FIG. 16C, each depth is 0.05 μm,
A base contact region 71 and a junction termination region 78 having a p-type impurity concentration of 1 × 10 ²¹ cm ⁻³ are formed.

The p-type impurity ions are not limited to Al ions, and boron (B) ions may be used. Alternatively, Al ions and B ions may be used in combination. Here, the case where the base contact region 71 and the junction termination region 78 are formed at the same time has been described, but they may be formed by different ion implantation steps and heat treatment steps.

(E) Next, the emitter layer 72 and the base layer 7
An oxide film is formed on the collector layer 80 and the collector layer 80. The oxide film is selectively removed by using the photolithography method and the RIE method, and a mask 82 having an opening in the depletion layer limiting region 4 is formed as shown in FIG. N-type impurity ions such as phosphorus (P) ions are selectively implanted into the collector layer 80 through the mask 82. Here, the P layer is subjected to multi-stage implantation with an acceleration energy of 10 to 250 keV and a total dose of 5 × 10 ¹⁵ cm ⁻² , whereby the collector layer 8 is formed.
Ions are implanted from the upper surface of 0 into a region having a depth of about 0.3 μm. After removing the mask 82, activation heat treatment at about 1600 ° C. is performed. As shown in FIG. 17A, a depletion layer restriction region 207 having an n-type impurity concentration of 1 × 10 ²⁰ cm ⁻³ is formed.

It should be noted that nitrogen (N) ions may be used as n-type impurity ions without being limited to P ions. Also, P ions and N ions may be used in combination. In addition, the base contact region 71 of FIG.
The order of forming the junction terminating region 78 and the depletion layer limiting region 4 of FIG. 17A is not limited to that shown here, and may be replaced with each other.

(F) Next, an insulating film such as an oxide film and a nitride film is formed on the emitter layer 72, the base layer 79 and the collector layer 80 by the CVD method. Second sidewall insulating film 7
A mask is selectively formed in the region where 7b is formed. Anisotropic etching such as RIE is performed through this mask,
The insulating film on the emitter layer 72, the base contact region 71 and the depletion layer limiting region 4 is selectively removed. FIG. 17
As shown in (b), the first sidewall insulating film 77a and the second sidewall insulating film 77a
The side wall insulating film 77b is formed, and the emitter layer 72, the base contact region 71, and the depletion layer limiting region 4 are exposed.
At this time, the etching conditions for anisotropic etching are
It is set so that the first sidewall insulating film 77a is formed on the side surface of the emitter layer 72.

(G) Next, as shown in FIG.
A silicon (Si) film 83 having a thickness of about 100 nm is selectively grown on the exposed emitter layer 72, base contact region 71 and depletion layer limiting region 4 by the vapor phase selective growth method. At this time, as the source gas of the Si film 83, for example, a mixed gas of SiH ₂ Cl ₂ gas and HCl gas diluted with H ₂ gas is used. The pressure is, for example, 10 Tor
Set to low pressure of r units. As a source gas, Si
SiH ₄ gas or Si ₂ H instead of H ₂ Cl ₂ gas
You may use ₆ gas. Further, the thickness of the Si film 83 needs to be 100 nm or less so that the Si film does not grow on the first and second sidewall insulating films 77a and 77b.

(H) Next, as shown in FIG.
Si film 83 and first and second sidewall insulating films 77a, 77
thickness on b by vacuum deposition or sputtering
A 33 nm nickel (Ni) film 84 is deposited. here
Of the Si film 83 (100 nm) and the Ni film 84
The thickness (33 nm) has a stoichiometric composition ratio of 1: 2 (= N
i: Si). Then vacuum
Or 600 ° C to 1100 ° C in an inert gas, as desired
Or heat treatment at about 900 ° C. to remove Si film 83 and Ni.
The film 84 is silicide-reacted without excess or deficiency. Emitter layer
72, base contact region 71, and depletion layer limiting region 4
On top of the Ni disilicide film (NiSi _TwoFilm) formed
To be done. The upper surface side of the collector layer 80 may be chemically cleaned.
Thus, the unreacted Ni film 84 is removed. That is,
Deposited on the first and second sidewall insulating films 77a and 77b.
The Ni film 84 thus removed is removed.

(I) Finally, the thickness of about 1 is formed on the lower surface of the n-type low resistance substrate 1 by using the vacuum evaporation method or the sputtering method.
A μm Ni film is deposited. The collector electrode 76 is formed by a sintering process at about 1000 ° C. Through the above steps, the bipolar transistor shown in FIG. 15 is completed.

Emitter layer 72, base contact region 7
1 and the depletion layer confined region 4 by combining the selective growth technique of the Si film 83 and the subsequent silicide process technique, the disilicide film (NiSi
It is possible to simultaneously form the emitter electrode 74, the base electrode 73, and the depletion layer limiting electrode 55 composed of _two films in a self-aligned manner.

As described above, the emitter electrode 74,
The base electrode 73 and the depletion layer limiting electrode 55 are formed of the Si film 83.
And Ni formed only by the silicide reaction of the Ni film 84
Si _TwoSince it is a film, the SiC substrate during the silicide reaction
It does not consume the Si atoms in 14. For this reason,
Ohmic connection field between the miter layer 72 and the emitter electrode 74
The composition change on the surface becomes steep and this interface structure is reflected
And the barrier height is as low as 0.5 eV.
It As a result, the emitter layer 72 and the emitter electrode 74
Contact resistance is 1x10^-6Ω cm^TwoVery good with
Good ohmic characteristics can be obtained. In addition,
Ohmic contact between the base contact region 71 and the base electrode 73.
The same applies to the connection, reflecting the sharp interface structure.
Touch resistance is 1x10^-5Ω cm^TwoVery good with
Ohmic characteristics can be obtained.

On the other hand, in the prior art, the compositional change at the interface becomes slow and the barrier height becomes as high as about 1.2 eV. As a result, particularly in the ohmic connection between the base contact region 71 and the base electrode (Ni ₂ Si) 73, the contact resistance becomes extremely high at ¹ × 10 ⁻² Ωcm ² or more, and a Schottky-like characteristic is exhibited.

<Electrical Characteristics of Bipolar Transistor> The results of evaluating the electrical characteristics of the bipolar transistor manufactured by the above manufacturing method are as follows. Collector-emitter blocking voltage (BV
_CEO ) was about 1000V. Further, when the forward current density is 100 A / cm ² , the forward ON voltage is 1.
It was 3 V, and the on-resistance was a very low value of 7 mΩ · cm ² .

On the other hand, the bipolar transistor using the Ni ₂ Si ohmic contact according to the related art has a very high contact resistance of 1 × 10 ⁻² Ωcm ² or more, and exhibits Schottky-like characteristics. Therefore, even if a forward voltage is applied to the pn junction between the base and the emitter, the electric field is retained at the base electrode interface,
Since no voltage is applied to the pn junction itself, a satisfactory ON operation cannot be performed.

Therefore, according to the bipolar transistor of the fifth embodiment, by using the NiSi ₂ film for the emitter electrode 74, the base electrode 73 and the depletion layer limiting electrode 55, the bipolar transistor has a breakdown voltage close to the theoretical value. It is possible to obtain the above, and at the same time, the excellent physical properties of SiC can be brought out to realize a low on-voltage and an on-resistance. Further, the electric field is not retained at the connection interface between the base electrode 73 and the base contact region 71, and the gate voltage is applied to the pn junction itself between the base and the emitter,
Satisfactory off operation can be performed at high speed. Therefore, the switching speed of the device is improved. Here, the case where Ni is used as the electrode material of the refractory metal is shown as an example, but other materials such as Ti, V, Cr, Ni, Zr, and N are used.
When b, Mo, Hf, Ta, and W are used, the emitter electrode 74, the base electrode 73, and the depletion layer limiting electrode 55 having the disilicide structure can be formed by the same method, and similar results can be obtained. .

As described above, according to the first to fifth embodiments of the present invention, after depositing the Si film and the refractory metal film on the SiC substrate 14, the Si film and the refractory metal film are deposited in vacuum or in an inert gas.
By performing heat treatment in the range of 0 to 1100 ° C. to form metal disilicide, the barrier height is 0.65 eV or less in the Schottky contact and the contact resistance is 1 × 10 5 in the ohmic contact.
^It can be reduced to ⁻⁶ Ωcm ² or less. As a result, the forward ON voltage can be effectively lowered without impairing the reverse characteristics such as breakdown voltage and leakage current in the JBS diode, Schottky diode, static induction transistor, and bipolar transistor.

(Other Embodiments) As described above, the present invention has been described by the first to fifth embodiments, but the description and drawings forming a part of this disclosure limit the present invention. Should not be understood. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

When Ni (nickel) is used as the refractory metal in the first, second, fourth and fifth embodiments, and Co (cobalt) is used in the third embodiment. I explained. However, the refractory metals applicable in the present invention are not limited to these. Instead of Ni (nickel) or Co (cobalt), titanium (Ti), vanadium (V), chromium (C
r), zirconium (Zr), niobium (Nb), molybdenum (Mo), hafnium (Hf), tantalum (T
a), tungsten (W), etc. can be used. Further, in the first to fifth embodiments, the silicide film is the disilicide film having the MSi ₂ structure of the refractory metal element M. However, the present invention is not limited to this, and may be another silicide film having an MSi _X structure (X is a natural number of 3 or more), or M
It may be a silicide film having a Si structure.

Further, in the first to third embodiments, in order to form the refractory metal silicide film, Si is used.
The case where the two-layer laminated structure of the film and the refractory metal film (Ni film, Co film) is used is shown, but the present invention is not limited to this. In order to further promote the silicidation reaction, the thin film structure of the Si film and the refractory metal film may be stacked a plurality of times repeatedly, and the same action result can be obtained. Further, instead of the laminated film, an alloy film of Si and a refractory metal may be formed at once. The alloy film of Si and Ni may be formed by simultaneously sputtering a Si target and a Ni target in the same chamber. However, whether a laminated film or an alloy film is used,
In order to form the MSi ₂ structure (disilicide structure), the stoichiometric composition ratio between the refractory metal and Si is approximately 1:
It is important to set it to 2.

Furthermore, in the first to fifth embodiments, the anode electrode 7a and the depletion layer limiting electrode 7 shown in FIG.
b, the anode electrodes (21, 22) shown in FIG. 5, the gart ring electrode 23, the depletion layer limiting electrode 7b, the source electrode 34, the gate electrode 33, the depletion layer limiting electrode 7b shown in FIG.
The source electrode 54, the gate electrode 53, the depletion layer limiting electrode 55 shown in FIG. 12, the emitter electrode 74, the base electrode 73, and the depletion layer limiting electrode 55 shown in FIG. 15 are entirely made of a refractory metal silicide film. The case is shown below. However, the present invention is not limited to this. Of the above electrodes, only the portion that makes Schottky or ohmic contact with SiC is composed of a silicide film of a refractory metal, and the above electrodes are not limited to the silicide film, but other conductive materials formed on the silicide film. You may further have the electrode film which consists of. The depletion layer limiting electrode (7
For b and 55), the silicide film of refractory metal need not be arranged in the ohmic contact portion. That is, the depletion layer limiting electrodes (7b, 55) may be composed only of another conductive film such as an aluminum film instead of the refractory metal silicide film.

Furthermore, as an example of the junction termination structure for increasing the breakdown voltage of the device, in the first to fifth embodiments, the guard rings (8, 43, 58), the junction termination extension (JTE) are used. )
Although the structure 78 is shown and the guard ring electrode 23 is shown in the second embodiment, the present invention is not limited thereto. Instead of the guard ring 8, the JTE structure 78 or the guard ring electrode 23, another structure such as a field limiting ring (FLR) or a field plate (FP) may be used.

Further, in the first to fifth embodiments, the one-step heat treatment process is used for forming the disilicide film, but the present invention is not limited to this. For example, it is also effective to use a two-step heat treatment process at around 500 ° C. and around 900 ° C. In this case, the uniformity of the disilicide film is further improved, and as a result, the barrier height value of the Schottky contact is made uniform.

Furthermore, in each of the first to fifth embodiments, the structure of the single type semiconductor device is shown, but the present invention can be applied to the multi type semiconductor device.
For example, in the static induction transistor and the trench type static induction transistor shown in FIGS. 8 and 12, one source region 32 is provided between the two gate regions 31 and 51.
Not only the configuration (single type) in which 52 is arranged,
A plurality of gate regions 31, 51 and source regions 32, 52
It may be a configuration (multi-type) in which are alternately arranged. In the bipolar transistor shown in FIG. 15, not only a structure in which one emitter layer 72 is arranged on one base layer 79 (single type) but also a plurality of emitter layers 72 are formed on one base layer 79. Placed,
The base contact region 7 is formed between the adjacent emitter layers 72.
1 may be arranged (multi-type).

The present invention is based on the JBS diode shown here,
The invention is not limited to the Schottky diode, the static induction transistor, the bipolar transistor, or the like, and can be applied to other semiconductor devices. That is, various modifications can be made without departing from the scope of the present invention.

As described above, it should be understood that the present invention includes various embodiments and the like not described here. Therefore, the present invention is limited only by the matters specifying the invention according to the scope of claims appropriate from this disclosure.

[0158]

As described above, according to the present invention,
It is possible to provide a semiconductor device that can effectively reduce the on-voltage in the forward direction without impairing the reverse characteristics such as withstand voltage and leakage current, and a manufacturing method thereof.

[Brief description of drawings]

FIG. 1 is a sectional view showing a configuration of a JBS diode according to a first embodiment of the present invention.

FIG. 2 is a top view showing a planar shape (square shape) of each semiconductor region in the JBS diode shown in FIG.

3A to 3C are process cross-sectional views showing a main manufacturing process for manufacturing the JBS diode shown in FIGS. 1 and 2 (No. 1).

FIGS. 4A to 4C are process cross-sectional views showing the main manufacturing processes for manufacturing the JBS diode shown in FIGS. 1 and 2 (No. 2).

FIG. 5 is a sectional view showing a configuration of a Schottky diode according to a second embodiment of the present invention.

6A to 6C are process cross-sectional views showing the main manufacturing process for manufacturing the Schottky diode shown in FIG. 5 (No. 1).

7A to 7C are process cross-sectional views showing the main manufacturing processes for manufacturing the Schottky diode shown in FIG. 5 (No. 2).

FIG. 8 is a sectional view showing a configuration of a static induction transistor according to a third embodiment of the present invention.

9A to 9C are process cross-sectional views showing the main manufacturing processes for manufacturing the static induction transistor shown in FIG. 8 (No. 1).

10 (a) and 10 (c) are process cross-sectional views showing the main manufacturing process for manufacturing the static induction transistor shown in FIG. 8 (No. 2).

11 is a top view showing a planar shape (striped shape) of each semiconductor region in the JBS diode shown in FIG. 1. FIG.

FIG. 12 is a sectional view showing a configuration of a trench type static induction transistor according to a fourth embodiment of the present invention.

13A to 13C are process cross-sectional views showing a main manufacturing process for manufacturing the trench static induction transistor shown in FIG. 12 (No. 1).

14A and 14C are process cross-sectional views showing the main manufacturing processes for manufacturing the trench static induction transistor shown in FIG. 12 (No. 2).

FIG. 15 is a sectional view showing a structure of a bipolar transistor according to a fifth embodiment of the present invention.

16A to 16C are process cross-sectional views showing the main manufacturing process for manufacturing the bipolar transistor shown in FIG. 15 (No. 1).

17A and 17C are process cross-sectional views showing the main manufacturing processes for manufacturing the bipolar transistor shown in FIG. 15 (No. 2).

[Explanation of symbols]

1 n-type low-resistance substrate 2 n-type high-resistance layer 3 p-type low-resistance region 4 depletion layer limiting region 5 cathode electrode 6, 37 insulating film 7a anode electrode 7b, 55 depletion layer limiting electrode 8, 58 guard ring 10, 11, 38-40, 60, 62, 64, 81, 8
2 mask 12, 24, 41, 65, 83 Si film 13, 25, 66, 84 Ni film 14 SiC substrate 21 second anode electrode 22 first anode electrode 23 guard ring electrode 31, 51 gate region 32, 52 source region 33 , 53 gate electrode 34, 54 source electrode 36, 56 drain electrode 42 Co film 43, 78 junction termination region 57a first insulating film 57b second insulating film 59 recessed portion 61 n ⁺ region 63 bottom surface 71 base contact region 72 emitter layer 73 Base Electrode 74 Emitter Electrode 76 Collector Electrode 77a First Sidewall Insulation Film 77b Second Sidewall Insulation Film 79 Base Layer 80 Collector Layer

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Tetsuo Hatakeyama             1st Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa             Inside the Toshiba Research and Development Center F-term (reference) 4M104 AA03 BB20 BB21 BB24 BB25                       BB26 BB27 BB28 CC01 CC03                       DD34 DD37 DD84 FF35 GG03                       GG06 GG12                 5F003 BA92 BA93 BB02 BE02 BH07                       BH99 BM01 BP33 BP42 BP93                 5F102 FA01 FA03 FB01 GB04 GC07                       GC09 GD04 GJ02 GL02 GR07                       HC01 HC07 HC11 HC16 HC21

Claims (16)

[Claims] 1. A silicon carbide substrate having a first conductivity type and high resistance, a second conductivity type region formed on the silicon carbide substrate, and an outer region of the second conductivity type region on the silicon carbide substrate. A second conductivity type junction termination region formed, a first conductivity type low resistance depletion layer limiting region formed outside the junction termination region in an upper portion of the silicon carbide substrate, the second conductivity type region, and Connected to the junction termination region,
And an anode electrode having a refractory metal silicide film disposed at least at a Schottky connection interface, which is Schottky connected to the upper surface of the silicon carbide substrate exposed inside the junction termination region, and the depletion layer restriction region. A semiconductor device, comprising: a depletion layer limiting electrode ohmic-connected to and a cathode electrode ohmic-connected to the lower surface of the silicon carbide substrate. 2. The semiconductor device according to claim 1, wherein the silicide film is a disilicide film having an MSi ₂ structure, where M is the refractory metal. 3. The semiconductor device according to claim 1, wherein the depletion layer limiting electrode has the same film structure as the anode electrode. 4. A step of preparing a silicon carbide substrate having a first conductivity type and a high resistance, and a step of selectively diffusing a second conductivity type impurity in an upper portion of the silicon carbide substrate to form a second conductivity type region. And a step of selectively diffusing a second conductivity type impurity in an upper portion of the silicon carbide substrate to form a junction termination region outside the second electrode region, and selectively forming a junction termination region in the upper portion of the silicon carbide substrate. A step of diffusing a 1-conductivity type impurity at a high concentration to form a depletion layer limiting region outside the junction termination region; On the upper surface of the silicon carbide substrate that has been taken out,
A step of forming a silicon film, a step of forming a refractory metal film on the silicon film so that a stoichiometric composition ratio is 1: 2 (= refractory metal: silicon), and a predetermined heat treatment And a step of forming a silicide film to be an anode electrode from a silicidation reaction between the silicon film and the refractory metal film; and a step of forming a depletion layer limiting electrode that makes ohmic contact with the depletion layer limiting region, And a step of forming a cathode electrode in ohmic contact with the lower surface of the silicon carbide substrate. 5. The method of manufacturing a semiconductor device according to claim 4, wherein the predetermined heat treatment is a heat treatment at a temperature of 600 to 1100 ° C. in a vacuum or an inert gas atmosphere. 6. The method of manufacturing a semiconductor device according to claim 4, wherein the depletion layer limiting electrode is formed simultaneously with the anode electrode in the step of forming the anode electrode. 7. A silicon carbide substrate having a first conductivity type and a high resistance, a first anode electrode embedded in an upper portion of the silicon carbide substrate and Schottky-connected to an upper surface of the silicon carbide substrate, and a silicon carbide substrate of the silicon carbide substrate. A second conductivity type junction termination region formed outside the first anode electrode at an upper portion, a junction termination electrode connected to the junction termination region, and the silicon carbide substrate exposed inside the junction termination region. A second anode electrode having a refractory metal silicide film disposed at least at a Schottky connection interface, the second anode electrode being Schottky connected to the upper surface of the silicon carbide and being connected to the first anode electrode and the junction termination electrode. A first conductivity type low resistance depletion layer limiting region formed outside the junction termination region in the upper portion of the substrate, and a depletion ohmic-connected to the depletion layer limiting region. A layer limiting electrode and a cathode electrode ohmic-connected to the lower surface of the silicon carbide substrate, and a barrier height of the silicon carbide substrate at a Schottky connection interface with the first anode electrode is different from that of the second anode electrode. A semiconductor device having a height higher than a barrier height of the silicon carbide substrate at a Schottky connection interface. 8. The semiconductor device according to claim 7, wherein the silicide film is a disilicide film having an MSi ₂ structure, where M is the refractory metal. 9. The semiconductor device according to claim 7, wherein the depletion layer limiting electrode has the same film structure as the second anode electrode. 10. A step of preparing a silicon carbide substrate having a first conductivity type and a high resistance, and a step of selectively diffusing a second conductivity type impurity in an upper portion of the silicon carbide substrate to form a junction termination region, A step of selectively diffusing a first conductivity type impurity at a high concentration in an upper portion of the silicon carbide substrate to form a depletion layer limiting region outside the junction termination region; and exposing the inside of the junction termination region. A step of selectively forming a silicon film on the upper surface of the silicon carbide substrate; and a refractory metal on the silicon film, the junction termination region, and the upper surface of the silicon carbide substrate exposed inside the junction termination region. The film has a stoichiometric composition ratio of 1: 2 (= refractory metal:
Silicon) and a predetermined heat treatment to form a first anode electrode and a junction termination electrode from a silicide reaction between the silicon carbide substrate and the junction termination region and the refractory metal film. And forming a second silicide film to be a second anode electrode from a silicide reaction between the silicon film and the refractory metal film, and a depletion layer ohmic-connected to the depletion layer restriction region. A method of manufacturing a semiconductor device, comprising: a step of forming a limiting electrode; and a step of forming a cathode electrode that makes ohmic contact with a lower surface of the silicon carbide substrate. 11. The method of manufacturing a semiconductor device according to claim 10, wherein the predetermined heat treatment is a heat treatment at a temperature of 600 to 1100 ° C. in a vacuum or an inert gas atmosphere. 12. The method of manufacturing a semiconductor device according to claim 10, wherein the depletion layer limiting electrode is formed simultaneously with the second anode electrode in the step of forming the second anode electrode. . 13. A first-conductivity-type high-resistance silicon carbide substrate, a first-conductivity-type low-resistance source region formed on the silicon carbide substrate, and an upper part of the silicon carbide substrate outside the source region. A second conductivity type gate region formed on the silicon carbide substrate, a second conductivity type junction termination region formed outside the gate region on the silicon carbide substrate, and a junction termination region on the silicon carbide substrate. A first-conductivity-type low-resistance depletion layer confined region formed on the outer side of the source region, a source electrode ohmic-connected to the source region, and having a refractory metal silicide film disposed at least at an ohmic contact interface; A gate electrode ohmic-connected to the region, the gate electrode having a silicide film of a refractory metal disposed at least at the ohmic-connection interface; And Mikku connected depletion limiting electrode, wherein a and a drain electrode which is ohmic connected to the lower surface of the silicon carbide substrate. 14. A step of preparing a silicon carbide substrate having a first conductivity type and high resistance, and a step of selectively diffusing a first conductivity type impurity in a high concentration on the silicon carbide substrate to form a source region. And a step of selectively diffusing a second conductivity type impurity in an upper portion of the silicon carbide substrate to form a gate region outside the source region, and a second conductivity type in an upper portion of the silicon carbide substrate. Diffusing impurities to form a junction termination region outside the gate region; and selectively diffusing the first conductivity type impurity in a high concentration on the silicon carbide substrate to outside the junction termination region. A step of forming a depletion layer confined region in, a step of forming a silicon film on the source region and the gate region, a refractory metal film on the silicon film, and a stoichiometric composition ratio of 1: 2 (= refractory metal: silicon ), A predetermined heat treatment is performed to generate a silicide film to be a source electrode and a gate electrode from a silicide reaction between the silicon film and the refractory metal film, and the depletion layer A method of manufacturing a semiconductor device, comprising: a step of forming a depletion layer limiting electrode that makes ohmic contact with a limited region; and a step of forming a drain electrode that makes ohmic contact on a lower surface of the silicon carbide substrate. 15. A first-conductivity-type high-resistance silicon carbide substrate, a first-conductivity-type low-resistance source region formed on the silicon carbide substrate, and above the silicon carbide substrate and outside the source region. A concave portion of the silicon carbide substrate formed on the substrate, a second conductivity type gate region formed on a bottom surface of the concave portion, and a second conductivity type gate region formed on the silicon carbide substrate outside the gate region. A junction termination region, a first conductivity type low resistance depletion layer limiting region formed outside the junction termination region in an upper portion of the silicon carbide substrate, and arranged at least at an ohmic connection interface ohmic-connected to the source region. And a source electrode having a refractory metal silicide film formed thereon and a refractory metal silicide layer ohmic-connected to the gate region and disposed at least at an ohmic contact interface. A gate electrode having a side film, a depletion layer limiting electrode that is ohmic-connected to the depletion layer limiting region, and a drain electrode that is ohmic-connected to the lower surface of the silicon carbide substrate, and the silicide film has the high melting point. If the metal is M,
A semiconductor device comprising a disilicide film having an MSi ₂ structure. 16. A step of preparing a silicon carbide substrate having a first conductivity type and a high resistance, and a step of selectively diffusing a first conductivity type impurity in a high concentration on the silicon carbide substrate to form a source region. And a step of selectively removing an upper portion of the silicon carbide substrate to form a recess outside the source region, and a step of selectively diffusing a second conductivity type impurity from a bottom surface of the recess to form a gate region. A step of selectively diffusing a second conductivity type impurity in an upper portion of the silicon carbide substrate to form a junction termination region outside the gate region, and a first selectively in an upper portion of the silicon carbide substrate. A step of diffusing a conductivity type impurity in a high concentration to form a depletion layer limiting region outside the junction termination region, and selectively forming a silicon film on the exposed source region and the gate region. Process and the silicon Forming a refractory metal film on the film so that the stoichiometric composition ratio is 1: 2 (= refractory metal: silicon); Forming a silicide film to be a source electrode and a gate electrode from a silicide reaction with the melting point metal film; forming a depletion layer limiting electrode that makes ohmic contact with the depletion layer limiting region; and forming a depletion layer limiting electrode on the lower surface of the silicon carbide substrate. And a step of forming a drain electrode for ohmic connection.