CN104464816A - One-time programmable memory, operation method and programming method thereof and electronic system - Google Patents

Abstract

An OTP memory and operating method and programming method thereof and electronic system, the OTP memory includes: a plurality of otp units, at least one otp unit comprising at least: an otp element includes at least one electrical fuse coupled to a first voltage source line; and a programming selector coupled to the one-time programmable element and a second voltage source line, wherein at least a portion of the electrical fuse has at least one extension region with reduced or no current flowing through the extension region; and wherein the one-time programmable element is programmable by applying voltages to the first and second voltage source lines and turning on the program selector, thereby changing the one-time programmable element to a different logic state. The programmable resistance element unit of the present invention will use junction diodes as an exemplary illustrative embodiment of the program selector. The programmable resistance element unit can use CMOS logic process to reduce unit size and cost.

Description

One-time programmable memory, method of operation and programming thereof, and electronic system

technical field

The invention relates to a programmable memory element, in particular to a programmable resistance element used in a memory array.

Background technique

A programmable resistive element generally means that the resistive state of the element can be changed after programming. The resistance state can be determined by the resistance value. For example, the resistive element may be a One-Time Programmable (OTP) element (such as an electrical fuse), and the programming method may apply a high voltage to generate a high current through the OTP element. When a high current flows through the OTP element by turning on the program selector, the OTP element will be programmed by firing into a high or low resistance state (depending on whether it is a fuse or an antifuse).

Electrical fuse is a common OTP, and this programmable resistance element can be connected by a segment, such as polysilicon, silicided polysilicon, silicide, metal, metal alloy or their combination. The metal can be aluminum, copper or other transition metals. The most commonly used e-fuse is a CMOS gate made of silicided polysilicon, which is used as an interconnect. Electrical fuses may also be one or more contacts or vias rather than interconnects of small segments. High current can burn the contact or layer-to-layer contact into a high resistance state. An electrical fuse can be an antifuse, where a high voltage lowers the resistance instead of increasing it. An antifuse may consist of one or more contacts or interlayer contacts with an insulator in between. The antifuse can also be coupled to the CMOS body by the CMOS gate, which contains the gate oxide as an insulator.

The programmable resistance element may be a reversible resistance element, which can be programmed repeatedly and reversibly into a digital logic value "0" or "1". Programmable resistive elements can be fabricated from phase change materials such as the composition Ge2Sb2Te5 (GST-225) of germanium (Ge), antimony (Sb), tellurium (Te) or compositions including indium (In), tin (Sn) or selenium ( Se) GeSbTe-like materials. Another type of phase change material includes chalcogenide materials such as AglnSbTe. Through short pulses of high voltage or long pulses of low voltage, phase change materials can be programmed into an amorphous high-resistance state or a crystalline low-resistance state. Another type of reversible resistive element is a type of memory called resistive random access memory (RRAM), which starts out as an insulating dielectric and can be turned on through filamentation, defects, or metal migration. The dielectric can be a transition metal oxide, such as NiO or TiO ₂ ; or a perovskite material, such as Sr(Zr)TiO ₃ or PCMO; or a charge transfer complex, such as CuTCNQ; or an organic donor-acceptor Body systems, such as Al AIDCN. RRAM memory cells are composed of metal oxides between electrodes, such as platinum/nickel oxide/platinum (Pt/NiO/Pt), titanium nitride/titanium oxide/hafnium oxide/titanium nitride (TiN/TiOx/HfO ₂ /TiN ), titanium nitride/zinc oxide/platinum (TiN/ZnO/Pt), or tungsten/titanium nitride/silicon dioxide/silicon (W/TiN/SiO ₂ /Si). The reversible change of the resistance state is via the polarity, intensity, and duration of the voltage or current pulses to create or destroy conductive filaments.

Another programmable resistive element similar to resistive random access memory (RRAM) is conductive bridge random access memory (CBRAM). The memory is based on the electrochemical deposition and removal of metal ions in a solid electrolyte film between metal or metal alloy electrodes. The electrodes can be an oxidizable anode and an inert cathode, and the electrolyte can be a silver or copper doped chalcogenide glass such as germanium selenide (GeSe) or sulfur selenide (GeS). The reversible change of the resistance state is via the polarity, intensity, and duration of the voltage or current pulses to create or destroy the conductive bridge. In addition, the programmable resistance element can also be a magnetic memory memory (MRAM), which is composed of a magnetic tunnel junction (MTJ) made of multi-layer magnetic layers. In spin transfer torque (SpinTransfer Torque, STT) MRAM, the direction of the current applied to the MTJ determines the parallel or antiparallel state, which in turn determines the low or high resistance state.

A traditional programmable resistance memory storage unit is shown in FIG. 1 . The memory cell 10 includes a resistive element 11 and an N-type metal oxide semiconductor transistor (NMOS) program selector 12 . One end of the resistance element 11 is coupled to the drain of the NMOS, and the other end is coupled to the positive voltage V+. The gate of the NMOS 12 is coupled to the selection signal SEL, and the source is coupled to the negative voltage V-. When a high voltage is applied to V+ and a low voltage is applied to V-, the NMOS 12 is turned on by raising the programming select signal SEL, and the resistive element 10 can be programmed. FIG. 2 shows another programmable resistive memory cell 20' having a programmable resistive element 21' coupled to a diode 22'. The cathode of this diode 22' can be switched to a low potential to turn on the diode 22' for programming.

Figures 3a and 3b show some embodiments of electrical fuse elements 80 and 84 fabricated from interconnects. A resistive element has three parts: the anode, the cathode, and the body. The anode and cathode provide the electrical connection of the resistive element to the rest of the circuit so that current can flow from the anode through the body to the cathode. The width of the body determines the current density and thus the electromigration threshold of the programming current. FIG. 3 a shows a conventional e-fuse element 80 comprising an anode 81 , a cathode 82 , and a body 83 . This embodiment has a large and symmetrical anode and cathode. FIG. 3 b shows another conventional e-fuse element 84 comprising an anode 85 , a cathode 86 , and a body 87 . Fuse elements 81 and 85 in FIGS. 3a and 3b are relatively large structures, which makes them unsuitable for some applications.

Contents of the invention

It is an object of the present invention to provide an exemplary embodiment of a programmable resistive element unit using a junction diode as a program selector. The programmable resistance element unit can use CMOS logic technology to reduce unit size and cost.

According to one embodiment, a programmable resistance element and a memory can use P+/N well diodes as program selectors, wherein the P and N terminals of the diodes are the P+ and N+ active regions of the N well. The P+ and N+ active regions can also be used as sources or drains of PMOS or NMOS. The same N well is preferably a PMOS well embedded in a standard CMOS logic process. By using P+/N well diodes in a standard CMOS process, the cell size can be reduced without any special process or mask. Junction diodes can be fabricated in N-well or P-well in bulk CMOS, or from isolated active regions in SOI CMOS, bulk FinFET, or SOI FinFET (or similar technologies). Therefore, the cost can be greatly reduced to benefit a variety of uses (such as embedded applications).

According to one embodiment, junction diodes can be built with standard CMOS logic processes and serve as program selectors for one-time programmable devices. The one-time programmable device can be an electrical fuse (including an interconnection, a local interconnection, a contact/interlayer contact antifuse, or a gate oxide collapse antifuse, etc.). The programmable resistive element may have a heat sink to dissipate heat or a heating element to heat, thereby assisting programming of the programmable resistive element. If the programmable resistive element is an e-fuse, the e-fuse may have an extended region to aid programming of the programmable resistive element. If the programmable resistor element is a metal fuse, at least one contact point and/or multiple interlayer contacts (one or more jumpers may be used) can be made in the programming path to generate more Joule heat and assist programming. The spans are all conductive and can be made of metal, metal gate, local interconnect, polysilicon metal. The OTP element may have at least one OTP element coupled to at least one diode in the memory array. Diodes can be fabricated with P+ and N+ active regions in an N-well of CMOS, or have isolated active regions as P and N terminals. The OTP element can be polysilicon, silicided polysilicon, metal silicide, polysilicon metal, metal, metal alloy, local interconnect, thermally isolated active region, CMOS gate, CMOS metal gate or a combination thereof.

The invention can be implemented in various embodiments, including methods, systems, components, or devices (including graphical user interfaces and computer readable media). Various embodiments of the invention are described below.

For an embodiment of a programmable resistive device (PRD) memory, it includes at least a plurality of PRD cells, at least one PRD cell includes at least one PRD element coupled to a first voltage supply line, and a program selection The device is coupled to the PRD element and a second voltage supply line. At least a portion of the PRD elements include at least one heat sink, heater, or expansion region to aid in programming. The heat sink is built inside or adjacent to the PRD element to enhance the heat dissipation effect. The heating element can be any high resistance material in the path of the current so that the temperature of the PRD element can be raised. The heating element may comprise multiple interconnections and/or multiple contact points or interlayer points as bridges. An extended region is an area within the PRD where reduced or no current flows. The PRD elements are programmable to different logic states by applying voltages to the first and second voltage supply lines.

An electronic system according to an embodiment includes at least one processor and a PRD memory operatively connected to the processor. This PRD memory contains multiple PRD cells. At least one PRD cell includes a PRD element operatively coupled to a first voltage supply line, and a program selector coupled to the PRD element and a second voltage supply line. The PRD element is operatively coupled to at least one heat sink, heating element or an expansion area to aid in programming. The heat sink is built inside or adjacent to the PRD element to enhance the heat dissipation effect. The heating element can be any high resistance material in the path of the current so that the temperature of the PRD element can be raised. The heating element may comprise multiple interconnections and/or multiple contact points or interlayer points as bridges. An extended region is an area within the PRD where reduced or no current flows. The PRD elements are programmable to different logic states by applying voltages to the first and second voltage supply lines.

According to one embodiment, the method for operating a PRD memory includes the following steps: providing a plurality of PRD cells, at least one PRD cell at least comprising: (i) a PRD element operatively coupled to a first voltage supply line; (ii) a The programming selector is coupled to the PRD element and a second voltage supply line; and (iii) the PRD element is operatively coupled to at least one heat sink, heating element or an expansion area to assist in programming. The heat sink is built inside or adjacent to the PRD element to enhance the heat dissipation effect. The heating element can be any high resistance material in the path of the current so that the temperature of the PRD element can be raised. The heating element may comprise multiple interconnections and/or multiple contact points or interlayer points as bridges. An extended region is an area within the PRD where reduced or no current flows. The PRD elements are programmable to different logic states by applying voltages to the first and second voltage supply lines.

According to one embodiment, the OTP memory includes a plurality of OTP cells. At least one OTP cell at least includes: an OTP element including at least one electrical fuse operatively coupled to a first voltage supply line; and a program selector coupled to the OTP element and a second voltage supply line. At least a portion of the electrical fuse has an expansion region through which reduced or no current flows. By applying a voltage to the first and second voltage source lines, the extended area has a reduced current flow or no current flow. The OTP element can be programmed to different logic states by applying voltages to the first and second voltage supply lines and turning on the program selector.

According to an embodiment of the present invention, an electronic system includes: at least one processor and an OTP memory operatively connected to the processor. This OTP memory contains multiple OTP units. At least one OTP cell includes an OTP element including an electrical fuse operatively coupled to a first voltage source line, and a program selector coupled to the OTP element and a second voltage source line. At least a portion of the electrical fuse includes an expansion region through which reduced or no current flows. The OTP element can be programmed to different logic states by applying voltages to the first and second voltage supply lines and turning on the program selector.

According to an embodiment of the present invention, an operating method for operating an OTP memory includes the following steps: providing a plurality of OTP units, at least one OTP unit at least comprising: (i) an OTP element comprising operatively coupled to a first voltage supply line at least one e-fuse; (ii) a programming selector coupled to the OTP element and a second voltage supply line; and (iii) at least a portion of the e-fuse includes an extension region having decremented current or no current flows; and by applying voltage to the first and second voltage supply lines and turning on the program selector, the OTP element can be programmed to different logic states at a time.

The present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments, but not as a limitation of the present invention.

Description of drawings

FIG. 1 shows a conventional programmable resistance memory cell;

Figure 2 shows another conventional programmable resistance memory cell, and uses a diode as a program selector;

Figure 3a and b respectively show examples of internal connections as electrical fuses;

Figure 4a shows a block diagram of a memory cell using a junction diode;

Fig. 4b shows the IV curve characteristics of an example electric fuse programming process;

Figure 5a shows a cross-sectional view of another embodiment of a junction diode used as a program selector and isolated by STI;

Figure 5b shows a cross-sectional view of another junction diode embodiment, which acts as a program selector and is isolated with a dummy CMOS gate;

Figure 5c shows a cross-sectional view of another embodiment of a junction diode used as a program selector and isolated by SBL;

Figure 5d shows a cross-section of another embodiment in which junction diodes are used as program selectors and isolated using dummy CMOS gates in silicon-on-insulator (SOI) technology.

Figure 6a shows a top view of a junction diode used as a program selector and isolated using a silicon-on-insulator (SOI) or similar technology dummy CMOS gate;

Fig. 6b is a top view of a programmable resistance unit, the programmable resistance unit has a resistance element and a diode as a program selector, and the diode is integrally formed in the isolation active region, and the two ends of the diode are isolated by dummy gates;

Figure 6c is a top view of a Schottky diode with STI isolation and as a program selector;

Figure 6d shows a top view of a Schottky diode with CMOS gate isolation and as a program selector according to an embodiment of the present invention;

Figure 6e shows a top view of a Schottky diode with SBL isolation and as a program selector according to an embodiment of the present invention;

Figure 6f shows a perspective view of an embodiment of a junction diode, which is a program selector using a dummy CMOS gate in FinFET technology for isolation;

FIG. 6g shows an embodiment of using PMOS as a diode (or MOS) to provide a program or read selector;

FIG. 6h shows a cross-sectional view of the cell in FIG. 6g to show a schematic diagram of a program/select path using a PMOS as a diode program selector or a MOS read selector;

FIG. 6i further shows the operation state of the programmable resistance unit shown in FIG. 6g, which uses PMOS as a diode programming/reading selector;

Figure 6j further shows the operating state of the programmable resistance unit shown in Figure 6h, which uses PMOS as a MOS programming/reading selector;

Figure 6k shows a schematic diagram of a programmable resistive element unit fabricated on a thermally isolated substrate, which uses a dummy gate of a programming selector as a PRD element;

Figure 6l shows a schematic diagram of a programmable resistive element unit fabricated on a thermally isolated substrate, the programmable resistive element unit uses the MOS gate of the programming selector as a PRD element;

Figure 7a shows a top view of an e-fuse element using a thermally conductive but electrically insulating heat sink to couple to the anode;

Figure 7b shows a top view of an e-fuse element using a thin oxide under the body and close to the anode as a heat sink;

Figure 7c shows a top view of an e-fuse element using a thin oxide region under the anode as a heat sink;

Figure 7d shows a top view of an e-fuse element using a thin oxide region near the anode as a heat sink;

Figure 7e shows a top view of an e-fuse element using an extended anode as a heat sink;

Figure 7f shows a top view of an e-fuse element using a high resistance region as a heating element;

Figure 7g shows a top view of an e-fuse element having an extension at the cathode;

Figure 7h shows a top view of an e-fuse element with an extended region at the cathode and borderless contacts at the anode;

Figure 7i shows a top view of an e-fuse element having an extension at the cathode and a common contact at the anode;

Figure 7j shows a top view of an electrical fuse element having at least one notch;

FIG. 7k shows a top view of an electrical fuse element having a portion of an NMOS metal gate and a portion of a PMOS metal gate;

Figure 8a shows a top view according to an e-fuse unit having a P+/N well diode and an adjoining connection contact;

Figure 8b shows a top view of a programmable resistor unit coupled to a junction diode with a dummy CMOS gate for isolation of P+ and N+;

Figure 9 is an example processor system.

Detailed ways

Below in conjunction with accompanying drawing, structural principle and working principle of the present invention are specifically described:

Embodiments of the present invention relate to programmable resistive elements using P+/N well junction diodes as program selectors. The diode can include P+ and N+ active regions in an N-well region. The P+ and N+ active regions in the N-well region can be easily manufactured by standard CMOS technology, and the programmable resistance element of the present invention can be manufactured effectively and reduce the cost. For standard SOI, FinFET or similar technologies, the isolated active region can be fabricated as a program selector diode or as a programmable resistor element. The programmable resistance element can also be included in an electronic system.

In one or more embodiments, the junction diode can be fabricated in a standard CMOS process and used as a one-time programmable (One-Time Programmable, OTP) element, such as an electrical fuse (including an interconnect fuse, a local Program selector for local interconnect fuse, contact/via fuse, contact/via antifuse, or gate oxide collapse antifuse). A programmable resistive device (PRD) may include heat sinks, heating elements, or expansion areas to aid in programming. The heat sink includes at least one conductor adjacent to or within the PRD element to dissipate heat. The heating element may comprise a high resistance material in the current path to generate heat. Interconnects, partial interconnects, silicon, polysilicon, metals, conductors, single or multiple contacts, or vias can be used as heating elements. The extended region is the region in the PRD element where no current will flow or a reduced current will flow. If the electrical fuse is a metal fuse, at least one contact point and/or multiple vias (multiple jumpers can be used) can be made in the programming path to generate heat through the Joule effect for programming. Jumpers are conductive and can be formed of metal, metal gates, interconnects, or local interconnects. In the memory cell, the OTP element includes at least one OTP element coupled to at least one diode. Diodes can be fabricated from P+ and N+ active regions in CMOS wells, or in isolated active regions (as diode P/N terminals). The OTP element can be polysilicon, silicided polysilicon, metal silicide, polysilicon metal, metal, metal alloy, local interconnect, thermally isolated active region, CMOS gate or a combination thereof.

Embodiments of the present invention will be described below with reference to the accompanying drawings, but those skilled in the art should understand that the scope of this case is not limited to the illustrated embodiments.

Figure 4a shows a block diagram of a memory cell 30 using a junction diode. The memory unit 30 includes a resistance element 30a and a junction diode 30b. The resistance element 30a is coupled to the anode of the junction diode 30b and the high voltage V+; the cathode of the diode 30b is coupled to the low voltage V−. According to one embodiment, the memory unit 30 is a fuse unit having a resistive element 30a as an electrical fuse. The junction diode 30b is used as a program selector, which can be made of a P+/N well in a standard CMOS process, using a P-type substrate, or in an isolated active area of SOI, or using FinFET technology. The P+ and N+ active regions as the anode and cathode are the source and drain of the CMOS element. The N well is the CMOS well embedded in the PMOS element; moreover, the junction diode can also be made of N+/P well or CMOS process using N-type substrate. The positions of the resistor element 30a and the junction diode 30b are also interchangeable between the voltage sources V+ and V−. Apply an appropriate voltage between the voltage sources V+ and V- at an appropriate time, and the resistance element 30a can be programmed into a high resistance or a low resistance state according to the voltage and time, so that the memory unit 30 can be programmed to store data (such as a bit of data) ). The P+ and N+ active regions of the diode can be isolated using dummy CMOS gates, shallow trench isolation (STI), local oxidation (LOCOS), or silicide barrier layers (SBL).

FIG. 4b shows an IV characteristic curve of an example e-fuse programming process. The IV curve shows that the electrical fuse is applied with a voltage source as the X-axis parameter, and the corresponding response current is the Y-axis parameter. When the current is very low, the slope of the curve is the inverse of the initial resistance. As the current increases, the resistance increases due to Joule heating; assuming the temperature coefficient is positive, you can see that the curve starts to bend towards the x-axis. When the critical current (Icrit) is exceeded, the resistance of the electronic fuse begins to change sharply or even become negative due to rupture, decomposition or melting. The traditional method of programming an e-fuse operates at a current higher than Icrit, and its physical mode is like an explosion, so the resulting resistance is completely unpredictable. On the other hand, assuming that the operating current is lower than Icrit, the writing mechanism is only electromigration. Due to electromigration, the write behavior becomes controllable and deterministic. The electrical fuse can be programmed by receiving pulses multiple times, and the resistance is gradually changed with the application of pulses until the required high resistance value can be achieved and detected. The electrical fuse programmed according to the above method has a 100% yield rate after programming, and the yield rate can be determined by manufacturing defects before programming. The IV characteristic curve shown in FIG. 4b can also be used for an OTP unit having at least one OTP element and a selector. Furthermore, the programming status (whether programmed or not) of the electrical fuse programmed by the above method cannot be seen by an optical microscope or a scanning electron microscope (SEM).

The present invention provides a reliable method of programming an e-fuse comprising the steps of: (a) using a low programming voltage to initially program a portion of an OTP memory, gradually increasing the programming voltage until all OTP cells can be programmed and read Confirm, this voltage is marked as the programming voltage lower limit; (b) continue to increase the programming voltage to program the same part of the OTP cell until at least one OTP cell (regardless of whether it has been programmed or not) has failed to read the confirmation, and this voltage is marked as Program voltage upper limit. In addition, the programming time can be adjusted to repeat the above steps (a) and (b) until the lower limit, the upper limit or a programming interval (the voltage range between the upper limit and the lower limit) meets a standard value. A reliable programming range for e-fuse is shown in Fig. 4b. After defining the programming interval, other OTP cells can be programmed at voltages between the lower limit and the upper limit, and in a cell voltage or current pulse manner.

The present invention provides a cell current measurement method, comprising the following steps: (a) in programming mode, apply a voltage to a programming pin VDDP, the voltage is low enough to not program the OTP cell; (b) prevent VDDP from providing current to An OTP circuit that is not an OTP memory array; (c) turn on (turn on) the selector of the OTP unit to be measured; (d) measure the current flowing through VDDP as the unit current of the selected OTP unit. This method can be applied to programmed or unprogrammed OTP cells. This method can also be used as a criterion for judging whether an OTP cell is programmed, as long as the programmed maximum cell current and the unprogrammed minimum cell current are set to determine the upper and lower limits of the programming voltage when defining characteristics.

An e-fuse unit serves as an example to illustrate key implementation concepts. Figure 5a shows a cross-section of diode 32, using a shallow trench isolated P+/N well diode as a program selector in a programmable resistive element. The P+ active region 33 and the N+ active region 37 respectively constituting the P and N terminals of the diode 32 are the source or drain of the PMOS and NMOS in the standard CMOS logic process. N+ active region 37 is coupled to N-well 34 embedded in PMOS in a standard CMOS logic process. Shallow trench isolation 36 isolates the active areas of the different components. A resistive element (not shown in FIG. 5a ), such as an electrical fuse, may be coupled at one end to the P+ active region 33 and at the other end to the high voltage supply V+. To program this programmable resistive element, a high voltage is applied to V+ and a low voltage or ground potential is applied to the N+ active region 37 . Thus, a high current passes through the fuse element and diode 32 to program the resistive element.

Figure 5b shows a cross-sectional view of another embodiment of junction diode 32', which acts as a program selector and is isolated by a dummy CMOS gate 39'. Shallow trench isolation 36' provides isolation from other active regions. The active region 31' is defined by shallow trench isolation 36'. The N+ and P+ active regions 37' and 33' here are further defined by the mixture of the dummy CMOS gate 39', the P+ implant layer 38' and the N+ implant layer (complementary to the P+ implant layer 38') to form a diode 32' N and P termini. The dummy MOS gate 39' is a CMOS gate fabricated in a standard CMOS process. The width of the dummy MOS gate 39' can be chosen to be the minimum width of a CMOS gate, and can be less than twice the width. The dummy MOS gate 39' may also have a thicker gate oxide layer for the I/O transistors. The diode 32' is fabricated as a PMOS-like element and includes 37', 39', 33' and 34' as source, gate, drain and N-well; however, the source 37' is covered with N+ implants layer, instead of the P+ implant layer 38' covered by the real PMOS. The dummy MOS gate 39' is preferably biased at a fixed voltage, or coupled to the N+ active region 37', and its purpose is to serve as a gap between the P+ active region 33' and the N+ active region 37' during fabrication. isolation. The N+ active region 37' is coupled to the N-well 34', which is embedded in the body of the PMOS in standard CMOS logic processes. The P base 35' is a base of P-type silicon. A resistive element (not shown in FIG. 5b ), such as an electrical fuse, may be coupled at one end to P+ region 33' and at the other end to a high voltage supply V+. To program this programmable resistive element, a high voltage is applied to V+, while a low voltage or ground is applied to the N+ active region 37'. Therefore, a high current flows through the fuse element and diode 32' to program the resistive element. This embodiment has relatively small size and low resistance.

Figure 5c shows a cross-section of another embodiment in which the junction diode 32" is isolated by a silicide barrier layer (SBL) 39" and acts as a program selector. Figure 5c is similar to Figure 5b, however the dummy CMOS gate 39' in Figure 5b is replaced by a silicide barrier layer 39" in Figure 5c to prevent silicide growth on top of the active region 31". If there is no dummy CMOS gate or silicide barrier layer, the N+ and P+ active regions will be short-circuited by the metal silicide on the surface of the active region 31″.

Figure 5d shows a cross-section of another embodiment, wherein the junction diode 32" is used as a program selector and adopts silicon-on-insulator (SOI), FinFET or other similar technologies. In SOI technology, the substrate 35" is as An insulator of silicon dioxide or similar material with a thin silicon well grown on top. All NMOS and PMOS are in silicon wells, separated from each other and the substrate 35" by silicon dioxide or similar material. An active region 31" is via dummy CMOS gate 39", P+ implanted layer 38" and N+ implanted layer ( The mixture of P+ implanted layer 38" is divided into N+ active region 37", P+ active region 33" and body 34". This N+ active area 37 " and P+ active area 33 " constitute the N end and the P end of junction diode 32 " respectively. N+ active area 37 " and P+ active area 33 " can respectively be with the source of NMOS and PMOS in the standard CMOS logic process The electrode or the drain is the same. Likewise, the dummy CMOS gate 39" can be the same as the CMOS gate constructed in a standard CMOS process. The dummy MOS gate 39" can be biased at a fixed voltage, and its purpose is to serve as isolation between the P+ active region 33" and the N+ active region 37" during fabrication. The width of the dummy MOS gate 39" can be varied , but according to an embodiment may be close to the minimum gate width of a CMOS gate, and may be less than twice the minimum gate width. The dummy MOS gate 39" may also have a thicker gate oxide to withstand higher voltages. The N+ active region 37" is coupled to the low voltage V-. A resistive element (not shown in FIG. 5d), such as an electrical fuse, can be coupled at one end to the P+ active region 33" and at the other end to the high voltage supply V+. In order to program this electrical fuse memory cell, the high and The low voltage is applied to V+ and V- respectively, and the conduction current flows through the fuse element and junction diode 32 ″ to program the resistance element. Other embodiments of CMOS isolation technology, such as shallow trench isolation (STI), dummy CMOS gate, or silicide barrier layer (SBL) can be on one to four sides or any side, which can be easily applied to the corresponding CMOS SOI technology.

FIG. 6a shows a top view of a junction diode 832, which corresponds to the cross-sectional view of FIG. 5d. The junction diode 832 is used as a program selector and is fabricated with a self-isolated active region using silicon-on-insulator (SOI), FinFET, or other similar technologies. The active region 831 is divided into an N+ active region 837, a P+ active region 833 and a body (in the dummy CMOS gate 839).

Figure 6b is a top view of a fuse element 932 made of a fuse element 931-2, a diode 931-1 and a contact region 931-3; the diode 931-1 acts as a program selector and Formed in one piece in the isolated active area. The active regions 931 - 1 , 931 - 2 , and 931 - 3 are isolated active regions constructed on the same structure as the diode, fuse elements and contact regions of the fuse element 932 . The isolated active region 931-1 is divided into regions 933 and 937 by a dummy CMOS gate 939, and these regions are respectively covered by a P+ implant layer 938 and an N+ implant layer (complementary to the P+ implant layer 938) to serve as a diode 931-1 The P-terminal and N-terminal. P+ region 933 is coupled to fuse element 931-2, which is further connected to contact region 931-3. The contact region 931-3 and the cathode contact of the diode 931-1 can be coupled to the V+ and V- power lines via one or more contacts.

If high and low voltages are applied at V+ and V- respectively, a current flows through the fuse element 931-2 to program it to a high resistance state. According to an embodiment, the fuse elements 931-2 can all be N-type or P-type. According to another embodiment, half of the fuse element 931-2 may be P-type and half of N-type, so that the fuse element 931-2 resembles a reverse-biased diode when read. And the top metal silicide will be depleted after programming. If there is no metal silicide, the fuse element 931-2 (which is an OTP element) can be made as an N/P or P/N diode to collapse under forward or reverse bias. In this embodiment, the OTP element can be directly coupled to the diode as the program selector without any contact therebetween, thereby reducing cell area and cost.

As shown in Figures 6c-e, the diodes used as program selectors can be made of Schottky diodes in standard CMOS technology. A Schottky diode is a metal-semiconductor junction diode, rather than a junction diode generally composed of semiconductor P+ and N+ doping. Schottky diodes are very similar to junction diodes, and the anode of a Schottky diode is connected to a lightly doped N or P type by a metal, while the anode of a general junction semiconductor is connected to a heavily doped N or P type by a metal . The anode of the Schottky diode can be made of any metal, such as aluminum, copper, metal alloys, or metal suicides. The metal anode of the Schottky diode can be connected to the N+ active region in the N well or the P+ active region in the P well as the cathode. Schottky diodes can be made of bulk CMOS or SOI CMOS, planar or FinFET CMOS. Those skilled in the art know that the scope of the present invention also includes Schottky diodes of different processes.

FIG. 6c shows a top view of a Schottky diode 530 according to an embodiment of the present invention. The Schottky diode 530 is formed in an N-well (not shown) and has an active region 531 (cathode) and an active region 532 (anode). The active region 531 is covered by an N+ implant layer 533 and has a contact point 535 for external connection. The active region 532 is not covered by the N+ or P+ implant layer, so that its doping concentration is substantially the same as that of the N well. The active region 532 has a metal silicide layer on it to create a Schottky barrier with silicon, and is further connected to a metal 538 via an anode contact 536 . A P+ implant layer 534 can cover the active region 532 to reduce leakage current.

Figure 6d shows a top view of a Schottky diode 530' according to an embodiment of the present invention. Schottky diode 530' is formed in an N-well (not shown) and has active region 531' embedded in the anode and cathode of the diode. The active region 531' is divided into a central anode and two outer cathodes by dummy gates 539'. The cathode is covered by an N+ implant layer 533' and has a contact 535' for external connection. The central anode is not covered by the N+ or P+ implant layer, so that its doping concentration is roughly the same as that of the N well. The central anode has a metal silicide layer on it to create a Schottky barrier with silicon and is further connected to metal 538' via anode contact 536'. A P+ implant layer 534' can cover part of the central anode to reduce leakage. According to other embodiments, the boundaries of the N+ implant layer 533' and the P+ implant layer 534' may fall on the cathode. Figure 6e shows a top view of a Schottky diode 530" according to an embodiment of the present invention. The Schottky diode 530" is formed in an N well (not shown) and has an active region 531" to insert the anode and cathode of the diode. Region 531" is divided by a silicide barrier layer 539" into a central anode and two outer cathodes. The cathode is covered by an N+ implant layer 533" and has a contact 535" for external connection. The central anode is not covered by an N+ or P+ implant layer cover, so that the doping concentration is substantially the same as that of the N well. There is a metal silicide layer on the central anode to create a Schottky energy barrier with silicon, and it is further connected to the metal 538" through the anode contact 536". A P+ implant layer 534" can cover the center anode to reduce leakage current.

Figure 6f shows a cross-sectional view of another embodiment of a junction diode 45, which is a program selector using fin field effect transistor (FinFET) technology. The FinFET refers to a fin-based multi-gate transistor. FinFET technology is similar to traditional CMOS, but has tall, thin islands of silicon that rise above a silicon substrate to serve as the body of the CMOS element. Its main body is like traditional CMOS, divided into source, drain and channel by polysilicon or non-aluminum metal gate. The main difference is that in FinFET technology, the body of the MOS element is lifted above the substrate, and twice the height of the island region is about the width of the channel, but the direction of current flow is still parallel to the surface of the silicon. Figure 6f shows an embodiment of FinFET technology, the silicon substrate 35 is an epitaxial layer built on top of an insulating layer like SOI or other high resistance silicon substrate. The silicon base 35 can be etched into several tall rectangular island-like regions 31-1, 31-2 and 31-3. With proper gate oxide growth, the island regions 31-1, 31-2 and 31-3 can cover both sides of the raised island regions with MOS gates 39-1, 39-2 and 39-3, respectively. and define the source and drain regions. The source and drain regions are formed in the island regions 31-1, 31-2 and 31-3, and then filled with silicon/silicon germanium to form extended source/drain regions 40-1, 40-2, allowing the merged The source and drain areas are large enough to place contacts. The extended source/drain regions 40-1, 40-2 can be made of polysilicon, polysilicon/silicon germanium, lateral epitaxial silicon germanium, or selective epitaxial growth (SEG) silicon/silicon germanium. Extended source/drain regions 40-1, 40-2 or other isolated active regions can be grown or deposited next to or at the end of the island. In FIG. 6f, the filling regions extending the source/drain regions 40-1, 40-2 are only used to illustrate and reveal the cross-section, for example, the filling regions can be filled to the island regions 31-1, 31-2 and 31- 3 at the top. In this embodiment, active regions 33-1, 2, 3 and 37-1, 2, 3 are respectively covered by P+ implant layer 38' and N+ implant layer (complementary to P+ implant layer 38') to form a junction The P and N terminals of the diode 45 are not entirely covered by the P+ implant layer 38 ′ like the PMOS of a conventional FinFET. The N+ active regions 37-1, 2, 3 are coupled to the low voltage supply V-. Resistive elements (not shown in Figure 6f), such as electrical fuses, are coupled to the P+ active region 33-1,2,3 at one end and to the high voltage supply V+ at the other end. To program the e-fuse, high and low voltages are applied to V+ and V-, respectively, to conduct current to flow through the resistive element and the junction diode 45, thereby programming the resistive element. Other embodiments of CMOS body technology isolation, such as shallow trench isolation (STI), dummy CMOS gate or silicide barrier layer (SBL), can be easily applied to the corresponding FinFET technology.

Figure 5d and Figure 6a, bf show schematic diagrams for fabricating diodes (as program selectors) or OTP elements in fully or partially isolated active regions, respectively. The diode as a program selector can be made of isolated active regions such as SOI or FINFET. Isolating the active region can make a diode with P+ and N+ implants (as the two terminals of the diode) at both ends, which are the same as the source/drain implants of CMOS components. A dummy CMOS gate or a silicide barrier layer (SBL) can be used to isolate and avoid short circuits between the two terminals. In SBL isolation, the SBL layer can overlap the N+ and P+ implanted regions, and the N+ and P+ implanted regions are separated from each other. The breakdown voltage and leakage current of the diode can be adjusted by adjusting the width of the gap and the doping level. Fuses as OTP elements can also be fabricated by isolating the active area. Because the OTP is thermally isolated, the heat generated during programming is difficult to remove, which can be beneficial to increase the temperature to speed up programming. OTP elements can be fully N+ or P+ implanted. If there is a metal silicide on the top of the active area, the OTP element can have part of N+ implantation and part of N+ implantation, so that the OTP element is like a reverse biased diode when reading. And the top metal silicide will be depleted after programming. If there is no metal silicide, the OTP element can have a partial N+ implant and a partial N+ implant, making the OTP element resemble a diode that will collapse when read. In both cases, the OTP elements or diodes can be fabricated in the same structure that isolates the active area to save area. In SOI or FinFET SOI technology, the active area can be isolated from the substrate and other active areas by silicon dioxide or similar materials. Likewise, in FINFET body technology, active regions fabricated on the same silicon substrate with fin structures are surface-isolated from each other, and these active regions can be coupled to each other by extended source/drain regions.

FIG. 6g shows an embodiment in which PMOS is used as a diode (or MOS) to provide a program or read selector. The programmable resistance element unit 170 has a programmable resistance element 171 coupled to a PMOS 177. The gate of this PMOS 177 is coupled to a read word bar (WLRB), the drain is coupled to a program word bar (WLPB), the source is coupled to the programmable resistive element 171, and the body is coupled to the drain . The source junction configuration of PMOS 177 allows the PMOS 177 to operate like a diode when programming selected cells. And the source junction or channel structure of PMOS 177 can make this PMOS 177 operate like a diode or a MOS selector when reading operations.

FIG. 6h shows a cross-sectional view of the cell in FIG. 6g to show a schematic diagram of a program/select path using a PMOS as a diode program selector or a MOS read selector. The programmable resistive element unit 170' has a programmable resistive element 171' coupled to a PMOS having a source 172', a gate 173', a drain 174', an N-well 176' and an N-well contact 175'. This PMOS has a special conduction mode that is difficult to find in the existing CMOS digital or analog technology, that is, the level of the drain 174' is pulled to a very low voltage (such as grounding) to conduct the junction diode at the source 172', This in turn provides programming as shown by the dashed lines. Because the IV curve of the diode follows the exponential law instead of the square law of the MOS, this mode of operation can provide higher current to reduce the cell size and lower the programming voltage. This PMOS can be turned on during reading for low voltage reading.

Fig. 6i and Fig. 6j further show the operation state of the components shown in Fig. 6g and Fig. 6h to illustrate the innovation of the special unit. Figure 6i shows the programming and reading states by the diode. During programming, WLPB of the selected cell is coupled to a very low voltage (eg, ground) to turn on the source junction diode, while WLRB can be coupled to VDDP (the programming voltage) or ground. WLPB and WLRB of unselected cells may both be coupled to VDDP. When reading, WLRB of the selected cell is coupled to VDD core voltage or ground, and WLPB is coupled to ground to conduct the source junction diode of PMOS 171 shown in FIG. 6g. Both WLPB and WLRB of unselected cells are coupled to VDD. Figure 6j shows the state programmed and read by the MOS. The mode of operation shown in this figure is similar to that shown in Figure 6i, except that WLRB and WLPB of the selected cell are coupled to 0 Volts and VDD/VDDP when reading and programming, respectively. Therefore, the PMOS can be turned on when programming or reading. This PMOS can be laid out by conventional PMOS, but its operating voltage is very different from existing PMOS. In other embodiments, a combination of diodes and/or MOSs can also be used for programming or reading, that is, in one embodiment, diodes are used for programming and MOSs are used for reading. In another embodiment, diodes and MOSs are programmed in different current directions for different materials.

FIG. 6k shows a schematic diagram of a programmable resistive device (PRD) unit 730 fabricated on a thermally isolated substrate such as SOI or polysilicon. The thermal conductivity of the thermal isolation substrate is extremely poor, and the Programmable Resistive Element (PRE) can be shared with the gate of the program selector while still maintaining high programming efficiency. The cell 730 has a PRE comprising a body 731 , an anode 732 and a cathode 733 . The body 731 of the PRE is also the gate of a pseudo-gate diode having an active region 734, a cathode with an N+ implant 735 and a cathode contact 737, and an anode with a P+ implant 736 and an anode contact 738 . The cathode of the PRE is coupled by a metal 739 to the anode of the dummy gate diode.

FIG. 61 shows a schematic diagram of a programmable resistive device (PRD) unit 730' fabricated on a thermally isolated substrate such as SOI or polysilicon. The thermal conductivity of the thermal isolation substrate is extremely poor, and the Programmable Resistive Element (PRE) can be shared with the gate of the program selector while still maintaining high programming efficiency. The cell 730' has a PRE comprising a body 731', an anode 732' and a cathode 733'. The body 731' of the PRE is also the gate of a MOS with an active region 734', a drain with a drain contact 737' covered by an N+ implant 735', and a source contact covered by a P+ implant 736' source at point 738'. The cathode of the PRE is coupled to the source contact 738' of the MOS by a metal 739'. Similar to the operation of Figures 6g-j, the PRD cell 730' can be programmed or read by turning on the channel of the source junction diode or transistor of the MOS.

The PRD units 730, 730' shown in Figures 6k and 61 are for illustration purposes only. The thermal isolation substrate can be SOI or polysilicon substrate. The active region can be silicon, germanium, silicon germanium, III V or II VI semiconductor material. The PRE can be an electrical fuse (including an antifuse), a phase change (PCM) film, a magnetic penetration interface (MTJ) film, a resistive memory (RRAM) film, and the like. The PRE can be fabricated with a heat sink as shown in Figure 7a-e, a heating element as shown in Figure 7f, or an expansion zone as shown in Figure 7g-i. The program selector can be diode or MOS. The MOS selector can be programmed or read by turning on a MOS channel or a source junction. The present invention can have multiple implementations and combinations, all of which are within the patent scope of the present invention.

Figure 7a shows a top view of an e-fuse element 88". The e-fuse element 88" uses a thermally conductive but electrically insulating heat sink to couple to the anode. This electric fuse element 88 ", for example, can use the resistance element 30a shown in Figure 4a. This electric fuse element 88 " can include an anode 89 ", a cathode 80 ", a main body 81 " and an N+ active region 83". The N+ active region 83" of the P-type substrate is coupled to the anode 89" via a metal 84". In this embodiment, the N+ active region 83" is electrically insulated from the conduction path (that is, the N+/P sub-diode is reverse Bias), but thermal conduction with the P-type substrate as a heat sink. In other embodiments, the heat sink can be directly coupled to the anode 89" without other metal or internal connections. In other embodiments, the heat sink can also be coupled to the body, cathode, and anode of a fuse element Part or all. The heat sink of this embodiment can provide a sharp thermal gradient to speed up programming. In other embodiments, the body can be bent 45 degrees or 90 degrees one or more times.

FIG. 7b shows a top view of another embodiment of an e-fuse element 88"'. This e-fuse element 88"' is similar to that shown in FIG. The heat sink under the main body 81"' and close to the anode 89"'. The electric fuse element 88"' can be a resistor element 30a as shown in FIG. 4a, for example. The e-fuse element 88"' may include an anode 89"', a cathode 80"', a body 81"' and an active region 83"' close to the anode 89"'. The active region 83"' is located under the body 81"' so that the oxide layer in this region is thinner than other regions (eg thin gate oxide instead of thick STI oxide). The active region 83"' on the oxide can effectively dissipate heat to provide a thermal gradient for accelerated programming. According to other embodiments, the thin oxide region 83"' can be on the body, cathode and anode portions of a fuse element or All below to act as a heat sink to speed up programming.

FIG. 7c shows a top view of an electrical fuse element 198 according to another embodiment. The e-fuse element 198 is similar to that shown in Figure 7a, but has a thinner oxide region 193 on either side of the anode 199 to provide another form of heat dissipation. The electrical fuse element 198 can be, for example, the resistor element 30a shown in FIG. 4a. The e-fuse element 198 may include an anode 199 , a cathode 190 , a body 191 and an active region 193 near the anode 199 . The active region 193 is located under the anode 199 so that the oxide layer in this region is thinner than other regions (eg thin gate oxide rather than thick STI oxide).

FIG. 7d shows a top view of another embodiment of an electrical fuse element 198'. The e-fuse element 198' is similar to that shown in Figure 7a, but has a thinner oxide region 193' near the anode 199' side to provide another form of heat dissipation. The electrical fuse element 198', for example, can use a resistor element 30a as shown in FIG. 4a. The e-fuse element 198' may include an anode 199', a cathode 190', a body 191' and an active region 193' proximate to the anode 199'. The active region 193' is close to the anode 199' so that the oxide layer in this region is thinner than other regions (such as thin gate oxide instead of thick STI oxide) and can dissipate heat rapidly to provide a thermal gradient for fast programming. According to other embodiments, the thin oxide region may be close to one side, two sides, three sides, four sides or any side of the body, cathode or anode of a fuse element to facilitate heat dissipation. According to other embodiments, at least one substrate contact coupled to the active area (such as active area 193') may be provided to avoid latch-up. Contact posts or metal on the base contacts can act as another heat sink.

Figure 7e is a top view of another example of an electrical fuse element 198", which is similar to that shown in Figure 7a, but has a heat sink 195" located at the cathode. This electrical fuse element 198" For example a resistive element 30a as shown in Fig. 4a may be used. The electric fuse element 198" may include a cathode 199", an anode 190", a body 191" and a heat sink 195". According to other embodiments, the heat sink may only have one side instead of two sides for proper fit Small unit space, and its length can increase or decrease.According to other embodiments, this radiator also can be a part of anode or main body on one side (or both sides).In another embodiment, the aspect ratio of radiator can be greater than 0.6 or greater than the minimum required by the design rule.

Figure 7f is a top view of another example of an electric fuse element 198"', which is similar to that shown in Figure 7a, but has a heating element 195"' close to the cathode. The electric fuse The silk element 198"' can be, for example, the resistance element 30a shown in FIG. 4a. The electric fuse element 198"' may include an anode 199"', a cathode 190"', a body 191"' and a high resistance region 195"' as a heating element. The high resistance region 195"' may generate more heat to assist in programming this fuse element. According to an embodiment, the heating element can be non-silicided polysilicon or non-silicided active region to have a higher resistance value. According to another embodiment, the heating elements can be single or multiple contacts/vias connected in series to increase the resistance value to generate more heat on the programming path. The heating element 195"' can be placed at the cathode, anode, body of some or all of the fuse elements. The active area 197"' has a body contact point to avoid latch-up. The contact studs in the active area 197"' also act as heat sinks.

FIG. 7g shows a top view of an e-fuse element 298 according to another embodiment. The electrical fuse element 298 is similar to that shown in Figure 7a, but with an extension at the cathode. The electrical fuse element 298 can use the resistor element 30a shown in FIG. 4a. The e-fuse element 298 may include a cathode 299 , an anode 290 , a body 291 and an extended cathode region 295 . According to another embodiment, the extended cathode region 295 can also be only on one side of the main body 291 to fit a small unit space, and its length can be increased or decreased. In a more general sense, the extended cathode region may be called an extended region, that is, the extended cathode region is an example of the extended region. According to another embodiment, the extension region can be the anode or part of the body on one or both sides. According to another embodiment, the aspect ratio of the extension region is greater than 0.6. The extension region is any region longer than required by the design rule and coupled to the anode, cathode, or body with little or no current flow.

Figure 7h shows a top view of another embodiment of an e-fuse element 298' having an extended region in the cathode portion. The electrical fuse element 298' may include a cathode 299', an anode 290', and a body 291'. The cathode 299' has extended cathode regions 295' proximate to one or both sides of the body 291' to aid (ie, speed up) programming. The extension region 295' is the portion of the fuse element extending from the point closest to the cathode or anode contact and is longer than the region required by the design rule. The contact point of the anode 290' of the electrical fuse element 298' is also borderless, that is, the width of the contact point is larger than the width of the fuse element below it. According to another embodiment, the cathode contact point is also borderless and/or the anode part also has an extended area.

Figure 7i shows another embodiment of the electric fuse element 298 "top view, this electric fuse element 298" may include a cathode 299", an anode 290", a main body 291". The cathode 299" has a structure close to the main body 291 The expansion area 295" on both sides is used to speed up programming. This expansion area 295" is the part of the fuse element extending from the cathode and anode contacts and has a small current or no current, or its length is longer than the design rule. ) required length. The aspect ratio of the extension region 295" along the current path is greater than that required by the design rule, or may be greater than 0.6. The anode 290' has a common contact 296". A metal 293" is located on the common contact point 296" to interconnect the body 291' with the active region 297". According to one embodiment, the extension region may be close to one side of the body 291" and/or connected to cathode or anode. According to another embodiment, the anode can have an extension area and/or the cathode can have a common contact.

A heat sink can provide a temperature gradient that speeds up programming. The heat sink shown in Figures 7a-e is for illustrative purposes. A heat sink can be a thin oxide region on one, two, three, four or any sides near, below or above the anode, body or cathode to accelerate heat dissipation. The heat sink can be the anode of the fuse element, the main body or an extended area of the cathode to accelerate heat dissipation. The heat sink can also be one or more conductors coupled to (in contact with or close to) the anode, body, or cathode of the fuse element to accelerate heat dissipation. The heat sink can also be an anode or cathode with a larger area (with one or more contact points/vias) to speed up heat dissipation. The heat sink can also be a fuse element close to the active area of the cathode, body or anode (also can have a contact post on at least the active area) to accelerate heat dissipation. An OTP cell with a common contact (ie metal interconnecting the MOS gate and the active area at a single contact point) can also be considered as a heat sink embodiment for the MOS gate to efficiently dissipate heat into the active area.

The extended area shown in Figure 7g-i is the extended part of the fuse element from the contact point or via. This part can be longer than the value required by the design rule and has reduced or no current flow. , thereby speeding up programming. An extended region (eg, a 45 degree or 90 degree bend and may include multiple components) may be on one, two, three or four sides or any side of the anode, body or cathode of the fuse element. An expansion area can also be a heat sink for auxiliary heat dissipation. Although the implementation structure can be very similar, the heat sink and expansion area are based on different physical mechanisms to speed up programming. An expansion area can serve as a heat sink, but the heat sink does not have to be an expansion area. Embodiments of the present invention can be implemented alone or in combination.

In some embodiments, the thermal conductance (ie, heat loss) of a fuse element can be increased by 20% to 200% by the heat sink. Likewise, a heating element can add more heat to assist in programming the fuse elements. A heating element (such as element 195"' of FIG. 7f) is usually located at or near a portion (or all) of the fuse element's cathode, body, or anode with high resistance to generate more heat. A heating element can be formed by One or more non-salicided polysilicon, non-salicided active regions, one or more contact points or vias or a combination thereof, or one or more high-resistance internal connections on the programming path. The resistance value of the heater can be 8Ω to 200Ω; in some embodiments, it may be 20Ω to 100Ω.

Fuse elements with heat sinks, heaters, or extensions can be made of polysilicon, metal suicide polysilicon, metal suicide, polysilicon metal, metal, metal alloy, metal gate, local interconnect, metal zero (metal0), thermal isolation Active area or CMOS gate etc. production. In addition, there are still many different combinations and changes to provide heat sinks capable of dissipating heat, heating elements capable of generating heat, and expansion areas for assisting programming, and these combinations and changes are all within the scope of the present invention.

Figure 7j shows a top view of an e-fuse element 98' according to another embodiment. The e-fuse element 98' is similar to that shown in Figure 7a, except that there is at least one notch in the body to aid in programming. In general, a target portion of the body 91' may be formed with a smaller area (eg, thinner) to form the notch. The electrical fuse element 98' can be used for the resistor element 30a shown in FIG. 4a, for example. The electric fuse element 98' includes an anode 99', a cathode 90' and a body 91'. The body 91' includes at least one notch 95' to allow the fuse element to break easily during programming.

Figure 7k shows a top view of an e-fuse element 98" according to another embodiment. The e-fuse element 98" is similar to that shown in Figure 7a, except that the fuse element is part NMOS metal gate and part PMOS metal grid. This electric fuse element 98 ", for example, can be used for the resistance element 30a shown in FIG. The main body of the production is 91" and 93". Using different kinds of metals in the same fuse element, the temperature increase during programming can generate thermal expansion with large stress, thereby breaking the fuse.

The OTP elements shown in Figures 7a-k illustrate only some of the embodiments. As mentioned earlier, this OTP element can be fabricated from any interconnect including but not limited to polysilicon, metal silicided polysilicon, metal silicide, local interconnect, polysilicon metal, metal, metal alloy, metal gate, thermally isolated active region or a CMOS gate, or a combination of the above. Polysilicon metal is a sandwich structure of metal-metal nitride-polysilicon (ie W/WNx/Si), which can be used to reduce the resistance value of polysilicon. The OTP element can be N-type, P-type or partially N and partially P-type. Each OTP element has an anode, a cathode and at least one host. For polysilicon/polysilicon metal/local interconnect metal fuses, the number of anode or cathode contacts may not exceed two; for metal fuses, the number of anode or cathode contacts may not exceed four.

In other embodiments, the number of contact points of the anode or the cathode may be only one. The contact size may be larger than at least one contact size outside the OTP memory array. The contact periphery can be smaller than at least one contact periphery outside the OTP memory array. In other embodiments, the periphery can be a negative value, that is, the contact point is wider than the contact area below it, which is a so-called borderless contact point. The aspect ratio of the body may be 0.5-8, or in some embodiments 2-6 (polysilicon/local interconnect/polysilicon metal/metal gate body) or 10 or more (metal body). In addition to the above-mentioned examples, the scope of the present invention also includes combinations and parts of the above-mentioned examples.

Polysilicon that defines CMOS gates and interconnects in high-k/metal gate CMOS processes can also be used as an OTP element. The OTP element can be P-type, N-type or part N and part P type. For fuse elements with P+ type and N+ type doping, the resistance ratio before and after programming can be increased to create a diode after programming, such as polysilicon, polysilicon metal, thermally isolated active area, or high dielectric Coefficient/Metal Gate The metal gate of CMOS. If the metal gate CMOS has a polysilicon sandwich structure between metal alloy layers, the metal alloy layers can be manipulated with a mask generated by a layout database to create a diode in the fuse element. In SOI or SOI-like processes, a fuse element can be created from thermal isolation of the active region so that the fuse element can be implanted with P+ type, N+ type or part N+ and part P+ type impurities at each end of the active region. If a fuse element is partially N+ and partially P+ impurity, the fuse element behaves like a reverse biased diode, as the metal silicide on top is depleted after programming. In one embodiment, if there is no metal silicide on the top of the active region, the OTP element can also be built from a partially N+ and partially P+ doped isolated active region, which behaves like a diode that collapses under forward or reverse bias . If an isolated active region is used to create an OTP element, the OTP element can be combined with a program select diode in a single active island region to reduce the area used.

For process technologies that can provide local interconnects, the local interconnects can be part or all of the OTP elements. Local interconnects, also known as level zero (M0), are a by-product of the silicide process and directly interconnect polysilicon (or MOS gates) to the active region. At advanced processes beyond 28nm, scaling progresses much faster along the silicon surface than along the height direction. Therefore, the aspect ratio of the CMOS gate (the ratio of the gate height to the channel length) becomes extremely high, resulting in a high manufacturing cost of the contact point between the metal 1 and the source/drain or the CMOS gate (such as considering the component area and costs). The local internal connection can be used as the intermediate internal connection between the source/drain and the CMOS gate, the intermediate internal connection between the CMOS gate and metal 1, or the intermediate internal connection between the source/drain and metal 1 in one or two layers. connect. According to an embodiment, local interconnects, CMOS gates, or a combination thereof can be used as OTP elements. According to another embodiment, the OTP element and one end of the program selector can be directly connected (without any contact point) via a local interconnection to save area. Therefore, the zeroth layer can be used to connect the source/drain to pad to the same height as the metal gate, so that metal 1 can be used to connect the zeroth layer and the metal gate.

Those skilled in the art will know that the above description is only an illustrative example, and the present invention still includes various variations and equivalent ways to fabricate e-fuse, anti-fuse elements or program selectors in a CMOS process.

Figures 8a and 8b show P+/N well diodes and fuse elements fabricated by different isolation implementations, respectively. Without isolation, the P+ and N+ active regions would be shorted by the metal silicide grown on them. One to four sides or any side of the cell can be isolated by STI, dummy CMOS gate, SBL or a combination thereof. The P+ and N+ active regions as the P and N terminals of the diode are the source and drain of the CMOS element. Both the P+ and N+ active regions are located in the N well, which is the N well embedded in the PMOS in the standard CMOS process. For simplicity of illustration, FIGS. 8a and 7b show that there is only one N+ active region in a P+ active region, but the diode N+ active regions in most wells can be shared.

Figure 8a shows a top view of an e-fuse unit 70 having a P+/N well diode and an adjoining connection contact according to one embodiment. The active regions 73 and 74 isolated by the STI are covered by a P+ implant layer 77 and an N+ implant layer (the complement of the P+ implant layer 77 ), respectively, to form the P and N terminals of the diode 70 . Both active regions 73 and 74 are located in an N-well 75, which is a well in which PMOS is embedded in a standard CMOS process. A fuse element 72 is coupled to P+ active region 73 via a metal 76 (in single contact 71 ). The contact point 71 is significantly different from the traditional contact point. One contact point can be connected to the fuse element through a metal, and the other connection point can be connected to the metal through the P+ active region. By directly connecting a fuse element to an active area via a metal in a single contact, the cell area can be greatly reduced. The adjacent connection contact can be larger than a typical contact, and can be a square contact with about twice the area of a typical CMOS process square contact. The fuse element of this embodiment can be made of a CMOS gate (including polysilicon, metal silicided polysilicon, polysilicon metal, local interconnect, or non-aluminum metal CMOS gate) to provide adjacent connection contacts.

Fig. 8b shows a top view of an e-fuse cell 70" having a dummy MOS gate 78" to serve as the P+ and N+ (as across the diode) in the N-well according to one embodiment. isolation, and has an electrical fuse element 72". An active region 71" is divided into an upper active region 73" and a lower active region 74" by a dummy MOS gate 78". The upper active region 73" and the lower active region 74 "are respectively covered by P+ implant layer 77" and N+ implant layer (complementary to P+ implant layer 77"). In unit 70", the upper active region 73" and lower active region 74" constitute the two ends of the diode. A dummy MOS gate (eg, a polysilicon) 78" provides isolation of the diode P+/N+ regions of cell 70" and may have a fixed bias or be coupled to the cathode of the diode. The polysilicon 78" is a dummy MOS gate in a standard CMOS process, and may be a metal gate in an advanced metal gate CMOS process. The width of the dummy MOS gate can be close to the minimum gate width of CMOS technology. According to a In an embodiment, the width of the dummy MOS gate is less than twice the minimum gate width of CMOS technology. The dummy MOS gate can also be made by I/O components to withstand higher voltages. The active region 71 "is located in an N well 75", the N The well is the well that is embedded in PMOS in a standard CMOS process. A fuse element 72" is coupled at one end to the P+ active region 73" via a metal 76" (via contacts 75"-2 and 75"-3), The other end is coupled to a high voltage source line V+ (via contact 75"-1). The N+ region 74" is coupled to a low voltage source line V- via contact 75-4". According to one embodiment, the contact At least one of the points 75"-1,2,3,4 is larger than the contact point outside the memory array to reduce the resistance. When high and low voltages are applied to V+ and V- respectively, a current flows through the fuse element 72" to program it in a high resistance state.

FIG. 9 is an example processor system 700 . Processor system 700 in one example includes a programmable resistive element 744 in memory 740 (eg, in cell array 742 ). The processor system 700 may be, for example, a computer system. The computer system includes a central processing unit 710, communicates through a common bus 715, and includes various memories and peripheral devices (such as I/O 720, hard disk 730, CDROM 750, memory 740, and other memories 760). Other memories 760 are conventional memories, such as SRAM, DRAM, and flash memory, typically connected to the CPU 710 through a memory controller. CPU 710 is typically a microprocessor, a digital signal processor or other programmable digital logic element. The memory 740 is preferably implemented as an integrated circuit, including a memory array 742 having at least one programmable resistive element 744 . The memory 740 is generally connectable to the CPU 710 through a memory controller interface. If desired, memory 740 may be combined with a processor (such as CPU 710) in a single integrated circuit.

The invention can be implemented partially or completely on a printed circuit board or in an integrated circuit in a system. Programmable resistive elements can be fuses, antifuses or new non-volatile memories. Fuses can be silicided or non-silicided polysilicon fuses, thermally isolated active area fuses, local interconnect fuses, metal fuses, contact point fuses, layer-to-layer contact fuses, or fuses made of CMOS gates. Silk. The antifuse may be a gate oxide breakdown antifuse, a contact with a dielectric therebetween, or an interlayer contact antifuse. The new non-volatile memory can be magnetic memory (MRAM), conductive bridge random access memory (CBRAM), or resistive random access memory (RRAM). Although the programming mechanisms are different, their logic states are defined by different resistor values.

Certainly, the present invention also can have other multiple embodiments, without departing from the spirit and essence of the present invention, those skilled in the art can make various corresponding changes and deformations according to the present invention, but these corresponding Changes and deformations should belong to the scope of protection of the appended claims of the present invention.

Claims (41)

1. A one-time programmable memory, characterized in that, comprising: A plurality of one-time programmable cells, at least one one-time programmable cell comprising at least: A one-time programmable element includes at least one electrical fuse coupled to a first voltage supply line; and a program selector coupled to the one-time programmable element and a second voltage supply line, wherein at least a portion of the electrical fuse has at least one extension region through which a reduced current or no current flows; and Wherein the one-time programmable element can be programmed by applying voltage to the first and second voltage supply lines and turning on the program selector, thereby changing the one-time programmable element to different logic states. 2. The one-time programmable memory according to claim 1, wherein the electrical fuse is made of polysilicon, metal silicide, metal silicided polysilicon, CMOS metal gate, metal internal connection, polysilicon metal, local internal connection, At least one of a metal alloy, or a thermally isolated active region. 3. The one-time programmable memory according to claim 1, wherein the width of the extension region is equivalent to the minimum width, and/or the aspect ratio of the current path is greater than 0.6 times. 4. The one-time programmable memory of claim 1, wherein at least a portion or the extension of the e-fuse has at least one bend of about 45 degrees or 90 degrees. 5. The one-time programmable memory according to claim 1, wherein the electrical fuse has two ends, and the aspect ratio between the two closest contact points of the electrical fuse at the two ends is 2 to 8. 6. The one-time programmable memory according to claim 1, wherein the electrical fuse has only one contact at at least one end. 7. The one-time programmable memory according to claim 1, wherein the electrical fuse has no more than two contact points on at least one end. 8. The one-time programmable memory according to claim 1, wherein the one-time programmable unit is a part of a one-time programmable memory array, wherein the electrical fuse or the program selector has at least one The contact point is larger than at least one contact point outside the one-time programmable memory array. 9. The one-time programmable memory according to claim 1, wherein the one-time programmable memory is a part of a one-time programmable memory array, wherein the electrical fuse or the program selector has at least one The periphery of the contact point is smaller than the periphery of at least one contact point outside the one-time programmable memory array. 10. The one-time programmable memory according to claim 1, wherein the width of at least one contact point at at least one end of the electrical fuse is the same as or greater than the width of the fuse. 11. The one-time programmable memory according to claim 1, wherein the electrical fuse has at least one active area adjacent to the fuse, and/or at least one substrate contact is established on the active area. 12. The one-time programmable memory according to claim 1, wherein the program selector comprises at least one diode or a MOS, which can be turned on through a channel or a source/drain junction. 13. The one-time programmable memory of claim 1, wherein the program selector is built in a thermally isolated substrate or a three-dimensional fin structure. 14. The one-time programmable memory according to claim 1, wherein the program selector has at least one diode, and the diode has at least one first active region and a second active region isolated from the first active region , the first active region has a first type of doping, the second active region has a second type of doping, the first active region provides the first end of the diode, the second active region provides the second end of the diode, the Both the first and the second active regions are located in a common CMOS well or on an isolation substrate, at least one of the active regions is constructed by a source or a drain of a CMOS element. 15. The one-time programmable memory according to claim 14, wherein the one-time programmable memory comprises at least one shallow trench isolation, the shallow trench isolation isolates the first and second terminals of the diode, and/or isolate adjacent one-time programmable cells. 16. The one-time programmable memory according to claim 14, wherein the one-time programmable memory comprises at least one dummy CMOS gate, the dummy CMOS gate isolates the first and second ends of the diode, and/or isolate adjacent one-time programmable cells. 17. The one-time programmable memory according to claim 1, wherein the gate oxide thickness of a part of the program selector is larger than the gate oxide thickness of the core element. 18. An electronic system, characterized in that it comprises: at least one processor; and A one-time programmable memory is operatively connected to the processor, the one-time programmable memory comprising: A plurality of one-time programmable cells, at least one one-time programmable cell comprising: a one time programmable element comprising at least one electrical fuse operatively coupled to a first voltage supply line; and a program selector coupled to the one-time programmable element and a second voltage supply line, wherein at least a portion of the electrical fuse has at least one extension region through which a reduced current or no current flows; and Wherein the one-time programmable element is programmed by applying voltage to the first and second voltage source lines and turning on the program selector, thereby changing the one-time programmable element to different logic states. 19. The electronic system according to claim 18, wherein the program selector comprises at least one diode or a MOS, which can be turned on through a channel or a source/drain junction. 20. The electronic system according to claim 18, wherein the electrical fuse is made of polysilicon, metal silicide, metal silicided polysilicon, CMOS metal gate, metal interconnect, polysilicon metal, local interconnect, metal alloy, or At least one of the active regions is thermally isolated. 21. A method for operating a one-time programmable memory, comprising: providing a plurality of one-time programmable cells, at least one one-time programmable cell comprising (i) one one-time programmable element comprising at least one electrical fuse coupled to a first voltage supply line; ( ii) a program selector coupled to the one-time programmable element and a second voltage supply line, wherein at least a portion of the e-fuse has at least one extended region, the extended region has reduced or no current flow passed; and At least one cell of the one-time programmable cell is single-time programmed to a different logic state by applying a voltage to the first and second voltage supply lines and turning on the program selector. 22. The method for operating a one-time programmable memory according to claim 21, wherein the program selector comprises at least one diode or a MOS, which can be turned on through a channel or a source/drain junction. 23. The method for operating a one-time programmable memory according to claim 21, wherein the electrical fuse is made of polysilicon, metal silicide, polysilicon metal silicide, CMOS metal gate, metal interconnection, polysilicon metal, local internal At least one of connections, metal alloys, or thermally isolated active regions is made. 24. A method for programming a one-time programmable memory, comprising: providing a plurality of one-time programmable cells, at least one one-time programmable cell comprising (i) one one-time programmable element comprising at least one electrical fuse coupled to a first voltage supply line; ( ii) a program selector coupled to the one-time programmable element and a second voltage supply line; and By applying a plurality of voltage or current pulses to the first and second voltage supply lines and turning on the program selector to gradually change the fuse resistance, and then program at least one of the one-time programmable cells at a time to different logical states. 25. The method for programming a one-time programmable memory according to claim 24, wherein the step of programming at least one unit of the one-time programmable units comprises: (a) obtaining a destructive programming current that causes a sharp change in resistance of the at least one one time programmable cell; and (b) limiting the programming current below the destructive programming current. 26. The method for programming a one-time programmable memory according to claim 24, wherein the step of programming at least one unit of the one-time programmable units comprises: (a) initially programming a portion of the one-time programmable memory using a low programming voltage and gradually increasing the programming voltage until all the one-time programmable cells can be programmed and verified to be correct, thereby determining a lower programming voltage limit; and (b) continuously increasing the programming voltage to program the same portion of the one-time programmable cells until an overvoltage is asserted under which at least one one-time programmable cell, whether already programmed or not, has been asserted to fail, The excess voltage is a programming voltage upper limit. 27. The method for programming a one-time programmable memory according to claim 26, wherein the step of programming at least one of the one-time programmable cells is to apply a single pulse between the upper limit and the lower limit of the programming voltage between voltages. 28. The method for programming a one-time programmable memory according to claim 24, wherein the selector is a diode, and the diode has a dummy gate to isolate the first end and the second end of the diode, or the selector is A MOS that can be turned on through a channel or a source/drain junction. 29. The method for programming a one-time programmable memory according to claim 24, wherein the program selector has at least one diode, and the diode has at least one first active area and a second active area isolated from the first active area. Active region, the first active region has a first type of doping, the second active region has a second type of doping, the first active region provides the first end of the diode, and the second active region provides the second end of the diode , the first and second active regions are both located in a common CMOS well or on an isolation substrate, and at least one of the active regions is constructed by a source or a drain of a CMOS element. 30. The method for programming a one-time programmable memory according to claim 24, wherein the one-time programmable memory comprises at least one shallow trench isolation, and the shallow trench isolation isolates the first and second diodes. two-terminal, and/or isolate adjacent one-time programmable cells. 31. The method for programming a one-time programmable memory according to claim 24, wherein the program selector is built in a heat-isolated substrate or a three-dimensional fin structure. 32. The method for programming a one-time programmable memory according to claim 24, wherein the electrical fuse comprises a heat sink, a heating element or a part of an expansion area. 33. The programming one-time programmable memory method according to claim 24, characterized in that, the electrical fuse is made of polysilicon, metal silicide, metal silicide polysilicon, CMOS metal gate, metal interconnection, polysilicon metal, local internal At least one of connections, metal alloys, or thermally isolated active regions is made. 34. A programmable resistance element memory, characterized in that it comprises: A plurality of programmable resistance element units, at least one programmable resistance element unit includes at least at least one programmable resistive element coupled to a first voltage supply line, and At least one metal oxide semiconductor MOS element has a source coupled to the programmable resistance element, a drain coupled to a second voltage supply line, a body coupled to the drain, and a third a gate of the voltage supply line; Wherein, by applying a voltage to the first, second and/or third voltage source lines, the source junction diode of the MOS or the channel of the MOS can be turned on to program the programmable resistance element to different logic states. 35. The programmable resistive element memory according to claim 34, wherein the programmable resistive element can (a) turn on the source of the MOS by applying a voltage to the first, second and/or third voltage source lines connecting diodes to program the programmable resistive element to a different logic state; and (b) turning on the channel of the MOS by applying voltage to the first, second and third voltage source lines to read the programmable resistive element is a logical state. 36. The programmable resistive device (PRD) memory according to claim 34, wherein the programmable resistive element can (a) be turned on by applying a voltage to the first, second and/or third voltage source lines MOS source junction diode to change the programmable resistance element to a logic state; and (b) turn on the channel of the MOS by applying voltage to the first, second and third voltage source lines to change the programmable Resistive elements are another logic state. 37. The programmable resistive element memory according to claim 34, wherein the programmable resistive element is a one-time programmable element which can only be programmed once. 38. The programmable resistive element memory according to claim 34, characterized in that the programmable resistive element comprises at least one thin film, characterized in that the programmable resistive element is a phase change memory, a resistive random access memory , conductive bridge random access memory or magnetic memory. 39. The programmable resistance element memory according to claim 34, wherein the programmable resistance element comprises a phase change material film, and the phase change material comprises at least one of germanium, antimony and tellurium. 40. The programmable resistance element memory according to claim 34, wherein the programmable resistance element comprises a metal oxide film between metal electrodes or metal alloy electrodes. 41. The programmable resistance element memory according to claim 34, wherein the programmable resistance element comprises a solid electrolyte film between metal electrodes or metal alloy electrodes.