CN102385917B - Phase change memory, electronic system, reversible resistance memory unit and method for providing the same - Google Patents

Abstract

A phase change memory, an electronic system, a reversible resistance memory unit and a providing method, wherein the memory unit comprises a plurality of diversified reversible resistance memory units, at least one of which comprises: a reversible resistance element coupled to a first power supply voltage line; a diode comprising at least a first active region and a second active region, the first active region having a first type of doping, the second active region having a second type of doping, the first active region providing a first end of the diode, the second active region providing a second end of the diode, the first active region and the second active region both having a common well region, the first active region being coupled to the reversible resistance element, the second active region being coupled to a second power supply voltage line; the first and second active regions being manufactured from a source or a drain of a CMOS, and the well being manufactured from a CMOS well; by applying voltage to the first and second power supply voltage lines, the reversible resistance element reversibly changes resistance to different logic states, and is configured as programmable.

Description

Phase change memory, electronic system, reversible resistance memory unit and method for providing the same

technical field

The present invention relates to programmable memory elements, such as programmable resistance elements used in memory arrays.

Background technique

A programmable resistive element generally means that the resistive state of the element can be changed after programming. The resistance state can be determined by the resistance value. For example, the resistive element can be a one-time programmable OTP (One-Time Programmable) element (such as an electric fuse), and the programming method can apply a high voltage to generate a high current through the OTP element. When this large current flows through the OTP element through the open program selector, the OTP element will be burned into a high or low resistance state (depending on whether it is a fuse or an anti-fuse) and programmed.

Electrical fuse is a common OTP, and this programmable resistance element can be polysilicon, silicided polysilicon, silicide, thermally isolated active area, metal, metal alloy or their combination. The metal can be aluminum, copper or other transition metals. Among them, the most commonly used e-fuse is silicided polysilicon, which is made of the gate of a complementary metal oxide semiconductor transistor (CMOS), and is used as an interconnect. An electrical fuse may also be one or more contacts or vias rather than interconnects of small segments. High current can burn the contact or layer-to-layer contact into a high resistance state. An electrical fuse can be an antifuse, where a high voltage lowers the resistance instead of increasing it. An antifuse may consist of one or more contacts or interlayer contacts with an insulator in between. The antifuse can also be coupled to the CMOS body by the CMOS gate, which contains the gate oxide as an insulator.

The traditional programmable resistive memory storage unit is shown in Fig. 1 . The memory cell 10 includes a resistive element 11 and an N-type metal oxide semiconductor transistor (NMOS) program selector 12 . One end of the resistance element 11 is coupled to the drain of the NMOS, and the other end is coupled to the positive voltage V+. The gate of the NMOS 12 is coupled to the select signal (SEL), and the source is coupled to the negative voltage V-. When a high voltage is applied to V+ and a low voltage is applied to V-, the resistive element 10 can be programmed by raising the programming select signal (SEL) to turn on the NMOS 12. One of the most common resistive elements is silicided polysilicon, the same material that is used when making MOS gates at the same time. The area of the program selector NMOS 12 needs to be large enough to provide the required programming current for several microseconds. The programming current for silicided polysilicon is typically from a few milliamps (for fuses about 40 nanometers wide) to 20 milliamperes (for fuses about 0.6 microns wide). Therefore, the area of the e-fuse memory cell using silicided polysilicon often needs to have a large area.

The programmable resistance element may be a reversible resistance element, which can be programmed repeatedly and reversibly into a digital logic value "0" or "1". Programmable resistive elements can be fabricated from phase change materials such as Ge2Sb2Te5 (GST-225) consisting of germanium (Ge), antimony (Sb), tellurium (Te), or compositions including indium (In), tin (Sn) or selenium ( Se) GeSbTe-like materials. Through short pulses of high voltage or long pulses of low voltage, phase change materials can be programmed into an amorphous high-resistance state or a crystalline low-resistance state. The reversible resistive element can be resistive random access memory (resistive memory RRAM), the memory cell is made of a metal oxide between metal or metal alloy electrodes, such as platinum/nickel oxide/platinum (Pt/NiO/Pt) , made of titanium nitride/titanium oxide/hafnium oxide/titanium nitride (TiN/TiOx/HfO2/TiN). The reversible change of the resistance state is via the polarity, intensity, and duration of the voltage or current pulses to create or destroy conductive filaments. Another programmable resistive element similar to resistive random access memory (RRAM) is conductive bridge random access memory (CBRAM). The memory is based on the electrochemical deposition and removal of metal ions in a solid electrolyte film between metal or metal alloy electrodes. The electrodes can be an oxidizable anode and an inert cathode, and the electrolyte can be a silver- or copper-doped sulfur glass such as germanium selenide (GeSe) or sulfur selenide (GeS). The reversible change of the resistance state is via the polarity, intensity, and duration of the voltage or current pulses to create or destroy the conductive bridge.

Phase change memory (PCM) is another conventional programmable resistive element 20, as shown in FIG. 2a. The PCM memory cell comprises a phase change material (Phase Change Material) thin film 21 and a bipolar transistor 22 as a programming selector, which has a P+ emitter 23, an N-type base 27 and a P-type base collector 25. One end of the phase change film 21 is coupled to the emitter 23 of the bipolar transistor 22 , and the other end is coupled to the positive voltage V+. The N-type base 27 of the bipolar transistor 22 is coupled to the negative voltage V-. Collector 25 is coupled to ground. By applying an appropriate voltage between V+ and V- for an appropriate time, the phase change film 21 can be programmed into a high or low resistance state, depending on the voltage and duration. By convention, programming a phase change memory into a high resistance state (or reset state) takes about 3V for 50ns and consumes about 300uA of current. To program a phase change memory into a low resistance state (or set state) requires 2V for about 300ns and consumes about 100uA of current. This memory cell requires a special process to properly isolate each memory cell, thus requiring 3-4 more masks than a standard CMOS logic process, making it more expensive to manufacture.

Figure 2b shows another programmable resistance element of a phase change memory (PCM), which has a programmable resistance element and a diode as a programming selector. Figure 3 shows its cross-section, and its programmable resistor is constructed from a phase-change film. The phase change memory material includes a phase change film 21' and a diode 22'. Phase change film 21' is coupled between diode anode 22' and positive voltage V+. The cathode 22' of the diode is coupled to the negative voltage V-. By applying an appropriate voltage between V+ and V- for an appropriate time, the phase change film 21' can be programmed to a high or low resistance state, depending on the voltage and duration, see "Kwang-Jin Lee et al ., "A 90nm 1.8V 512Mb Diode-Switch PRAM with 266MB/s Read Throughput," International Solid-State Circuit Conference, 2007, pp.472-273". Figure 2c shows an example of using a diode as a program selector for a phase change memory (PCM) memory cell. Although this technology can reduce the PCM memory cell size to only 6.8F2 (F stands for feature size), the diode requires very complex manufacturing processes such as selective epitaxial (epitaxy) growth (SEG). As a result, the application of embedded PCM will become very expensive.

FIG. 3 shows a cross-sectional view of a conventional phase change memory cell (with bipolar transistor 22). The bipolar transistor 22 includes a P+ active region 23, an N shallow well 24, an N+ active region 27, a P-type substrate 25, and shallow trench isolation (STI) 26 for isolating components. The P+ active region 23 and the N+ active region 27 are coupled to the N well 24 , which is the P and N terminals of the emitter and base diodes in the bipolar transistor 22 , and the P-type body 25 is the collector of the bipolar transistor 22 . This kind of memory cell requires N shallow well 24 to be shallower than shallow trench isolation 26 to properly isolate each memory cell, so it needs 3-4 more masks than the standard CMOS logic process, making its production more expensive.

Contents of the invention

The object of the present invention is to provide a phase-change memory, an electronic system, a reversible resistance memory unit and a method for providing a programmable resistance element memory unit using a diode as a programming selector. Programmable resistive elements can use standard CMOS logic processes to reduce memory cell size and cost.

The present invention provides a reversible resistance memory unit, comprising: a plurality of diversified reversible resistance memory units, at least one reversible resistance memory unit comprising: a reversible resistance element coupled to a first power supply voltage line; and a diode Comprising at least a first active region and a second active region, wherein the first active region has a first type of doping, the second active region has a second type of doping, the first active region provides the A first end, the second active region provides a second end of the diode, a common well region exists for both the first active region and the second active region, the first active region is coupled to the reversible resistive element, and the second active region is coupled to a second supply voltage line; wherein the first and second active regions are fabricated from the source or drain of a metal oxide semiconductor (CMOS) element, and the well is fabricated from a CMOS Well fabrication; wherein by applying a voltage to the first and second supply voltage lines, the reversible resistance element thereby reversibly changes resistance to different logic states, thereby being configured to be programmable.

The present invention provides a phase-change memory, comprising: a plurality of diversified phase-change memory units, at least one phase-change memory unit comprising: a phase-change film coupled to a first power supply voltage line; and a diode comprising at least one first An active region and a second active region, wherein the first active region has a first type of doping, the second active region has a second type of doping, the first active region provides a first end of the diode , the second active region provides a second end of the diode, both the first active region and the second active region have a common well region, the first active region is coupled to the phase change film, the second active region The active region is coupled to a second supply voltage line; wherein the first and second active regions are fabricated from the source or drain of a metal oxide semiconductor (CMOS) element, and the well is fabricated from a CMOS well; wherein via applying a voltage to The first and second power supply voltage lines, the phase change film thereby reversibly changing the resistance to different logic states, are configured to be programmable.

The present invention provides an electronic system comprising: a processor; and a reversible resistive memory operatively connected to the processor, the reversible resistive memory comprising a plurality of reversible resistive memory cells providing data storage , each reversible resistive memory cell includes: a reversible resistive element coupled to a first supply voltage line; and a diode including at least a first active region and a second active region, wherein the first active region has a first type doping, the second active region has a second type of doping, the first active region provides a first end of the diode, the second active region provides a second end of the diode, the first and second Both of the two active regions have a common well region, the first active region is coupled to the reversible resistance element and the second active region is coupled to a second supply voltage line; wherein the first and second active The region is fabricated from the source or drain of a metal oxide semiconductor (CMOS) element, and the well is fabricated from a CMOS well; where a voltage is applied to the first and second supply voltage lines, the reversible resistive element thereby reversibly changes the resistance to different logic states, which in turn are configured to be programmable.

The present invention discloses a method for providing a reversible resistive memory, comprising: providing a plurality of reversible resistive memory cells, at least one reversible resistive memory cell comprising at least (i) a reversible resistive element coupled to a first power supply voltage and (ii) a diode comprising at least a first active region and a second active region, the first active region has a first type of doping, the second active region has a second type of doping, the first active region region provides a first end of the diode, the second active region provides a second end of the diode, both of the first and second active regions are connected from the source or drain of a metal oxide semiconductor (CMOS) device and there is a common well region, the well is fabricated from a CMOS well, the first active region is coupled to the resistive element and the second active region is coupled to a second supply voltage line; and by applying the voltage to the first and second voltage lines to change the resistance of the reversible resistance memory cell, thereby programming the logic state of the reversible resistance memory cell.

The present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments, but not as a limitation of the present invention.

Description of drawings

Fig. 1 shows a schematic diagram of a traditional programmable resistive memory storage unit;

Figure 2a shows another conventional programmable resistive element for phase change memory (PCM), which uses a bipolar transistor as a program selector;

Figure 2b shows a cross-sectional view of a conventional phase-change memory (PCM), which uses a diode as a program selector;

Fig. 3 shows a cross-sectional view of a traditional phase change memory (PCM) memory cell, which uses a diode as a program selector;

Figure 4 shows a block diagram comprising a reversible resistive memory cell using junction diodes according to the present invention;

Figure 5a shows a cross-section of a junction diode, according to this embodiment, the diode uses shallow trench isolation (STI) to isolate the anode and cathode, and acts as a program selector;

Figure 5b shows a cross-section of a junction diode, according to this embodiment, which uses a dummy CMOS gate to isolate the anode and cathode, and acts as a program selector;

Figure 5c shows a cross-section of a junction diode, according to this embodiment, the diode uses a silicide barrier layer (SBL) to isolate the anode and cathode, and acts as a program selector;

Figure 6a shows a cross-section of a junction diode, according to this embodiment, using a dummy CMOS gate in silicon-on-insulator (SOI) technology to isolate the anode and cathode and to act as a program selector;

Figure 6b shows a cross-section of a junction diode, according to this embodiment, which uses a pseudo CMOS gate in FinFET technology to isolate the anode and cathode and act as a program selector;

Fig. 7 shows a cross-sectional view of a programmable resistance element, which uses a phase change material as the resistance element; in addition, according to this embodiment, there is a buffer metal layer coupling the phase change material layer and other metals and P+/N well diodes;

FIG. 8 shows a top view of a PCM memory cell using a P+/N well junction diode as a program selector according to this embodiment;

9 shows a schematic diagram of a portion of a programmable resistive memory, according to this embodiment, consisting of n rows and (m+1) columns of single diode memory cells together with n word line drivers;

Figure 10a depicts a flow chart of a method to program a programmable resistive memory;

Figure 10b depicts a flow chart of a method to read a programmable resistive memory;

Fig. 11 shows a schematic diagram of an embodiment of a processor (Processor) system.

Detailed ways

Below in conjunction with accompanying drawing, structural principle and working principle of the present invention are specifically described:

In an embodiment disclosed herein, a P+/N well junction diode is used as the programmable resistive element of the program selector. This diode can include P+ and N+ active regions (Active regions) in the N well region. Since the P+ and N+ active regions and N-well are in off-the-shelf standard CMOS logic processes, these elements can be fabricated in an efficient and cost-effective manner. There are no additional masks or process steps to save costs. The programmable resistive element can be included in the electronic system.

FIG. 4 shows a block diagram of a reversible resistive memory cell 30 using junction diodes according to one embodiment. In particular, the memory cell 30 includes a reversible resistance element 30a and a diode 30b. Reversible resistive element 30a may be coupled between the anode of junction diode 30b and the positive voltage V+. The cathode of junction diode 30b may be coupled to negative voltage V-. In one embodiment, the reversible resistive memory cell 30 may be a phase-change memory cell, and includes a reversible resistive element 30 a with a phase-change thin film. Junction diode 30b may serve as a program selector. Junction diodes can be fabricated from P+/N wells in P-type substrates using standard CMOS processes. The P+ and N+ active regions as the anode and cathode of the diode are the source or drain of the CMOS element. The N well is the CMOS well used to embed the PMOS element. Alternatively, junction diodes can be constructed using N+/P wells in a P-well CMOS process, which uses an N-type substrate. The reversible resistive element 30a and the junction diode 30b are interchangeable between supply voltages V+ and V-. By applying an appropriate voltage between V+ and V- for an appropriate time, the reversible resistive element 30a can be programmed into a high or low resistance state according to the voltage and duration, so that the programmed memory cell 30 can store a data value ( For example, bits of data). The P+ and N+ active regions of the diode can be isolated using dummy CMOS gates, shallow trench isolation (STI), local oxidation (LOCOS), or silicide barrier layers (SBL). If there is no silicide near the boundary of the first and second active regions, the first and second active regions may be butted or a low dose doped active region may be used to separate the two active regions.

Figure 5a shows a cross-section of a diode 32 using a P+/N well diode with shallow trench isolation (STI) as a program selector in a programmable resistive element. The P+ active region 33 and the N+ active region 37 respectively constituting the P and N terminals of the diode 32 are the source or drain of the PMOS and NMOS in the standard CMOS logic process. N+ active region 37 is coupled to N-well 34 embedded in PMOS in a standard CMOS logic process. Shallow trench isolation (STI) 36 isolates the active regions of the different components. A resistive element (not shown in Figure 5a), such as a phase change film, can be coupled to the P+ region 33 at one end and to the high voltage supply V+ at the other end. To program this programmable resistive element, a high voltage is applied to V+ and a low voltage or ground is applied to N+ region 37 . Therefore, a high current flows through the phase change film and diode 32 to program the resistive element.

Figure 5b shows a cross-sectional view of another embodiment of junction diode 32, which acts as a program selector and is isolated with a dummy CMOS gate. Shallow trench isolation (STI) 36' provides isolation from other active regions. Active region 31' is defined by shallow trench isolation (STI) 36'. The N+ and P+ active regions 37' and 33' here are further defined by the mixture of dummy CMOS gate 39', P+ implant layer 38' and N+ implant layer (complementary to P+ implant layer 38'), respectively, to form a diode 32' N and P ends. The diode 32' is fabricated as a PMOS-like element and includes 37', 39', 33' and 34' as source, gate, drain and N-well, however the source 37' is covered by the N+ implant layer instead of being covered by a P+ implant layer 38' like a true PMOS. The dummy MOS gate 39' is preferably biased at a fixed voltage, and its purpose is only to serve as isolation between the P+ active region 33' and the N+ active region 37' during fabrication. The N+ active region 37' is coupled to the N well 34' which is embedded in the body of the PMOS in standard CMOS logic processes. The P base 35' is a base of P-type silicon. A resistive element (not shown in Figure 5b), such as a phase change film, can be coupled at one end to the P+ region 33' and at the other end to a high voltage supply V+. To program this programmable resistive element, a high voltage is applied to V+ and a low voltage or ground is applied to the N+ active region 37'. Therefore, a high current flows through the phase change element and diode 32' to program the resistive element. This embodiment has ideally small size and low resistance.

Figure 5c shows a cross-section of another embodiment in which junction diode 32" is isolated by silicide barrier layer (SBL) 39" and acts as a program selector. Fig. 5c is similar to Fig. 5b except that the dummy CMOS gate 39' in 5b is replaced by a silicide barrier layer 39" in Fig. 5c to prevent silicide growth on top of the active region 31". Without a dummy CMOS gate or silicide barrier, the N+ and P+ active regions would be disadvantageously shorted by the silicide on the surface of the active region 31".

Figure 6a shows a cross-section of another embodiment, wherein the junction diode 32" is considered as a program selector, and silicon-on-insulator (SOI) technology is used. In SOI technology, the substrate 35" is a material such as silicon dioxide or Similar to an insulator of material, this insulator consists of a thin layer of silicon grown on top. All NMOS and PMOS are in the silicon well area, separated from each other and the substrate 35" by silicon dioxide or similar materials. A one-piece active area 31" passes through the dummy CMOS gate 39", P+ implantation layer 38 The mixture of " and N+ implant layer (complementary to P+ implant layer 38") is divided into N+ active region 37", P+ active region 33" and body 34". Therefore, the N+ active region 37 "and the P+ active region 33" form the N end and the P end of the junction diode 32", respectively. The N+ active region 37" and the P+ active region 33" can be compared with the NMOS and PMOS in the standard CMOS logic process respectively. The source or drain is the same. Likewise, the dummy CMOS gate 39" can be the same as a CMOS gate constructed in a standard CMOS process. The dummy MOS gate 39", which can be biased at a fixed voltage, is intended to serve as isolation between the P+ active region 33" and the N+ active region 37" during fabrication. The N+ active region 37" is coupled to the low Voltage V- and N well 34, which is embedded in the body of PMOS in standard CMOS logic technology. A resistive element (not shown in FIG. 6a), such as a phase-change film, can be coupled to the P+ active region 33" at one end and coupled to the high-voltage power supply V+ at the other end. In order to program this phase-change film memory cell, high and low voltage Applied to V+ and V- respectively, a large current is turned on to flow through the phase change element and the junction diode 32" to program the resistance element. Other embodiments of CMOS isolation technology, such as shallow trench isolation (STI) or dummy CMOS gate, or silicide barrier layer (SBL) on one to four sides or any side, can be easily applied to the corresponding CMOS SOI technology.

Figure 6b shows a cross-sectional view of another embodiment 45 of a junction diode for a program selector using fin field effect transistor (FinFET) technology. FinFET refers to a finned (FIN)-based multi-gate transistor. FinFET technology is similar to traditional CMOS, but has tall, thin silicon islands that are raised above a silicon substrate to serve as the body of the CMOS element. The main body is like in traditional CMOS, divided into source, drain and channel of polysilicon or non-aluminum metal gate. The main difference is that in FinFET technology, the body of the MOS element is lifted above the substrate, and the height of the island is equal to the width of the channel, although the direction of current flow is still parallel to the surface of the silicon. Figure 6b shows an example of FinFET technology, the silicon substrate 35 is an epitaxial layer built on top of an insulating layer like SOI or other high resistance silicon substrate. The silicon base 35 can be etched into several tall rectangular island-like regions 31-1, 31-2 and 31-3. With proper gate oxide growth, the island regions 31-1, 31-2 and 31-3 can cover both sides of the raised island region with MOS gates 39-1, 39-2 and 39-3, respectively. and define the source and drain regions. The source and drain regions are formed in the island regions 31-1, 31-2 and 31-3, and then filled with silicon, such as filling in the silicon region 40-1 and the silicon region 40-2, so that the combined source and drain The area is large enough to place contacts. In FIG. 6 b , the filled regions of the silicon regions 40 - 1 and 40 - 2 are only used to illustrate and reveal the cross-section. For example, the filled regions can be filled to the surfaces of the island regions 31 - 1 , 31 - 2 and 31 - 3 . In this embodiment, the active regions 33-1, 2, 3 and 37-1, 2, 3 are respectively covered by the P+ implant layer 38' and the N+ implant layer (complementary to the P+ implant layer 38) to form junctions The P and N terminals of the diode 45 are not entirely covered by the P+ implant layer 38 like the PMOS of the conventional FinFET. N+ active regions 37-1, 2, 3 are coupled to a low voltage supply V-. Resistive elements (not shown in FIG. 6b ), such as phase change films, are coupled to the P+ active regions 33 - 1 , 2 , 3 at one end and to the high voltage power supply V+ at the other end. To program the e-fuse, high and low voltages are applied to V+ and V-, respectively, to conduct a large current through the resistive element and junction diode 45 to program the resistive element. Other implementations of isolation in CMOS body technologies, such as Shallow Trench Isolation (STI) or dummy CMOS gates, or silicide barrier layers (SBL), can be easily applied to the corresponding FinFET technologies.

FIG. 7 shows a cross-sectional view of a programmable resistive element memory cell 40 . According to this embodiment, a phase change material (Phase Change Material) is used as the resistive element 42, with buffer metals 41 and 43, and a P+/N well diode 32. According to this embodiment, the P+/N well diode 32 has a P+ active region 33 and an N+ active region 37, which serve as the P and N terminals of the diode on the N well 34, respectively. The isolation between the P+ active area 33 and the N+ active area 37 is an STI 36. The P+ active region 33 of the diode 32 is coupled to an underlying metal 41 as a buffer layer via a contact fill 40-1. The underlying metal 41 is coupled to a thin film 42 of phase change material (such as a GST thin film) via a contact filler 40-2. An upper layer metal 43 is also coupled to the thin film 42 of phase change material. The upper metal 43 is coupled to another metal 44 of the bitline (Bitline) through a contact filler 40-3. The phase change film 42 can have the following chemical composition: germanium (Ge), antimony (Sb) and tellurium (Te); such as GexSbyTez (x, y and z are arbitrary numbers), or as an example Ge2Sb2Te5 (GST-225). GST can be doped with at least one or more of indium (In), tin (Sn) or selenium (Se) to improve performance. The phase change memory cell structure can be substantially planarized. This means that the area of the phase change film 42 is larger than the contact area coupled to the program selector film, or the height from the surface of the silicon substrate to the phase change film 42 is much smaller than the dimension of the film parallel to the silicon substrate. In this embodiment, the active area of the phase change film 42 is much larger than the contact area, so that the programming characteristics can be more uniform and repeatable. The phase change film 42 is not a vertical structure, and is not located on a tall contact, so it can be more suitable for the application of the embedded phase change memory, especially when the diode 32 (ie, the junction diode) is used as a programming selector, the size of the memory cell can be reduced. very small. Those skilled in the art know that the structure and manufacturing process may be different, and the above-mentioned phase change film (such as GST film) structure and buffer metal are for illustrative purposes only.

Figure 8 shows a top view of a phase change material (Phase Change Material) storage unit. According to this example, the memory cell has a junction diode as a program selector with a boundary of 80. The phase-change material storage unit has a P+/N well diode and a phase-change material element 85, which may be a GST film. The P+/N well diode has active regions 83 and 81 covered by a P+ implant layer 86 and an N+ implant layer (complementary to the P+ implant layer 86) respectively, serving as an anode and a cathode, respectively. Both active regions 81 and 83 exist in the same N-well 84 . This N-well can be used for the body of PMOS in standard CMOS process. The anode is coupled to phase change material 85 via first layer metal 82 . The phase change material 85 is further coupled to a vertically oriented third level metal bit line (BL) 88 . The cathode of the P+/N well diode (that is, the active region 81 ) is connected by the second metal word line 87 in the horizontal direction. By applying an appropriate voltage between bit line 88 and word line 87 for an appropriate time period, phase change material 85 can be programmed to a corresponding 0 or 1 state. Since the programming of the phase-change material memory cell is based on temperature rise, rather than the electromigration of the electric fuse, the anode and cathode of the phase-change film (eg, GST film) can have symmetrical areas. Those skilled in the art know that the phase change film, structure and wiring style, and metal structure may be different in other embodiments.

Programming phase change memory (PCM), such as phase change films, depends on the physical properties of the phase change film, such as glass transition temperature and melting temperature. To reset (write 1), it needs to be heated above the melting temperature and then cooled down abruptly. To set (write 0), the phase change film needs to be heated to a temperature between melting and glass transition, then annealed. The glass transition temperature of a typical phase change material film is about 200 degrees Celsius, and the melting temperature is about 600 degrees Celsius. These temperatures determine the operating temperature of the phase change memory (PCM), since the resistive state may change over a long period of time at a particular temperature. But most applications need to retain data for 10 years, from the operating temperature of 0 to 85°C or -40 to 125°C. In order to maintain the stability of the memory cell over such a wide temperature range and over the lifetime of the element, phase change memory can be periodically read out and then written back to the same memory cell as a refresh mechanism. The update period may be quite long, such as more than a second (eg, minutes, hours, days, weeks, or even months). The update mechanism can be generated inside the memory or triggered from outside the memory. The long refresh cycle to maintain the stability of the memory cell can also be applied to other emerging memories such as resistive memory (RRAM), conductive bridge random access memory (CBRAM) and phase change memory (PCM) wait.

According to another embodiment, programmable resistive elements may be used to create memory. According to this embodiment, FIG. 9 shows a part of the programmable resistance memory 100, an array 101 of single diode memory cells 110 of n columns x (m+1) rows and n word line drivers 150-i (i= 0, 1, ..., n-1). The memory array 101 has m normal rows and a reference row, which share a sense amplifier for differential sensing. For each memory storage unit 110 of those memory storage units 110 in the same row, a resistive element 111 is coupled to the P terminal of a diode 112 of the program selector and to the bit line BLj 170-j (j=0, 1, ..m-1) or reference bit line BLR0 175-0. The N terminals of the diodes 112 in the same column for those memory storage cells 110 are coupled to a word line WLBi 152-i via a local word line LWLBi 154-i (i=0, 1, . . . , n-1), . Each word line WLBi is coupled to at least one local word line LWLBi (i=0, 1, . . . , n−1). The LWLBi 154-i is usually constructed of high-resistance material (such as N-well or polysilicon) to connect memory cells, and then via contacts or interlayer contacts, buffers, or post-decoders 172-i (i=0, 1, . . . . , n-1) coupled to WLBi (eg, low resistance metal WLBi). When using a diode as a program selector, a buffer or post-decoder 172-i may be required due to the current flowing through the WLBi; especially in other embodiments where a WLBi drives multiple memory cells for simultaneous programming and reading . The word line WLBi is driven by a word line driver 150-i, and its power supply voltage vddi can be switched between different voltages for programming and reading. Each BLj 170-j or BLR ₀ 175-0 is coupled to a power supply voltage VDDP via a Y-write channel gate 120-j or 125 for programming, and is programmed by the selected YSWBj (j=0, 1, . ., m-1) or YSWRB ₀ . Gates 120-j (j=0, 1, ..., m-1) or 125 in Y-write channel can be constructed by PMOS, however NMOS, diode or bipolar devices can also be used in some embodiments . Each BL or BLR ₀ is coupled to the data line DLj or the reference data line DLR ₀ via a Y-read channel gate 130-j or 135, respectively by YSRj (j=0, 1, .., m-1) or YSRR ₀ selected. In the memory array 101 part, m normal data lines DLj (j=0, 1, . . . , m−1) are connected to an input terminal 160 of a sense amplifier 140 . The reference data line DLR ₀ provides the other input 161 of the sense amplifier 140 (generally no multiplexer is required in the reference section). The output of sense amplifier 140 is Q ₀ .

To program a memory cell, specific WLBi and YSWBj are turned on and a high voltage is supplied to VDDP (i=0, 1, . . . , n-1 and j=0, 1, . . . , m-1). In some embodiments, the reference memory cell can be programmed to 0 or 1 by turning on WLRBi (i=0, 1, . . . , n−1) and YSWRB ₀ . To read a memory cell, data column line DLj 160 can be enabled by specific WLBi and YSRj (where i=0,1,...,n-1, and j=0,1,...,m-1 ), and a reference data line DLR ₀ 161 can be selected by enabling a specific reference memory cell, both of which are coupled to the sense amplifier 140 . This sense amplifier 140 can be used to sense and compare the difference in resistance between DL and DLR ₀ and ground while turning off all YSWBj and YSWRB ₀ (j=0, 1, . . . , m−1).

Figures 10a and 10b show an embodiment of a flowchart depicting a programming method 700 and a reading method 800 for a programmable resistive memory, respectively. Methods 700 and 800 describe the programming and reading of the programmable resistive memory 100 shown in FIG. 9 in the case of a programmable resistive memory. In addition, although it is a flow of steps, those skilled in the art know that at least some steps may be performed in a different order, including simultaneously or skipped.

FIG. 10a depicts a flowchart of a programming method 700 for a programmable resistive memory. According to this embodiment, in a first step 710, an appropriate power selector is selected to apply high voltage power to the wordline and bitline drivers. In a second step 720, an analysis is performed in the control logic (not shown in FIG. 9) of the data to be programmed, according to what type of programmable resistive element. For phase change memory (PCM), programming to a 0 (set) and programming to a 1 (reset) require different voltages and durations, so a control logic determines the input data and selects the appropriate power selector and initiate appropriate timing control signals. In a third step 730, a column (group) of memory cells is selected so that the corresponding local word line can be turned on. In a fourth step 740, the sense amplifier is disabled to save power and prevent interference with programmed operation. In a fifth step 750, a row (group) of memory cells may be selected and the corresponding Y-write channel gate may be opened to couple the selected bit line (group) to a supply voltage. In a final step 760, the desired current is driven through the established conduction path for the desired time to complete the programmed operation. For most programmable resistive memories, this conduction path is driven by a high-voltage power supply, through the selected bit line (group), the resistive element, the diode as the program selector, and the NMOS pull-down element of the local word line driver (group) to the grounded.

FIG. 10b is a flowchart of a reading method 800 for a programmable resistance memory. In a first step 810, appropriate power selectors are provided to select power supply voltages for local word line drivers, sense amplifiers and other circuits. In a second step 820, all Y-write channel gates, such as bit line program selectors, may be turned off. In a third step 830, the desired local word line driver(s) may be selected such that the diode(s) acting as program selector(s) have a conduction path to ground. In a fourth step 840, the sense amplifier is enabled and the input signal is prepared for sensing. In a fifth step 850, the data line and the reference data line are precharged to the V-voltage of the programmable resistive element memory cell. In a sixth step 860, the desired Y-read channel gate is selected such that the desired bit line is coupled to an input of the sense amplifier. A conductive path is then established from the bit line (group) to the resistive element of the desired memory cell, the diode (group) as program selector (group) and the pull-down element of the local word line driver (group) to ground. The same applies to reference branches. In the last step 870, the sense amplifier can compare the difference between the read current and the reference current to determine whether the logic output is 0 or 1 to complete the read operation.

FIG. 11 shows an embodiment of a processor system 700 . According to this embodiment, processor system 700 may include a programmable resistive element 744 in memory cell array 742 in memory 740 . Processor system 700 may, for example, belong to a computer system. The computer system may include a central processing unit (CPU) 710 that communicates via a common bus 715 with various memory and peripheral devices, such as an input output unit 720, hard drive 730, optical disk 750, memory 740, and other memory 760. The other memory 760 is a traditional memory such as static access memory (SRAM), dynamic access memory (DRAM) or flash memory (flash), and usually communicates with the CPU 710 through a memory controller. The central processing unit 710 is generally a microprocessor, digital signal processor or other programmable digital logic elements. The memory 740 is preferably implemented as an integrated circuit including a memory array 742 having at least a programmable resistive element 744 . Typically, the memory 740 contacts the CPU 710 via a memory controller. If desired, memory 740 can be combined with a processor (eg, central processing unit 710 ) on a single integrated circuit.

The invention may be implemented partially or fully on an integrated circuit, on a printed circuit board (PCB), or on a system. The programmable resistance element can be a fuse, an anti-fuse, or a new non-volatile memory. The fuses may be silicided or non-silicided polysilicon fuses, thermally isolated active area fuses, metal fuses, contact fuses, or interlayer contact fuses. The antifuse may be a gate oxide breakdown antifuse, a dielectric-in-between junction, or an interlayer junction antifuse. The emerging non-volatile memory can be Magnetic Access Memory (MRAM), Phase Change Memory (PCM), Conductive Bridge Random Access Memory (CBRAM), or Resistive Random Access Memory (RRAM). Although the programming mechanism is different, its logic state can be distinguished by different resistor values.

Certainly, the present invention also can have other multiple embodiments, without departing from the spirit and essence of the present invention, those skilled in the art can make various corresponding changes and deformations according to the present invention, but these corresponding Changes and deformations should belong to the scope of protection of the appended claims of the present invention.

Claims (14)

1. A reversible resistance memory unit, characterized in that it comprises: a plurality of diversified reversible resistance memory units, at least one reversible resistance memory unit comprising: a reversible resistive element coupled to the first supply voltage line; and A diode includes at least a first active region and a second active region, wherein the first active region has a first type of doping, the second active region has a second type of doping, and the first active region provides provides a first end of the diode, the second active region provides a second end of the diode, both the first active region and the second active region have a common well region, and the first active region is coupled to the reversible resistive element, and the second active region is coupled to a second supply voltage line; wherein the first and second active regions are fabricated from a source or drain of a metal oxide semiconductor transistor element, and the well is fabricated from a metal oxide semiconductor transistor well; The two active regions are used as two ends of the diode, separated by a dummy metal oxide semiconductor gate; Wherein the reversible resistance element and the diode jointly form a two-terminal element, connected between the first power supply voltage line and the second power supply voltage line; The reversible resistive element is constructed to be programmable, with a high voltage and application of the high voltage for a short duration setting the reversible resistive element into one state, and a low voltage and application of the low voltage for a long duration enabling the reversibility resistive element to another state. 2. The reversible resistance memory cell according to claim 1, wherein the reversible resistance element is a phase-change thin film comprising germanium, antimony and tellurium. 3. The reversible resistance memory cell according to claim 1, characterized in that the reversible resistance element is a phase-change thin film comprising chemical components germanium, antimony and tellurium, and can be doped with at least one or more of indium, tin or selenium. 4. The reversible resistance memory cell according to claim 1, wherein the reversible resistance element is an electrode and a metal oxide between the electrodes, wherein the electrode is a metal electrode or a metal alloy electrode. 5. The reversible resistance memory cell according to claim 1, wherein the reversible resistance element is an electrode and a solid electrolyte film between the electrodes. 6. The reversible resistive memory cell according to claim 1, wherein the reversible resistive elements are separated from each other in different memory cells. 7. The reversible resistance memory cell according to claim 1, wherein the reversible resistance element is planarized. 8. The reversible resistance memory unit according to claim 1, wherein the reversible resistance element is a reversible resistance film, the area A of the reversible resistance film, the diode is formed in a silicon substrate, and the reversible resistance film is coupled to A contact on the surface of the silicon substrate, the area of the contact is B, and A and B satisfy the relationship: A/B>2. 9. The reversible resistance memory cell according to claim 1, wherein the reversible resistance element is a reversible resistance film, and the reversible resistance film has at least one dimension whose length is greater than The height from the silicon surface to the film. 10. The reversible resistive memory cell of claim 1, wherein the reversible resistive film is configured to be programmed by current limiting or voltage limiting used. 11. A phase-change memory, characterized in that, comprising: A plurality of diversified phase-change memory cells, at least one phase-change memory cell includes: a phase change film coupled to the first supply voltage line; and A diode includes at least a first active region and a second active region, wherein the first active region has a first type of doping, the second active region has a second type of doping, and the first active region provides A first end of the diode is provided, the second active region provides a second end of the diode, a common well region exists for both the first active region and the second active region, the first active region is coupled to the a phase change film, the second active region being coupled to a second supply voltage line; wherein the first and second active regions are fabricated from a source or drain of a metal oxide semiconductor transistor element, and the well is fabricated from a metal oxide semiconductor transistor well; Wherein, by applying a voltage to the first and second power supply voltage lines, the phase change film can reversibly change the resistance to different logic states, thereby being configured as programmable The two active regions are used as two ends of the diode, separated by a dummy metal oxide semiconductor gate; Wherein the phase change film and the diode jointly form a two-terminal element, connected between the first power supply voltage line and the second power supply voltage line; The phase change film is constructed to be programmable, with a high voltage and application of the high voltage for a short duration bringing the phase change film into one state, and a low voltage and application of the low voltage for a long duration bringing the phase change film into another state. 12. An electronic system, characterized in that it comprises: a processor; and A reversible resistive memory is operatively connected to the processor, the reversible resistive memory includes a plurality of reversible resistive memory cells for data storage, each reversible resistive memory cell includes: a reversible resistive element coupled to the first supply voltage line; and A diode comprising at least a first active region and a second active region, wherein the first active region has a first type of doping, the second active region has a second type of doping, the first active region provides the a first end of the diode, the second active region provides a second end of the diode, a common well region exists for both the first and second active regions, the first active region is coupled to the reversible resistive element and the second active region is coupled to a second supply voltage line; wherein the first and second active regions are fabricated from a source or drain of a metal oxide semiconductor transistor element, and the well is fabricated from a metal oxide semiconductor transistor well; The two active regions are used as two ends of the diode, separated by a dummy metal oxide semiconductor gate; Wherein the reversible resistance element and the diode jointly form a two-terminal element, connected between the first power supply voltage line and the second power supply voltage line; The reversible resistive element is constructed to be programmable, with a high voltage and/or short duration placing the reversible resistive element into one state and a low voltage and/or long duration placing the reversible resistive element into another state . 13. The electronic system of claim 12, wherein the electronic system is configured to periodically read the contents of each storage unit and write back the contents. 14. A method for providing a reversible resistive memory cell, comprising: A plurality of reversible resistive memory cells is provided, at least one reversible resistive memory cell comprising at least (i) a reversible resistive element coupled to a first supply voltage line; and (ii) a diode comprising at least a first active region and a The second active region, the first active region has a first type of doping, the second active region has a second type of doping, the first active region provides a first end of the diode, the second active region provides A second end of the diode, the first and second active regions are both fabricated from the source or drain of the MOS transistor element, and there is a common well region, which is derived from the MOS transistor Well fabrication, the first active region is coupled to the resistive element and the second active region is coupled to a second power supply voltage line; the two active regions are used as two ends of a diode, and a dummy metal oxide semiconductor gate separate; wherein the reversible resistance element and the diode jointly form a two-terminal element connected between the first power supply voltage line and the second power supply voltage line; and The reversible resistive memory cell is brought to one state by a high voltage and applied for a short duration, and is brought to another state by a low voltage and applied for a long duration.