CN104425626A - Programmable device and its manufacturing method - Google Patents

Abstract

The invention discloses a programmable device and a manufacturing method thereof. A programmable device includes: a substrate having a source region, a drain region, and a diffusion region adjacent to the source region and the drain region; a channel connecting the source region and the drain region; a floating gate formed of a conductive material and located on the substrate corresponding to the channel; and a trench formed at the diffusion region of the substrate. The floating gate extends to the trench, and the conductive material covers a sidewall of the trench.

Description

Programmable device and its manufacturing method

technical field

The present invention relates to a programmable device and its manufacturing method, and in particular to a programmable device with improved coupling rate and its manufacturing method.

Background technique

For the semiconductor industry, in addition to continuously reducing the size of semiconductor structures, improving the speed, performance, density and cost reduction of integrated circuits are all important development goals. In the development of semiconductor technology, multiple times programmable (Multiple Times Programmable, MTP) memory has been applied in many aspects and has advantages in application. Relevant industry players all hope to increase the programming speed and erasing speed of MTP devices at least while maintaining the existing device size, or to better reduce the size, and to pursue better electronic characteristics of the device.

Contents of the invention

The object of the present invention is to provide a programmable element and its manufacturing method, by forming a trench in the diffusion region, and depositing the conductive material of the floating gate on the side wall of the trench, so that the floating gate and the diffusion region The coupling area (coupling area) between increases, thus increasing its coupling ratio (couplingratio). The electronic characteristics of the components can be greatly improved.

According to an embodiment, a programmable device is provided, comprising: a substrate having a source region, a drain region, and a diffusion region adjacent to the source region and the drain region; a channel connecting the source region and the drain a pole region; a floating gate formed of a conductive material and located on the substrate corresponding to the channel; and a trench formed at the diffusion region of the substrate. Wherein, the floating gate extends to the trench, and the conductive material covers a side wall of the trench.

According to an embodiment, a method for manufacturing a programmable device is proposed, including: providing a substrate, the substrate has a source region, a drain region, and a diffusion region adjacent to the source region and the drain region, wherein a channel is connected source region and drain region; forming a trench at the diffusion region of the substrate; and forming a floating gate on the substrate with a conductive material, the floating gate extending to the trench so that the conductive material covers a portion of the trench side wall.

In order to have a better understanding of the above-mentioned and other aspects of the present invention, the following specific embodiments are described in detail as follows in conjunction with the accompanying drawings:

Description of drawings

FIG. 1 is a side view of a part of a programmable device according to an embodiment of the present invention;

Fig. 2 is a top view of a part of a programmable device according to an embodiment of the present invention;

Fig. 3 is a diagram illustrating a layout design of an embodiment of the present invention, wherein adjacent structures/units are arranged oppositely up and down along the row direction of the layout;

FIG. 4 is another layout design illustrating the application of the embodiment of the present invention, wherein adjacent structures/units share a trench in the row direction (column direction) of the layout;

FIG. 5 is a flow chart of a method for manufacturing a programmable device according to an embodiment of the present invention;

FIG. 6 is a flow chart of another programmable device manufacturing method according to another embodiment of the present invention;

7A is a top view of a conventional multi-time programmable memory cell without trenches in simulation experiment 1;

7B is a top view of a multiple-time programmable memory cell with trenches as described in the embodiment in simulation experiment 1;

8A is a top view of a conventional multiple-time programmable memory cell without trenches in simulation experiment 2;

FIG. 8B is a top view of a multiple-time programmable memory cell with trenches according to the embodiment in simulation experiment 2. FIG.

Symbol Description

10: Substrate

11: channel

12: Shallow trench isolation

12a: first groove

13, 23: Groove

13a, 23a: an opening edge of the groove

16, 26: floating gate

17, 27: Lightly doped drain implantation region

18, 28: Diffusion area

19: Doped area

3-1, 4-1: The first structure/unit

3-2, 4-2: Second structure/unit

S, S1, S2: source region

D, D1, D2: Drain region

501, 503, 507, 601, 603, 604, 605, 607: steps

Detailed ways

The invention provides a programmable device and its manufacturing method. According to an embodiment, a plurality of trenches are respectively formed at the diffusion region of the programmable device and extend downward from the substrate, and conductive materials are deposited in the trenches. Therefore, the coupling area between the floating gate and the diffusion region of the programmable device can be increased, thereby improving the coupling ratio of the device. Accordingly, the programming speed and erasing speed of the programmable device manufactured by the manufacturing method of the embodiment can be greatly improved, thereby improving the electronic characteristics of the device.

The present invention can be applied to a multiple time programmable (MTP) memory cell, forming trenches in its diffusion region. The manufacturing method of the embodiment can be modified and changed according to the actual application procedure, and there are some differences. For example, the trenches of the embodiments may be formed simultaneously during trench patterning in a shallow trench isolation (silicon trench isolation, STI) manufacturing process. In addition, the trenches of an embodiment may be formed after the shallow trench isolation process. Furthermore, embodiments of the present invention can be applied to different layout designs. The following embodiments describe the relevant structure and manufacturing process of the present invention with reference to the accompanying drawings, but the present invention is not limited thereto. In the embodiments, the same or similar symbols are used to indicate the same or similar parts.

It should be noted that not all possible embodiments of the present invention are shown. Changes and modifications can be made to the structure and manufacturing process without departing from the spirit and scope of the present invention, so as to meet the needs of practical application of the manufacturing process. Therefore, other implementation aspects not proposed in the present invention may also be applicable. Furthermore, the size ratios on the drawings are not drawn to the same scale as the actual product. Therefore, the specification and illustrations are only used to describe the embodiments, not to limit the protection scope of the present invention.

Please refer to Figure 1 and Figure 2 at the same time. FIG. 1 is a side view of a part of a programmable device according to an embodiment of the present invention. FIG. 2 is a top view of a part of a programmable device according to an embodiment of the present invention. In one embodiment, a programmable device includes a substrate 10 having a source region S, a drain region D, and a diffusion region (diffusion region) 18 adjacent to the source region S and the drain region D; a channel 11 Connecting the source region S and the drain region D; a floating gate (floating gate) 16, formed with a conductive material, the floating gate 16 is located on the substrate 10 and corresponds to the channel 11; and a trench (trench) 13 is formed at the diffusion region 18 of the substrate 10 . The floating gate 16 extends to the trench 13 , and the conductive material of the floating gate 16 covers a sidewall of the trench 13 . Since the floating gate 16 extends to the trench 13 , the trench 13 is electrically connected to the floating gate 16 .

In one embodiment, the programmable device may include a plurality of shallow trench isolations (STIs) 12 on the substrate 10 . The substrate 10 has a doped region 19 such as an N+ region. In one embodiment, the trench 13 can be formed simultaneously when the trench is patterned (drilled) in the shallow trench isolation process. However, the present invention is not limited thereto. In other embodiments, the trench 13 may also be formed after the shallow trench isolation is completed. The manufacturing method of the programmable device will be described in the following paragraphs.

In one embodiment, the conductive material of the floating gate 16 covers sidewalls and a bottom surface of the trench 13 , as shown in FIGS. 1 and 2 . The conductive material can form a lining layer of the trench 13 ( FIG. 1 ), or completely fill the trench 13; the application of the present invention is not limited. In one embodiment, when a programmable voltage is across the source region S and the drain region D, the drain region D is capacitively coupled to the floating gate 16 due to the conductive material covering the sidewalls of the trench 13 with the conductive material at trench 13.

Furthermore, the filling area of the conductive material at the trench 13 can be substantially equivalent to an opening area of the trench 13; . Therefore, in one embodiment, a distal end of the conductive material may be substantially aligned with the opening edge 13 a of the trench 13 . In other embodiments, the filling area of the conductive material at the trench 13 can also be slightly larger than an opening area of the trench 13; for example, the conductive material deposited on the sidewall and bottom of the trench 13 can slightly overflow the trench 13, but Do not go beyond the diffusion area 18 . FIG. 1 and FIG. 2 illustrate an embodiment in which a distal end of the conductive material slightly exceeds the opening edge 13 a of the trench 13 .

Moreover, the programmable device in one embodiment may further include an insulating layer 15 formed on the sidewall of the trench 13 , and a conductive material is formed on the insulating layer 15 . In practical applications, a tunneling oxide or a liner oxide formed between the conductive material and the trench 13 can be used as the insulating layer 15 .

Furthermore, in an embodiment, the programmable device may further include a lightly doped drain (LDD) implant area 17 formed on the substrate 10 and corresponding to the diffusion area 18 . Depending on the situation of the actual application device, it is selectively determined whether to perform the step of forming the lightly doped drain implant. For example, if the N+ region (including the source and drain regions S/D) of the programmable device (such as the MTP memory cell) has sufficient doping concentration, the step of forming the lightly doped drain implant can be omitted. If the doping concentration of the N+ region (including the source and drain regions S/D) of the programmable device is low, forming the lightly doped drain implantation region 17 also helps to increase the programming/erasing speed of the device.

According to the above-mentioned embodiment, by forming a trench at the diffusion region (the trench extends downward from the substrate), and depositing conductive material in the trench 13, the floating gate of the programmable element (such as an MTP memory cell) can be increased. The coupling area between pole 16 and diffusion region 18. In an embodiment, the conductive material deposited in the trench 13 may be the same as that of the floating gate 16 . Therefore, the coupling area between the floating gate 16 and the diffusion region 18 of the embodiment can increase at least part of the sidewall area of the trench 13 (for example, increase the area of four sidewalls in one trench), thereby improving the programmable device. The coupling rate, thereby increasing the programming speed and erasing speed of the programmable device.

[layout]

Various device layout designs can be constructed using the embodiments of the present invention. Two of them are proposed below to illustrate the layout application, but the application of the present invention is not limited thereto.

FIG. 3 shows a layout design of an embodiment of the present invention, wherein adjacent structures/units are arranged oppositely up and down along the row direction of the layout. FIG. 4 shows another layout design applying the embodiment of the present invention, wherein adjacent structures/units up and down share a trench in the column direction of the layout. The arrangement shown in FIG. 4 can achieve a more compact and space-saving layout design.

In FIG. 3, the programmable device includes a first structure/unit 3-1 (as shown in FIG. 1 and FIG. 2) and a second structure/unit 3-2 as described above. The second structure/unit 3-2 includes another source region S2, another drain region D2 and another diffusion region 28 formed on the substrate 10, and the source region S2 and the drain region of the second structure/unit 3-2 The electrode region D2 is arranged adjacent to the source region S1 and the drain region D1 of the first structure/unit 3-1 along a row direction. The second structure/unit 3 - 2 also includes another trench 23 formed at the diffusion region 28 of the substrate 10 , and another floating gate 26 formed of a conductive material and extending to the trench 23 . As shown in Fig. 3, the trenches 13 of the first structure/unit 3-1 and the trenches 23 of the second structure/unit 3-2 are arranged on different columns of the layout.

In FIG. 4 , the programmable device includes a first structure/unit 4-1 (the structure shown in FIG. 1 and FIG. 2 ) and a second structure/unit 4-2 as described above. Wherein, two adjacent structures/units share a groove in the row direction, so as to achieve a more closely arranged layout. The second structure/unit 4-2 includes another source region S2 and another drain region D2 formed on the substrate 10, along with the source region S1 and the drain region D1 of the first structure/unit 4-1. Arranged in a row direction (column direction). As shown in FIG. 4 , the trench 13 is located between the source region S2 and the drain region D1 of the first structure/unit 4-1 and the source region S1 and the drain region D2 of the second structure/unit 4-2. The second structure/cell 4 - 2 also includes another floating gate 26 extending to the trench 13 and coupled with the conductive material of the trench 13 . In one embodiment, floating gates 16 and 26 may be formed simultaneously by forming and patterning the same conductive material.

[Manufacturing method]

The manufacturing method of the programmable device of the embodiment is described below. However, the following descriptions do not represent all possible implementations of manufacturing methods of the present invention. In the embodiments, appropriate modifications and changes can be made to the relevant steps according to actual application requirements without departing from the spirit and scope of the present invention.

FIG. 5 is a flow chart of a method for manufacturing a programmable device according to an embodiment of the present invention. Please refer to Figure 1 and Figure 2 at the same time. Figure 5 illustrates the generalized steps involved in, but not limited to, embodiments of the present invention. Step 501, providing a substrate 10 having a source region S, a drain region D and a diffusion region 18, wherein the diffusion region 18 is adjacent to the source region S and the drain region D, and a channel 11 is coupled to the source region S and the drain region D.

In one embodiment, the manufacturing method of the programmable device may optionally include: forming a lightly doped drain (LDD) implant area 17 on the substrate 10 and corresponding to the diffusion area 18 (as shown in FIG. 2 shown) to enhance the electronic characteristics of the component.

In step 503 , at least one trench 13 is formed at the diffusion region 18 of the substrate 10 . In one embodiment, the manufacturing method of the programmable device may optionally include: forming an insulating layer 15 such as a tunnel oxide layer or a liner oxide layer on the sidewall of the trench 13 .

Step 507 , forming a floating gate 16 on the substrate 10 , the floating gate 16 extends to the trench 13 , and the conductive material of the floating gate 16 covers a sidewall of the trench 13 . For example, the conductive material covers the sidewalls and a bottom surface of the trench 13 and may be formed in the trench 13 as a liner.

For the embodiment in which the sidewalls of the trench 13 have an insulating layer 15 , the conductive material is formed on the insulating layer 15 . In one embodiment, the conductive material (such as polysilicon) in the trench 13 covers at least the sidewall of the trench 13 . In one embodiment, an end of the conductive material may substantially correspond to an opening edge of the trench, for example align with or slightly exceed the opening edge of the trench.

Furthermore, the programmable device in one embodiment may include a plurality of shallow trench isolations (STIs) 12 on the substrate 10 . The trench 13 of the embodiment can be formed simultaneously in the patterning step of the shallow trench isolation 12 , and then the dielectric material (ie, the material used to fill the trench to complete the STI) in the trench 13 is replaced with a conductive material. In addition, the trench 13 of the embodiment can also be formed after the STI manufacturing process. The present invention does not limit this much. FIG. 6 is a flow chart of another programmable device manufacturing method according to another embodiment of the present invention. Please refer to Figure 1 and Figure 2 at the same time. It should be noted that FIG. 6 is only one of various implementation methods, and its content is for illustration only, and is not intended to limit the scope of the present invention.

Step 601, similarly, provide a substrate 10, which has a source region S, a drain region D and a diffusion region 18, the diffusion region 18 is adjacent to the source region S and the drain region D, wherein a channel 11 is coupled source region S and drain region D.

In step 603 , at least one trench 13 is formed on the diffusion region 18 of the substrate 10 and a first trench 12 a is formed on the substrate 10 at the same time.

Step 604 , filling a dielectric material in the first trench 12 a to form an isolation trench such as STI 12 , and the trench 13 at the diffusion region 18 is also filled with a dielectric material.

Step 605 , removing the dielectric material in the trench 13 .

Step 607 , using a conductive material to form a floating gate 16 on the substrate 10 , the floating gate 16 extends to the trench 13 , and the conductive material covers a sidewall of the trench 13 . In this way, the step of replacing the dielectric material with the conductive material in the trench is completed.

Similarly, an insulating layer 15 (such as a tunnel oxide layer) can be formed on the sidewall of the trench 13 before forming the conductive material. Furthermore, before depositing the dielectric material, a liner oxide layer can also be optionally formed on the first trench 12a and the trench 13, and when the step of removing the dielectric material in the trench 13 is performed, the trench can be retained. The liner oxide layer in the trench 13 is used as the insulating layer 15 .

According to the manufacturing method of FIG. 6, the trench 13 of the embodiment is formed together with the trench of the STI, and the dielectric material filled in the trench 13 due to the STI manufacturing process is then removed, and then, for example, a tunnel oxide layer ( As an optional step, this step can be omitted if the trench 13 already has a liner oxide layer), and filling the trench 13 with conductive material (such as polysilicon for the floating gate 16 ). However, the trench 13 may also be fabricated after the STI fabrication process is completed. Therefore, the steps described above do not represent all the steps in the embodiment, and relevant steps can be appropriately adjusted and changed according to conditions and requirements during actual application.

[Improvement of coupling area and simulation experiment]

The improvement of the coupling area in the embodiments of the present invention will be described below by means of mathematical analysis, and two sets of simulation experiments will be proposed for comparison and illustration.

For a conventional MTP memory cell (without trench), a coupling area between the floating gate and the diffusion region can be expressed as:

L*W ……………………………(1)

For an MTP memory cell of an embodiment (with a trench, and it is assumed that the trench has four sidewalls), a coupling area between the floating gate and the diffusion region can be expressed as:

L*W+(L+W)*d*2 ………………….(2)

Wherein, D is the depth of the trench, L is the length of the coupling area between the trench and the gate, and W is the width of the coupling area.

Comparing equations (1) and (2), the increase range of the coupling area of the MTP memory cell of the embodiment can be expressed as:

$\frac{\mathrm{<span\; class="notranslate">\; L</span>}<span\; class="notranslate">\; *</span>\mathrm{<span\; class="notranslate">\; W</span>}<span\; class="notranslate">\; +</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; L</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; W</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; *</span>\mathrm{<span\; class="notranslate">\; d</span>}<span\; class="notranslate">\; *</span>\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; L</span>}<span\; class="notranslate">\; *</span>\mathrm{<span\; class="notranslate">\; W</span>}}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; =</span>\frac{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; L</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; W</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; *</span>\mathrm{<span\; class="notranslate">\; d</span>}<span\; class="notranslate">\; *</span>\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; L</span>}<span\; class="notranslate">\; *</span>\mathrm{<span\; class="notranslate">\; W</span>}}$

For example, if the depth d of the trench is about 0.4 μm, the coupling area of the MTP memory cell of the embodiment is L*W+(L+W)*0.4*2, and the increased coupling ratio (coupling ratio) is (L+ W)*0.4*2/(L*W).

<Simulation experiment 1>

FIG. 7A is a top view of a conventional multi-time programmable (MTP) memory cell without trenches in simulation experiment 1. FIG. A coupling area between the floating gate and the diffusion region of a conventional MTP memory cell can generally be expressed as L*W. As shown in FIG. 7A , its coupling area is about 1.35 μm ² (=0.5 μm*2.7 μm).

FIG. 7B is a top view of a multiple time programmable (MTP) memory cell with trenches according to the embodiment in simulation experiment 1. FIG. Assume that the depth (d) of the groove is about 0.4 μm, as shown in the figure, the width (W) is about 0.48 μm and the length (L) (=2.7-0.24*2) is about 2.22 μm, and it is assumed that the opposite side walls in the groove have the same area. As shown in FIG. 7B , its coupling area is about 3.51 μm ² (=0.5*2.7+0.48*0.4*2+2.22*0.4*2).

Comparing Figure 7A and Figure 7B and their coupling area analysis results, both have the same overlapping area between the floating gate and the diffusion region, but after forming the trench as described in the embodiment, the coupling area can be changed from 1.35 The μm ² increases to 3.51μm ² , which is 2.6 times that of the traditional MTP memory cell.

<Simulation experiment 2>

FIG. 8A is a top view of a conventional multi-time programmable (MTP) memory cell without trenches in simulation experiment 2. FIG. A coupling area between the floating gate and the diffusion region of a conventional MTP memory cell can generally be expressed as L*W. As shown in FIG. 8A , its coupling area is about 0.642 μm ² (=1.07 μm*0.6 μm).

FIG. 8B is a top view of a multiple time programmable (MTP) memory cell with trenches according to the embodiment in simulation experiment 2. FIG. Assuming that the depth (d) of the groove is about 0.4 μm, the scale in the figure can be estimated: the width of the lower side is about 0.76 μm (=0.87-0.1), and the width of the upper side is about 0.83 μm (=1.07-0.24 ). Furthermore, it is assumed that the left and right sidewalls in the trench in FIG. 8B have the same area for easy calculation. As shown in FIG. 8B , its coupling area is about 1.662 μm ² (=1.07*0.6+0.76*0.4+0.83*0.4+0.48*0.4*2).

Comparing the analysis results of Figure 8A and Figure 8B and their coupling area, both have the same overlapping area between the floating gate and the diffusion region, but after forming the trench as described in the embodiment, the coupling area can be changed from 0.64 The μm ² increases to 1.662μm ² , which is 2.59 times that of the traditional MTP memory cell.

According to the programmable device and its manufacturing method disclosed in the above embodiments, the coupling area between the floating gate and the diffusion region in the programmable device can be effectively increased; accordingly, the coupling ratio of the programmable device can be improved , thus increasing the programming speed and erasing speed of the programmable device. Furthermore, the steps of the manufacturing method of the programmable device are simple and not cumbersome, and are compatible with the existing manufacturing process, so the programmable device of the embodiment is suitable for mass production and fabrication.

The technical features of the present invention can also be applied to other programmable devices with structures different from those of the above-mentioned embodiments, and their detailed structures should be adjusted and changed according to actual application requirements. Therefore, the detailed structures and descriptions shown in FIG. 1 and FIG. 2 are for description rather than limitation of the present invention. Therefore, those skilled in the relevant art know that the structures, layouts, and manufacturing steps proposed in the above embodiments can be properly modified and adjusted according to application conditions and manufacturing requirements.

In summary, although the present invention has been disclosed in conjunction with the above embodiments, they are not intended to limit the present invention. Those skilled in the art to which the present invention belongs can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be defined by the appended claims.

Claims (21)

1. a programmable element, comprising:

Substrate, has the diffusion zone of source region, drain region and this source region contiguous and this drain region;

Passage, connects this source region and this drain region;

Floating grid, is formed with an electric conducting material, and this floating grid to be positioned on this substrate and corresponding with this passage; With

Groove, is formed at this diffusion zone place of this substrate;

Wherein, this floating grid extends to this groove, and this electric conducting material covers a sidewall of this groove.

2. programmable element as claimed in claim 1, wherein this groove is electrically connected this floating grid.

3. programmable element as claimed in claim 1, wherein a tunnel oxide is formed at this sidewall of this groove, and this electric conducting material is formed on this tunnel oxide.

4. programmable element as claimed in claim 1, also comprises a lightly doped drain injection zone in this substrate place and to should diffusion zone.

5. programmable element as claimed in claim 1, wherein this electric conducting material covers this sidewall and a basal surface of this groove, to form a backing layer of this groove.

6. programmable element, wherein an edge of opening of this groove of end substantial alignment of this electric conducting material as claimed in claim 1.

7. programmable element as claimed in claim 1, wherein an end of this electric conducting material is greater than an edge of opening of this groove.

8. programmable element as claimed in claim 1, wherein when a programmable voltage across between this source region and this drain region time, this this drain region of electric conducting material capacitive coupling at least covering this sidewall of this groove is to this electric conducting material of this floating grid and this groove.

9. programmable element as claimed in claim 1, also comprises:

Another source region, another drain region are formed on this substrate, and arrange along a line direction with aforementioned source region and aforementioned drain region, wherein this channel shaped is formed between another this source region, separately this drain region and aforementioned source region, aforementioned drain region; With

Another floating grid, extends to this groove and couples with this electric conducting material of this groove.

10. programmable element as claimed in claim 1, also comprises:

Another source region, another drain region and another diffusion zone are formed on this substrate, and separately this source region and this drain region another are adjacent to aforementioned source region and aforementioned drain region along a column direction and arrange;

Another channel shaped is formed in this diffusion zone place another of this substrate;

Another floating grid, is formed by this electric conducting material, and extends to this groove another;

Wherein, separately this groove and former trenches are arranged in different lines.

The manufacture method of 11. 1 kinds of programmable elements, comprising:

There is provided a substrate, this substrate has source region, a drain region and is close to a diffusion zone of this source region and this drain region, wherein this source region of an expanding channels and this drain region;

Form a groove in this diffusion zone place of this substrate; With

Form a floating grid on this substrate with an electric conducting material, this floating grid extends to this groove makes this electric conducting material cover a sidewall of this groove.

12. manufacture methods as claimed in claim 11, wherein when a programmable voltage across between this source region and this drain region time, this this drain region of electric conducting material capacitive coupling at least covering this sidewall of this groove is to this electric conducting material of this floating grid and this groove.

13. manufacture methods as claimed in claim 11, also comprise formation one tunnel oxide on this sidewall of this groove, this electric conducting material is formed on this tunnel oxide.

14. manufacture methods as claimed in claim 11, also comprise formation one lightly doped drain injection zone in this substrate place and to should diffusion zone.

15. manufacture methods as claimed in claim 11, wherein this electric conducting material covers this sidewall and a basal surface of this groove, to form a backing layer of this groove.

16. manufacture methods as claimed in claim 11, wherein an edge of opening of this groove of end substantial alignment of this electric conducting material.

17. manufacture methods as claimed in claim 11, wherein an end of this electric conducting material is greater than an edge of opening of this groove.

18. manufacture methods as claimed in claim 11, also comprise formation one isolated groove in this substrate place.

19. manufacture methods as claimed in claim 18, also comprise:

Form this groove in this diffusion zone place and one first groove in this substrate simultaneously;

Filling one dielectric material is in this first groove to form this isolated groove, and this groove at this diffusion zone place also inserts this dielectric material; With

This dielectric material of this groove is replaced with this electric conducting material.

20. manufacture methods as claimed in claim 19, the step of wherein replacing this dielectric material of this groove with this electric conducting material comprises:

Remove this dielectric material in this groove; With

Form this electric conducting material at least this side-walls of this groove.

21. manufacture methods as claimed in claim 18, wherein this groove at this diffusion zone place is formed after this isolated groove manufacture craft.