CN104393050A - Method for improving performance of STI (Shallow Trench Isolation) edge epitaxial layer and corresponding semiconductor structure thereof - Google Patents

Abstract

The present invention provides a method for improving the performance of an STI edge epitaxial layer and its corresponding semiconductor structure, the method comprising: sequentially forming a pad oxide layer and a pad nitride layer on a semiconductor substrate, the pad oxide layer The thickness is greater than 100 angstroms; the pad oxide layer and the pad nitride layer are etched to form an opening; an etching process is performed along the opening to form a trench; a dielectric material is filled in the trench to form an STI structure, the upper surface of the STI structure is 100-200 Angstroms higher than the surface of the semiconductor substrate; a gate structure is formed on the semiconductor substrate between the STI structures; an etching process is performed to remove the STI structure and the gate The semiconductor substrate between the pole structures forms an epitaxial opening, and the semiconductor substrate located on the sidewall of the trench is retained; based on the semiconductor substrate on the sidewall of the trench and the semiconductor substrate at the bottom of the epitaxial opening, an epitaxial process is performed to form epitaxial layer. The invention improves the performance of the STI edge epitaxial layer.

Description

Method for improving performance of STI edge epitaxial layer and corresponding semiconductor structure

technical field

The invention relates to the field of semiconductor technology, in particular to a method for improving the performance of an STI edge epitaxial layer and a corresponding semiconductor structure.

Background technique

With the rapid development of VLSI technology, the size of MOSFET devices is continuously reduced, which usually includes the reduction of the channel length of MOSFET devices, the thinning of gate oxide layer thickness, etc. to obtain faster device speed. However, with the development of VLSI technology to the ultra-deep submicron level, especially when the technology node is 90 nanometers and below, reducing the channel length will bring a series of problems. In order to control the short channel effect, it will be in the channel Doping with a higher concentration of impurities will reduce the mobility of carriers, resulting in a decrease in device performance. It is difficult to simply reduce the size of the device to meet the development of large-scale integrated circuit technology. Therefore, stress engineering has been extensively studied to enhance carrier mobility, thereby achieving faster device speeds and satisfying the rules of Moore's law.

From the 1980s to the 1990s, the academic community had already begun to realize heterostructure research based on silicon-based substrates, and it was not until the beginning of this century that commercial applications were realized. There are two representative stress applications, one is the biaxial stress technology (Biaxial Technique) proposed by IBM; the other is the uniaxial stress technology (Uniaxial Technique) proposed by Intel, that is, SMT (Stress Memorization Technology) Tensile stress is applied to the channel of NMOSFET to increase the mobility of electrons, and selective (or embedded) epitaxial growth of silicon germanium SiGe is applied to the channel of PMOSFET to apply compressive stress to improve the mobility of holes, thereby improving the performance of the device.

At present, the research on the silicon germanium epitaxial growth process mainly focuses on how to increase the concentration of germanium in silicon germanium (SiGe). The higher the concentration of germanium, the greater the lattice mismatch, the greater the stress generated, and the greater the impact on carrier mobility. In addition, the shape of silicon germanium develops from U _- type to Σ _- type, and the Σ _- type silicon germanium is closer to the edge of polysilicon, that is, closer to the device channel, the more stress acts on the carrier of the device channel. flow, which significantly improves the performance of the device.

All of the above research and development are based on silicon substrates, that is to say, silicon substrates provide the seeds for the growth of silicon germanium, and silicon germanium grows epitaxially along the crystal lattice of silicon. However, in the semiconductor process, devices are separated by shallow trenches. The trench isolation structure (STI structure) achieves electrical isolation, and the STI structure is filled with silicon dioxide. Therefore, at the edge of the STI structure and the active region, the SiGe epitaxial process will be affected by the STI structure, and the STI structure cannot provide enough silicon. "Seed", there will be low or even missing epitaxial SiGe growth at the edge of the STI structure. Therefore, there is a need to improve the performance of STI edge epitaxial layers.

Contents of the invention

The problem solved by the present invention provides a method for improving the performance of the STI edge epitaxial layer and a corresponding semiconductor structure, which improves the performance of the STI edge epitaxial layer.

In order to solve the above problems, the present invention provides a method for improving the performance of the STI edge epitaxial layer, including:

Provide semiconductor substrates;

sequentially forming a pad oxide layer and a pad nitride layer on the semiconductor substrate, the thickness of the pad oxide layer being greater than 100 angstroms;

Etching the pad oxide layer and the pad nitride layer to form an opening;

performing an etching process on the semiconductor substrate along the opening to form a trench, the trench has a side facing the gate structure;

Filling the trench with a dielectric material to form an STI structure, the upper surface of the STI structure is 100-200 Angstroms higher than the surface of the semiconductor substrate;

forming a gate structure on the semiconductor substrate between the STI structures;

Perform an etching process to remove the semiconductor substrate between the STI structure and the gate structure, form an epitaxial opening, and retain the semiconductor substrate on the sidewall of the trench;

Based on the semiconductor substrate at the sidewall of the trench and the semiconductor substrate at the bottom of the epitaxial opening, an epitaxial process is performed to form an epitaxial layer.

Optionally, the thickness of the pad oxide layer is less than 700 angstroms.

Optionally, the trench etching process is performed using a dry etching process.

Optionally, the trench etching process is a plasma etching process, the gas of the plasma etching process includes: HBr, O ₂ , He, Cl ₂ and NF ₃ , the etching process of the plasma etching Eclipse times range from 5-200 seconds.

Optionally, the material of the semiconductor substrate is silicon, and the material of the epitaxial layer is silicon germanium.

Optionally, the pad oxide layer is made of silicon oxide, the pad nitride layer is made of silicon nitride, and the dielectric material is silicon oxide.

Optionally, the pad oxide layer has a thickness of 100-150 angstroms, and the pad nitride layer has a thickness of 100-200 angstroms.

Correspondingly, the present invention also provides a semiconductor structure formed by the method, including:

a semiconductor substrate, on which a gate structure is formed;

trenches in the semiconductor substrate on both sides of the gate structure;

A dielectric material is filled in the trench, the dielectric material and the trench form an STI structure, and the upper surface of the STI structure is 100-200 Angstroms higher than the surface of the semiconductor substrate;

An epitaxial opening is located in the semiconductor substrate between the STI structure and the gate structure, and the semiconductor substrate is located between the epitaxial opening and the sidewall of the trench;

The epitaxial layer is arranged in the epitaxial opening.

Optionally, the upper surface of the STI structure is 100-200 angstroms higher than the surface of the semiconductor substrate.

Optionally, the material of the semiconductor substrate is silicon, and the material of the epitaxial layer is silicon germanium.

Compared with the prior art, the present invention has the following advantages:

The invention increases the thickness of the oxide layer formed on the semiconductor substrate, and the pad oxide layer can increase the height of the dielectric material in the groove when the dielectric material is subsequently deposited to form the STI structure, so that the surface of the finally formed STI structure is high. For the semiconductor substrate, the part higher than the STI structure can protect the semiconductor substrate on both sides of the trench, so that the semiconductor substrate on both sides of the trench is protected from the effect of the epitaxial layer opening etching process and remains, The semiconductor substrates on both sides of the trench can be used as the "seed" of the epitaxial process in the follow-up, which improves the growth ability of the epitaxial layer on both sides of the STI, and can form an epitaxial layer with good performance on both sides of the STI.

Description of drawings

FIG. 1 is a schematic structural view of a semiconductor device in the prior art SiGe epitaxy process.

2-3 are schematic cross-sectional structural diagrams of a manufacturing method of a semiconductor structure according to an embodiment of the present invention.

detailed description

The performance of the prior art epitaxial layer at the edge of the STI needs to be improved. Please refer to FIG. 1 , which is a schematic structural diagram of a semiconductor device in the prior art SiGe epitaxial process. STI structures 11 are formed in the semiconductor substrate 10, and a gate oxide layer 13, a polysilicon gate 14 located above the gate oxide layer 13, and a polysilicon gate 14 located on the surface of the semiconductor substrate 10 between adjacent STI structures 11 are formed. The sidewalls 15 on both sides, and the epitaxial layer 12 located between the gate structure and the STI structure, the epitaxial layer 12 is made by epitaxial process. The material of the semiconductor substrate 10 is silicon, and the material of the epitaxial layer 12 is silicon germanium. Based on the semiconductor substrate 10 , an epitaxial process is performed to form an epitaxial layer 12 .

Since the epitaxial layer 12 is realized by an epitaxial process, the epitaxial process needs to be based on silicon, so the STI structure 11 is filled with silicon dioxide, so the STI structure 11 cannot meet the requirements of the epitaxial process, and the area near the edge of the STI structure will cause The growth of the epitaxial layer at the edge of the STI structure 11 is low or even missing, so the performance of the existing epitaxial layer at the edge of the STI is also affected.

The upper surface of the STI structure in the prior art is usually substantially flush with the surface of the semiconductor substrate, but the inventors have found that increasing the height of the upper surface of the STI structure (that is, the surface of the dielectric material filled in the STI structure) makes the STI structure The upper surface exceeds the surface of the semiconductor substrate, which can protect the semiconductor substrate in the process of forming the epitaxial opening in the subsequent etching process, so that the semiconductor substrate on both sides of the groove of the SIT structure can be preserved after the etching process of the epitaxial opening. The remaining semiconductor substrate can be used as the "seed" of the epitaxial process to form epitaxial layers with good performance on both sides of the STI.

In order to solve the above problems, the present invention provides a method for improving the performance of the STI edge epitaxial layer, including:

Provide semiconductor substrates;

sequentially forming a pad oxide layer and a pad nitride layer on the semiconductor substrate, the thickness of the pad oxide layer being greater than 100 angstroms;

Etching the pad oxide layer and the pad nitride layer to form an opening;

performing an etching process on the semiconductor substrate along the opening to form a trench, the trench has a side facing the gate structure;

Filling the trench with a dielectric material to form an STI structure, the upper surface of the STI structure is 100-200 Angstroms higher than the surface of the semiconductor substrate;

forming a gate structure on the semiconductor substrate between the STI structures;

Perform an etching process to remove the semiconductor substrate between the STI structure and the gate structure, form an epitaxial opening, and retain the semiconductor substrate on the sidewall of the trench;

Based on the semiconductor substrate at the sidewall of the trench and the semiconductor substrate at the bottom of the epitaxial opening, an epitaxial process is performed to form an epitaxial layer.

The technical solution of the present invention will be described in detail below in conjunction with the accompanying drawings. Please refer to FIG. 2-FIG. 3 which are schematic cross-sectional structure diagrams of a method for fabricating a semiconductor structure according to an embodiment of the present invention.

First, referring to FIG. 2 , a semiconductor substrate 100 is provided. The material of the semiconductor substrate 100 is silicon.

Then, a pad oxide layer 101 and a pad nitride layer 102 are sequentially formed on the semiconductor substrate 100, and the thickness of the pad oxide layer 101 is greater than 100 angstroms. Usually the thickness of the liner oxide layer in the prior art is about 50 angstroms, and the present invention increases the thickness of the liner oxide layer, and the purpose is to increase the thickness of the dielectric material filled in the STI trench correspondingly, so that the STI The upper surface of the structure is higher than the surface of the semiconductor substrate.

However, the thickness of the pad oxide layer 101 should not be too thick, so as not to affect other process steps. The thickness of the pad oxide layer in the present invention is less than 700 angstroms. As a preferred embodiment, the pad oxide layer 101 has a thickness of 100-150 angstroms.

The material of the liner oxide layer 101 in the present invention is silicon oxide, which can be made by furnace tube oxidation process or RTO process. In this embodiment, the thickness of the liner oxide layer 101 is 200 angstroms, which is fabricated by furnace tube oxidation process.

The material of the pad nitride layer 102 is silicon nitride, and the thickness of the pad nitride layer is 100-200 angstroms. In this embodiment, the pad nitride layer has a thickness of 200 angstroms, which can be fabricated by chemical vapor deposition.

Next, still referring to FIG. 2 , the pad oxide layer 101 and the pad nitride layer 102 are etched to form an opening, and the opening is used to define the position and shape of the trench.

Then, continuing to refer to FIG. 2 , an etching process is performed on the semiconductor substrate 100 below the opening along the opening to form a trench 103 , and the trench 103 has a side facing the gate 140 (combined with FIG. 3 ).

The trench etching process may be performed using a dry etching process.

As an embodiment, the trench etching process is a plasma etching process, the gas of the plasma etching process includes: HBr, O ₂ , He, Cl ₂ and NF ₃ , the plasma etching process The etching time ranges from 5 to 200 seconds. The time of the etching process needs to be determined according to the depth of the trench. In this embodiment, the time of the etching process is 30 seconds.

Next, referring to FIG. 3 , a dielectric material is filled in the trench to form an STI structure 110 , the upper surface of the STI structure 110 is 100-200 angstroms higher than the surface of the semiconductor substrate 100 . The material of the dielectric layer is silicon oxide. Since the thickness of the pad oxide layer 101 is larger than that of the prior art, the pad oxide layer 101 can increase the height of the upper surface of the STI structure 110 (that is, the upper surface of the dielectric material filled in the trench), so that the STI The upper surface of the structure 110 is higher than the surface of the semiconductor substrate 100 . The portion of the STI structure 110 higher than the surface of the semiconductor substrate 100 can be used as a protective layer for the semiconductor substrate on both sides of the trench of the STI structure in subsequent process steps, so that the semiconductor substrate on both sides of the trench of the STI structure able to keep.

Then, the pad oxide layer 101 and the pad nitride layer 102 are removed, and a gate oxide layer 130 and a gate structure located above the gate oxide layer 130 are formed on the semiconductor substrate 100 between the STI structures 110, the gate The pole structure includes: a gate 140 made of polysilicon; sidewalls 150 located on both sides of the gate 140, and the sidewall 150 is made of silicon nitride. As an embodiment, a silicon oxide layer-silicon nitride layer may be formed on both sides of the silicon nitride layer of the sidewall 150 later to form a NON structure sidewall structure.

Next, an etching process is performed to remove the semiconductor substrate between the STI structure 110 and the gate structure to form an epitaxial opening. Due to the protection of the part of the STI structure 10 higher than the semiconductor substrate 100, it is located on the side wall of the trench of the STI structure. The semiconductor substrate is retained, and the retained semiconductor substrate can be used as the basis of the epitaxial process in the follow-up.

Finally, based on the semiconductor substrate 100 at the sidewall of the trench and the semiconductor substrate at the bottom of the epitaxial opening, an epitaxial process is performed to form an epitaxial layer 120 . As an embodiment, the material of the semiconductor substrate is silicon, and the material of the epitaxial layer is silicon germanium.

In the follow-up, it is necessary to form a silicon oxide layer-silicon nitride layer on both sides of the sidewall 150 according to the existing process flow, and then perform ion implantation to form a lightly doped source/drain in the epitaxial layer, and form a source/drain. drain.

Correspondingly, the present invention also provides a semiconductor structure formed by the method, including:

A semiconductor substrate 100, a gate structure is formed on the semiconductor substrate 100, the gate structure includes a gate 140 on the gate silicon oxide layer 130, and sidewalls 150 on both sides of the gate 140;

trenches located in the semiconductor substrate 100 on both sides of the gate structure;

A dielectric material is filled in the trench, the dielectric material and the trench form an STI structure 110, and the upper surface of the STI structure 110 is 100-200 angstroms higher than the surface of the semiconductor substrate;

an epitaxial opening located in the semiconductor substrate 100 between the STI structure and the gate structure, the epitaxial opening and the semiconductor substrate located between the trench sidewall;

The epitaxial layer 120 is disposed in the epitaxial opening.

As an example, the upper surface of the STI structure is 100-200 Angstroms higher than the surface of the semiconductor substrate, and the raised part can ensure that a certain amount of semiconductor substrate remains on both sides of the STI during the process of forming the epitaxial opening. , the remaining semiconductor substrate can be used as the "seed" of the subsequent epitaxial process to form epitaxial layers with good performance on both sides of the trench. The material of the semiconductor substrate is silicon, and the material of the epitaxial layer is silicon germanium.

In summary, the present invention increases the thickness of the oxide layer formed on the semiconductor substrate, and the pad oxide layer can increase the height of the dielectric material in the trench when the dielectric material is subsequently deposited to form the STI structure, so that the finally formed STI structure The surface is higher than the semiconductor substrate, and the part higher than the STI structure can protect the semiconductor substrates on both sides of the trench, so that the semiconductor substrates on both sides of the trench are not affected by the etching process of the epitaxial layer opening If retained, the semiconductor substrates on both sides of the trench can be used as the "seed" of the epitaxial process in the future, which improves the growth ability of the epitaxial layer on both sides of the STI, and can form an epitaxial layer with good performance on both sides of the STI.

Therefore, the above-mentioned preferred embodiments are only to illustrate the technical concept and features of the present invention, and the purpose is to enable those skilled in the art to understand the content of the present invention and implement it accordingly, and not to limit the scope of protection of the present invention. All equivalent changes or modifications made according to the spirit of the present invention shall fall within the protection scope of the present invention.

Claims (10)

1. A method for improving the performance of STI edge epitaxial layer, characterized in that, comprising: Provide semiconductor substrates; sequentially forming a pad oxide layer and a pad nitride layer on the semiconductor substrate, the thickness of the pad oxide layer being greater than 100 angstroms; Etching the pad oxide layer and the pad nitride layer to form an opening; performing an etching process on the semiconductor substrate along the opening to form a trench, the trench has a side facing the gate structure; Filling the trench with a dielectric material to form an STI structure, the upper surface of the STI structure is 100-200 Angstroms higher than the surface of the semiconductor substrate; forming a gate structure on the semiconductor substrate between the STI structures; Perform an etching process to remove the semiconductor substrate between the STI structure and the gate structure, form an epitaxial opening, and retain the semiconductor substrate on the sidewall of the trench; Based on the semiconductor substrate at the sidewall of the trench and the semiconductor substrate at the bottom of the epitaxial opening, an epitaxial process is performed to form an epitaxial layer. 2. The method for improving the performance of the STI edge epitaxial layer according to claim 1, wherein the thickness of the pad oxide layer is less than 700 angstroms. 3. The method for improving the performance of the STI edge epitaxial layer according to claim 1, wherein the trench etching process is performed by a dry etching process. 4. the method for improving the performance of STI edge epitaxial layer as claimed in claim 3, is characterized in that, described trench etching process is plasma etching process, and the gas of described plasma etching process comprises: HBr, O2, He, Cl ₂ and NF ₃ , the etching time range of the plasma etching is 5-200 seconds. 5 . The method for improving the performance of the STI edge epitaxial layer according to claim 1 , wherein the material of the semiconductor substrate is silicon, and the material of the epitaxial layer is silicon germanium. 6. The method for improving the performance of the STI edge epitaxial layer as claimed in claim 1, wherein the material of the pad oxide layer is silicon oxide, and the material of the pad nitride layer is silicon nitride, so The dielectric material is silicon oxide. 7. The method for improving the performance of the STI edge epitaxial layer according to claim 1, wherein the pad oxide layer has a thickness of 100-150 angstroms, and the pad nitride layer has a thickness of 100-200 angstroms. eh. 8. The semiconductor structure formed by the method of claim 1, comprising: a semiconductor substrate, on which a gate structure is formed; trenches in the semiconductor substrate on both sides of the gate structure; A dielectric material is filled in the trench, the dielectric material and the trench form an STI structure, and the upper surface of the STI structure is 100-200 Angstroms higher than the surface of the semiconductor substrate; An epitaxial opening is located in the semiconductor substrate between the STI structure and the gate structure, and the semiconductor substrate is located between the epitaxial opening and the sidewall of the trench; The epitaxial layer is arranged in the epitaxial opening. 9. The semiconductor structure according to claim 8, wherein the upper surface of the STI structure is 100-200 angstroms higher than the surface of the semiconductor substrate. 10. The semiconductor structure according to claim 8, wherein the semiconductor substrate is made of silicon, and the epitaxial layer is made of silicon germanium.