CN104362159B - A kind of storage capacitance in overall situation exposing pixels unit and forming method thereof - Google Patents
A kind of storage capacitance in overall situation exposing pixels unit and forming method thereof Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 20
- 229910052751 metal Inorganic materials 0.000 claims abstract description 59
- 239000002184 metal Substances 0.000 claims abstract description 59
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 56
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 55
- 238000005530 etching Methods 0.000 claims abstract description 19
- 239000007924 injection Substances 0.000 claims abstract description 10
- 238000002347 injection Methods 0.000 claims abstract description 10
- 230000004888 barrier function Effects 0.000 claims abstract description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 14
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 11
- 238000006243 chemical reaction Methods 0.000 claims description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 7
- 239000004411 aluminium Substances 0.000 claims description 7
- 229910052782 aluminium Inorganic materials 0.000 claims description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 7
- 229910052802 copper Inorganic materials 0.000 claims description 7
- 239000010949 copper Substances 0.000 claims description 7
- 239000000377 silicon dioxide Substances 0.000 claims description 7
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 7
- 239000010937 tungsten Substances 0.000 claims description 7
- 229910052721 tungsten Inorganic materials 0.000 claims description 7
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 6
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 6
- 239000010941 cobalt Substances 0.000 claims description 6
- 229910017052 cobalt Inorganic materials 0.000 claims description 6
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 6
- 230000005611 electricity Effects 0.000 claims description 6
- 229910052759 nickel Inorganic materials 0.000 claims description 6
- 239000010936 titanium Substances 0.000 claims description 6
- 229910052719 titanium Inorganic materials 0.000 claims description 6
- 101100373011 Drosophila melanogaster wapl gene Proteins 0.000 claims 2
- 210000004483 pasc Anatomy 0.000 claims 2
- 230000018199 S phase Effects 0.000 claims 1
- 239000000463 material Substances 0.000 claims 1
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- 230000000149 penetrating effect Effects 0.000 abstract description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- 238000003384 imaging method Methods 0.000 description 5
- 230000004044 response Effects 0.000 description 5
- 238000000151 deposition Methods 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 229910000765 intermetallic Inorganic materials 0.000 description 3
- ALKWEXBKAHPJAQ-NAKRPEOUSA-N Asn-Leu-Asp-Asp Chemical compound NC(=O)C[C@H](N)C(=O)N[C@@H](CC(C)C)C(=O)N[C@@H](CC(O)=O)C(=O)N[C@@H](CC(O)=O)C(O)=O ALKWEXBKAHPJAQ-NAKRPEOUSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000012544 monitoring process Methods 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000035515 penetration Effects 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 210000004027 cell Anatomy 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 239000003814 drug Substances 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002736 metal compounds Chemical class 0.000 description 1
- 238000001883 metal evaporation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 230000005622 photoelectricity Effects 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
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Abstract
The invention discloses the storage capacitance in a kind of global exposing pixels unit, including lighttight upper bottom crown and middle dielectric layer, mutually insulated between upper bottom crown, the sidewall slope of top crown.Invention additionally discloses the forming method of the storage capacitance in this global exposing pixels unit, step includes, and trap injection, conventional polycrystalline etches, mos capacitance polycrystal etching, abutment wall etching, source and drain injection, generation silicide barrier layer and formation metal silicide.The mos capacitance polycrystal etching of the present invention, mos capacitance polycrystalline Sidewall angles are changed by adjusting etching technics, prevent it from leaving abutment wall, realize mos capacitance and generate lighttight metal silicide in polycrystalline side wall, effectively stop penetrating for incident ray, the distortion of electric charge is stored in the storage capacitance for avoiding thereby resulting in, reduces noise, improves the accuracy of output image signal.The present invention is widely used suitable for the various global pixel structures for needing MOS storage capacitances such as 4T, 5T, 6T, 8T and 12T.
Description
Technical field
The present invention relates to field of image sensors, storage capacitance in more particularly to a kind of global exposing pixels unit and its
Forming method.
Background technology
Imaging sensor refers to the device for converting optical signals to electric signal, usually extensive commercial imaging sensor core
Piece includes two major class of charge coupled device ccd and complementary metal oxide semiconductor cmos image sensor chip.
Cmos image sensor compares the low-power consumption having with traditional ccd sensor, inexpensive and simultaneous with CMOS technology
The features such as appearance, therefore have been more and more widely used.Present cmos image sensor is applied not only to consumer electronics field, such as
In miniature digital camera DSC, mobile phone camera, video camera and digital single anti-DSLR, and in automotive electronics, monitoring, biological skill
The field such as art and medicine is also widely used.
The pixel unit of cmos image sensor is that imaging sensor realizes photosensitive core devices.The most frequently used pixel unit
For the active pixel structure comprising a photodiode and four transistors, photodiode is photosensitive list in these devices
Member, realizes the collection to light and opto-electronic conversion, and other MOS transistors are control units, mainly realizes to photodiode
Choose, reset, signal amplification and read control.The number of MOS transistor determines non-photo-sensing area in one pixel unit
The area that domain accounts for, therefore the dot structure comprising four transistors is commonly referred to as 4T pixel units.
Usually there are two kinds of shutter control modes in digital camera:Mechanical shutter and electronic shutter.Mechanical shutter passes through peace
The foldings of mechanical parts before cmos image sensor controls the time for exposure；The sequential that electronic shutter passes through pixel unit
Control to change the time of integration, so as to achieve the purpose that to control the time for exposure.Since mechanical shutter needs mechanical parts, number can be taken
The area of code camera, therefore it is not suitable for portable digital camera, and for video surveillance applications, due to being typically
Video acquisition is carried out, therefore generally using the electronic shutter control time for exposure.Electronic shutter is divided into two kinds again：Roller shutter type and the overall situation
Exposure type.Time for exposure between roller shutter type electronic shutter is often gone is inconsistent, is to be easy to cause to drag in shooting high-speed object
Shadow phenomenon；Then charge signal is stored in pixel in same Time Exposure by every a line of global exposure type electronic shutter at the same time
The memory node of unit, finally exports the signal of memory node line by line, since all rows were exposed in the same time, so
It will not cause motion blur phenomenon.
It is right as cmos image sensor is more and more widely used in industrial, vehicle-mounted, road monitoring and high speed camera
Further improved in the demand for the imaging sensor that can catch high-speed moving object image.In order to monitor high-speed object, CMOS
Imaging sensor needs the pixel unit using global exposure, and being used in global exposing pixels unit stores charge signal
Memory node is a very important index for the spurious response of light source.In practical applications, according to each pixel unit
Using the number of transistor, global exposing pixels unit has 4T, 5T, 6T, 8T and 12T etc..As shown in Figure 1 with the global exposure pictures of 8T
Exemplified by plain unit, C1 is memory node 1 and C2 is memory node 2.C1 and C2 is respectively the mos capacitance for storing electric charge.Storage section
The light source spurious response of point refers to spurious response of the memory node capacitance to incident light.For pixel unit, picture is incided
The light of plain cell surface cannot all focus on photodiode surface due to reflect and scattering, and have some light to enter
It is mapped on memory node C1 and C2.C1 can also produce photoelectricity sound with C2 under the irradiation of incident light as photodiode
Should.Due to incident light irradiates and the electric charge that is produced on C1 and C2 can influence to be stored in being produced by photodiode above originally
Voltage signal, cause the distortion of signal.In order to reduce the light source spurious response of memory node, C1 and C2 are needed using complete
Lighttight metal screen layer prevents the influence of incident ray.In the prior art, the metal usually used in CMOS technology
Including metal silicide, tungsten, aluminium and copper etc., reduce just needing using therein a kind of or several for memory node light source spurious response
Kind forms the metal shadowing layer of mos capacitance, avoids influence of the incident light to storage electric charge in mos capacitance.
The conventional mos capacitance of the prior art includes two kinds of structures of N-type and p-type, by taking N-type mos capacitance as an example.So-called MOS electricity
Appearance is a two terminal device formed in P type substrate, and top crown is made of N-type polycrystalline and metal silicide, and bottom crown is by N
Trap, N+ source-drain areas and metal silicide form, and the gate oxide in CMOS technology is as the dielectric layer between capacitance.Mos capacitance
Injection well region of the upper bottom crown due to including polycrystalline, metal silicide or substrate inherently high concentration, it is all real
It is existing light tight.Covered with abutment wall on the side wall of mos capacitance, its purpose is to reduce the transverse electric field of device, abutment wall draws
Enter source and drain N+ can be injected and be lightly doped source and drain NLDD injections to separate, source and drain is lightly doped so as to fulfill what CMOS technology needed
Area.Since abutment wall usually using insulating materials such as silica or silicon nitride can separate N at the same time as its dielectric layer, abutment wall
The metal silicide on the source-drain area surface of type polycrystalline and N+ injections, prevents the short circuit between metal silicide.But due to oxidation
Silicon and silicon nitride are fully transparent to incident ray, therefore incident ray can penetrate the polycrystalline that abutment wall enters mos capacitance
Top crown and N trap bottom crowns region, cause the charge signal distortion stored in mos capacitance, ultimately result in cmos image sensor
Export the distortion of signal.
The content of the invention
The technical problem to be solved in the present invention is prevent incident ray from penetrating the upper bottom crown area that abutment wall enters mos capacitance
Domain, the charge signal distortion stored in the mos capacitance for avoiding thereby resulting in, so as to avoid cmos image sensor output signal
Distortion, reduces noise, improves the accuracy of output image signal and improves image definition.
To solve the above problems, the present invention provides the storage capacitance in a kind of global exposing pixels unit：Including light tight
Upper bottom crown and middle dielectric layer, mutually insulated between upper bottom crown, it is characterised in that the storage capacitance top crown
Sidewall slope；
Optionally, the top crown side wall of the storage capacitance is more than 0 degree with bottom crown angle and is less than 60 degree；
Optionally, the storage capacitance top crown is made of polycrystalline, and bottom crown is made of trap and source-drain area, middle dielectric layer
It is silica；
Preferably, the storage capacitance top crown polycrystalline top surface and side are surrounded by lighttight obstacle；
Preferably, the lighttight obstacle is metal silicide；
Preferably, the lighttight obstacle of the storage capacitance top crown side surrounding is metal silicide；
Preferably, the metal silicide is the metal or metal of titanium, titanium nitride, tungsten, aluminium, copper, cobalt and nickel etc
Compound；
Optionally, lighttight metal silicide covers on the source-drain area as storage capacitance bottom crown；
Preferably, the metal silicide is the metal or metal compound of titanium, titanium nitride, tungsten, aluminium, copper, cobalt and nickel etc
Thing；
Optionally, place mutually exhausted between bottom crown in silicide barrier layer realization in the edge that bottom crown is adjacent on described
Edge.
To solve the above problems, the present invention provides a kind of forming method of storage capacitance in global exposing pixels unit, its
Step is：
1) trap injection is carried out on substrate；
2) conventional polycrystalline etches；
3) mos capacitance polycrystal etching；
4) abutment wall etches；
5) source and drain is injected；
6) silicide barrier layer；
7) metal silicide is formed.
By taking the N-type mos capacitance in mos capacitance conventional in the prior art as an example, its section is as shown in Figure 2.N-type MOS electricity
Appearance is a two terminal device formed in P type substrate 201, and top crown is made of N-type polycrystalline 202a and metal silicide 202b,
Bottom crown is made of N traps 203a, N+ source-drain area 203b and metal silicide 203d, and gate oxide 204 is as Jie between capacitance
Matter layer., will using abutment wall 205 in order to reduce the transverse electric field of device, it is necessary to introduce the source-drain area being lightly doped in CMOS technology
Highly doped N+ source and drain 203b injects and is lightly doped NLDD source and drain 203c injections and separates.It is more that the introducing of abutment wall is also prevented from N+ at the same time
The short circuit of metal silicide 203d above brilliant 202a and N+ source-drain areas, avoids the short circuit between grid and source and drain.Usual abutment wall makes
Dielectric layer is used as by the use of silica or silicon nitride.Silica and silicon nitride are all-transparent for incident ray, therefore incident light
Line can penetrate polycrystalline top crown and N trap bottom crown region of the abutment wall into capacitance, cause the charge signal stored in mos capacitance
Distortion, ultimately result in cmos image sensor output signal distortion.
It can be solved using the global exposing pixels unit storage capacitance provided by the present invention for cmos image sensor
The above problem of the prior art, stops that incident light penetrates and enters the upper and lower pole plate of storage capacitance, avoids incident light from depositing MOS
The influence of charge signal during storing up electricity is held.Fig. 3 show cutting for the MOS capacitance structure that the present invention is provided to solve the above-mentioned problems
Face figure, changes the angle of MOS storage capacitance top electrode polycrystalline side walls, tilts polycrystalline side wall 302, side wall is less than with substrate angle
60 degree, then generation metal silicide is reacted with side wall at the top of the method polycrystalline by depositing metal and silicification reaction
304, the metal deposited is the metal or metallic compound of titanium, titanium nitride, tungsten, aluminium, copper, cobalt and nickel etc.Due to metal layer
Impermeable light characteristic, the metal silicide formed stops and reflects incident ray, prevents light from entering by polycrystalline side wall
The N well region of mos capacitance, prevents light penetration polycrystalline from entering mos capacitance charge signal memory block, prevents to store signal mistake
Very.
Using the shape of the storage capacitance in the global exposing pixels unit provided by the present invention for cmos image sensor
Into method, polycide and the metal silicide short circuit in source and drain can be also prevented while light leakage is realized.Such as
Shown in Fig. 3, the graph position insertion insulation of the silicide barrier layer between mos capacitance polycrystalline top crown and N+ source-drain areas 301
Silicide obstacle 303, then deposit metal, form metal silicide 304.Due to the presence of silicide obstacle, polycrystalline
Disconnected with the metal silicide on source-drain area, it is therefore prevented that on the metal silicide and N+ source-drain areas of mos capacitance polycrystalline top crown
It is short-circuit between metal silicide.And mos capacitance polycrystalline, due to its sidewall slope, will not be left after conventional cmos abutment wall technique
Abutment wall, therefore polycrystalline surface will be covered by metal and form metal silicide completely.Side wall as shown in Figure 3 is formed to be again covered with
The MOS capacitance structure of metal silicide, so as to prevent incident ray from entering mos capacitance from abutment wall.
It can be seen from the above that compared with prior art, technical scheme has the following advantages：The present invention passes through addition
Mos capacitance polycrystal etching, changes the angle of polycrystalline side wall, and side wall from the prior art changes over side wall and lining perpendicular to substrate
The angle at bottom is 0~60 degree, and less than 60 degree.Then after the abutment wall etching of follow-up common process, script D of the prior art
Type abutment wall will be etched totally completely so that not have abutment wall presence on mos capacitance polycrystalline side wall.Whole polycrystalline surface can pass through
Lighttight metal silicide is formed with the silicification reaction of metal, so as to stop penetrating for incident ray, is avoided since light is penetrated
Enter mos capacitance, the charge signal for causing to store in capacitance changes and causes the distortion of cmos image sensor output signal.Lead to again
Cross introducing silicide barrier layer, it is ensured that with the metal silicide of source-drain area short circuit will not occur for polycide.The present invention
Middle mos capacitance polycrystal etching is to be realized on conventional polycrystalline etching technics by the flow and proportioning that change etching gas.This
The storage capacitance that invention provides is fewer than the product noise of the prior art, and the accuracy and image definition of output image signal have
Significantly improve and improve, while ensure that polycide will not be sent out with the metal silicide of source and drain by silicide barrier layer
Raw short circuit, improves the qualification rate of product.The present invention can be used for 4T, 5T, 6T, 8T and 12T etc. are various to need MOS to deposit
In the global pixel structure that storing up electricity is held, it is widely used.
Brief description of the drawings
Fig. 1 is the circuit structure of 8T overall situation exposing pixels units
Fig. 2 is conventional MOS capacitance structure
Fig. 3 is the MOS storage capacitor constructions provided by the present invention for global exposing pixels unit
Fig. 4 is the forming method of conventional mos capacitance
Fig. 5 is the forming method of the MOS storage capacitor constructions of global exposing pixels unit provided by the invention
Embodiment
To make present disclosure more clear understandable, below in conjunction with Figure of description, present disclosure is made into one
Walk explanation.Secondly, the present invention has carried out detailed statement using schematic diagram, when present example is described in detail, for convenience of description,
Schematic diagram is not partially enlarged in proportion to the general scale, should not be in this, as limitation of the invention.
The present invention provides storage capacitance and its formation side in a kind of global exposing pixels unit of cmos image sensor
Method, can avoid influence of the incident light to the charge signal stored in mos capacitance, avoid the distortion of output signal, pass image
Sensor can finally obtain the image of high quality.
Embodiment
By taking the forming process of N-type mos capacitance as an example.
The forming method of conventional mos capacitance is as shown in Figure 4.It is specifically included in the progress trap injection in P-type silicon substrate；It is conventional
Polycrystal etching, abutment wall etching, source and drain injection and metal silicide are formed.Above-mentioned steps in order to protrude the technique theme of mos capacitance,
Standard technology necessary gate oxidation, polycrystalline deposition, abutment wall deposit and Metal deposition are eliminated, it is simple to show.Formation side
The metal silicide for being surrounded source-drain area by well region and its being covered above in method forms the bottom crown of conventional mos capacitance, and carves
The metal silicide covered on polycrystalline and polycrystalline after erosion is the top crown of conventional mos capacitance.Conventional polycrystalline etch to be formed it is more
Brilliant figure is the grid of MOS transistor in circuit, while is also the top crown of mos capacitance, therefore the polycrystalline side wall of mos capacitance
For angle as shown in Fig. 2, perpendicular to P type substrate, abutment wall is to be attached to the D type insulating medium layers formed on polycrystalline side wall.Due to side
Wall be by silica or silicon nitride, what silica and silicon nitride were formed, it is fully transparent for incident ray so that incident optical energy
Enough penetrate abutment wall and enter mos capacitance pole plate, influence the charge signal stored in mos capacitance.
It is illustrated in figure 5 the forming method of the mos capacitance provided by the present invention for global exposing pixels unit.With conventional
Mos capacitance forming method compare, forming method provided by the invention adds one of MOS electricity after conventional polycrystal etching
Hold polycrystal etching.In practical operation, after conventional polycrystalline etching, polycrystalline of the side wall perpendicular to substrate is formd；Pass through mos capacitance again
Mask plate, is protected with photoresist using as the polycrystalline of MOS transistor grid in circuit, leaves mos capacitance polycrystalline figure, Ran Houjin
Row mos capacitance polycrystal etching：By etching gas flow and proportioning adjustment, increase reaction process in reaction polymer in MOS
Capacitance polycrystalline disposed on sidewalls, forms as shown in Figure 3 inclined more than 0 degree but less than 60 degree with the angle of P type substrate
Polycrystalline side wall；Then remove photoresist and continue abutment wall and etch.Since mos capacitance polycrystalline side wall is inclined, abutment wall can not be
Formed above, therefore the side wall of MOS transistor gate polycrystalline still leaves abutment wall after abutment wall etching, and on mos capacitance polycrystalline side wall
But there is no abutment wall completely.Silicide obstacle is formed in next step, in the graph position of previous layout design, as shown in Figure 3 in MOS
The silicide barrier layer of insulation is inserted between metal silicide on capacitance polycrystalline top crown and N+ source-drain areas, prevents follow-up life
Into the short circuit of metal silicide.Eventually form metal silicide：With side wall since no abutment wall covers at the top of mos capacitance polycrystalline,
After depositing metal or metallic compound, polycrystalline and metal directly react generation metal silicide, form polycrystalline top as shown in Figure 3
The MOS capacitance structure of metal silicide is all covered in portion and side wall.Metal silicide be by titanium, titanium nitride, tungsten, aluminium, copper, cobalt and
The metal or metallic compound of nickel etc and polycrystalline reaction generation.Using the opaqueness of metal silicide, realization prevent into
Penetrate the purpose that light penetration enters mos capacitance.
It is described above to be only based on presently preferred embodiments of the present invention, the scope of the present invention can not be limited with this.
It is any replacement for making component well know in the art to the device of the invention, combination, discrete, and step is implemented to the present invention
Suddenly make equivalent change well know in the art or replace the exposure without departing from the present invention and protection domain.
Claims (8)
1. the storage capacitance in a kind of overall situation exposing pixels unit, including lighttight upper bottom crown and middle dielectric layer, on
Mutually insulated between bottom crown, it is characterised in that the sidewall slope of the storage capacitance top crown, and the storage capacitance is upper
Pole plate side wall and bottom crown angle are more than 0 degree less than 60 degree, the storage capacitance top crown polycrystalline top surface and side and under
Step is covered by lighttight obstacle.
2. the storage capacitance in overall situation exposing pixels unit as claimed in claim 1, it is characterised in that in the storage capacitance
Pole plate is made of polycrystalline, and bottom crown is made of trap and source-drain area, and middle dielectric layer is silica.
3. the storage capacitance in overall situation exposing pixels unit as claimed in claim 1, it is characterised in that the lighttight resistance
Block material is metal silicide.
4. the storage capacitance in overall situation exposing pixels unit as claimed in claim 3, it is characterised in that the metal silicide
It is to be generated by the one or more in titanium, titanium nitride, tungsten, aluminium, copper, cobalt and nickel with pasc reaction.
5. the storage capacitance in overall situation exposing pixels unit as claimed in claim 2, it is characterised in that described as storage electricity
Holding on the source-drain area of pole plate has lighttight metal silicide to cover.
6. the storage capacitance in overall situation exposing pixels unit as claimed in claim 5, it is characterised in that the metal silicide
It is to be generated by the one or more in titanium, titanium nitride, tungsten, aluminium, copper, cobalt and nickel with pasc reaction.
7. the storage capacitance in overall situation exposing pixels unit as claimed in claim 1, it is characterised in that in the superior and the subordinate's phase
Place silicide barrier layer and realize mutually insulated between upper bottom crown in adjacent edge.
8. the forming method of storage capacitance, its step are in overall situation exposing pixels unit as claimed in claim 1：
1) trap injection is carried out on substrate；
2) conventional polycrystalline etches；
3) mos capacitance polycrystal etching, the sidewall slope of the storage capacitance top crown, and the top crown side wall of the storage capacitance
It is more than 0 degree with bottom crown angle and is less than 60 degree；
4) abutment wall etches；
5) source and drain is injected；
6) silicide barrier layer is formed；
7) metal silicide is formed.
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| CN1311529A (en) * | 2000-03-01 | 2001-09-05 | 国际商业机器公司 | Method for mfg. polycrystal silicon capacitor using FET tube and bipolar base pole polycrystal silicon layer |
| CN1322014A (en) * | 2000-04-29 | 2001-11-14 | 双汉科技股份有限公司 | Manufacturing method of photodiode complementary metal oxide semiconductor image sensor |
| CN1812111A (en) * | 2005-01-27 | 2006-08-02 | 台湾积体电路制造股份有限公司 | Image sensing pixel unit, image sensing device and manufacturing method thereof |
| CN103378163A (en) * | 2012-04-12 | 2013-10-30 | 元太科技工业股份有限公司 | Thin film transistor, array substrate and display device |
| CN104362159A (en) * | 2014-09-19 | 2015-02-18 | 上海集成电路研发中心有限公司 | Storage capacitor of global exposure pixel unit and production method of storage capacitor |
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