CN114268753B - High conversion gain image sensor pixel structure - Google Patents

Abstract

The invention discloses a high conversion gain image sensor pixel structure, which comprises a photodiode 101, a transmission transistor 103, a floating diffusion node 104, a reset transistor 105, a source follower transistor 107, a row strobe transistor 108, a power supply 106 and a pixel output 109 which are arranged in a semiconductor matrix; by changing the overlap capacitance between the floating diffusion node 104 and the transfer transistor 103 and reset transistor 105, the charge-voltage conversion factor is improved, thereby improving the sensitivity of the image sensor: a reset transistor shallow trench oxide layer 115 and a transfer transistor shallow trench oxide layer 116 are respectively provided at the overlapping portions of the floating diffusion node 104 and the transfer transistor 103 and the reset transistor 105, and a shallow trench isolation 117 is provided around. The invention improves the charge-voltage conversion factor, reduces input reference noise and improves the signal-to-noise ratio by reducing the overlap capacitance between the floating diffusion node and the transmission transistor and the reset transistor, thereby realizing the high-sensitivity image sensor.

Description

High conversion gain image sensor pixel structure

Technical Field

The present invention relates to a CMOS image sensor, and more particularly, to a high conversion gain pixel structure of an image sensor.

Background

CMOS image sensors are used in a large number of portable digital cameras, cell phones, smart cars, security and medical fields. Many of these applications require advanced performance such as wide dynamic range, high speed and high sensitivity.

Sensitivity, which is the most important performance index in image sensors, is defined as the ratio of the change in the output signal to the change in the input light. And in the case of very low light levels, the noise level of the image sensor determines the image quality. When the entire illumination range is considered from dark to light, the sensitivity of the image sensor is measured using the signal-to-noise ratio (SNR).

The signal-to-noise ratio (SNR) can be improved by boosting the signal and reducing the noise.

The prior art is shown in fig. 1, which is a circuit diagram of a 4-tube active pixel (4T-APS) of a conventional CMOS image sensor;

Fig. 2 and 4 are schematic cross-sectional and top-view configurations of a conventional source follower, respectively.

The disadvantages of the above prior art are:

The pixel structure is limited by the current process limitation, the conversion gain is lower than 250uV/e-, so that the signal-to-noise ratio (SNR) cannot reach the standard, and the requirements of the current market on high-sensitivity performance cannot be met.

In view of this, the present invention has been made.

Disclosure of Invention

The present invention is directed to an image sensor pixel structure with high conversion gain, so as to solve the above technical problems in the prior art.

The invention aims at realizing the following technical scheme:

The high conversion gain image sensor pixel structure of the present invention comprises a photodiode 101, a transfer transistor 103, a floating diffusion node 104, a reset transistor 105, a source follower transistor 107, a row strobe transistor 108, a power supply 106, and a pixel output 109 disposed in a semiconductor body;

By changing the overlap capacitance between the floating diffusion node 104 and the transfer transistor 103 and the reset transistor 105, the charge-voltage conversion factor is improved, thereby improving the sensitivity of the image sensor.

Compared with the prior art, the pixel structure of the image sensor with high conversion gain provided by the invention reduces input reference noise, improves signal-to-noise ratio (SNR) by reducing overlap capacitance (overlap capacitance) between a floating diffusion node (FD) and a transmission Transistor (TX) and a RESET transistor (RESET) and improving charge-voltage conversion factor (C.G.), and realizes the image sensor with high sensitivity.

Drawings

FIG. 1 is a circuit diagram of a 4-pipe active pixel (4T-APS) of a conventional CMOS image sensor

FIG. 2 is a cross-sectional view of a conventional CMOS image sensor 4-pipe active pixel (4T-APS)

FIG. 3 is a schematic diagram showing a cross-sectional view of a 4-pipe active pixel (4T-APS) of a CMOS image sensor according to the present invention

FIG. 4 is a top view block diagram of a conventional CMOS image sensor 4-pipe active pixel (4T-APS)

FIG. 5 is a top view of a pixel unit of an image sensor according to an embodiment of the invention

In the figure:

101 Photodiode (PD)

102 Floating diffusion node capacitance (Cfd)

103 Transfer Transistor (TX)

104 Floating diffusion node (FD)

105 RESET transistor (RESET)

106 Power supply (VDD)

107 Source follower transistor (SF)

108 Row strobe transistor (SEL)

109Pixel output (Vout)

110 Substrate (Substrate)

111 Gate Oxide (Gate Oxide)

112 Pass transistor Gate polysilicon (TX Gate Poly)

113 Reset transistor grid polysilicon (RESET GATE Poly)

114 Power/reset transistor drain (VDD/RESET DRAIN)

115 Reset transistor shallow channel oxide layer (RESET Shallow Channel Oxide)

116 Transfer transistor shallow channel oxide layer (TX Shallow Channel Oxide)

117 Shallow Trench Isolation (STI)

Detailed Description

The technical solutions in the embodiments of the present invention are clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention; it will be apparent that the described embodiments are only some embodiments of the invention, but not all embodiments, which do not constitute limitations of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention.

The terms that may be used herein will first be described as follows:

The term "and/or" is intended to mean that either or both may be implemented, e.g., X and/or Y are intended to include both the cases of "X" or "Y" and the cases of "X and Y".

The terms "comprises," "comprising," "includes," "including," "has," "having" or other similar referents are to be construed to cover a non-exclusive inclusion. For example: including a particular feature (e.g., a starting material, component, ingredient, carrier, formulation, material, dimension, part, means, mechanism, apparatus, step, procedure, method, reaction condition, processing condition, parameter, algorithm, signal, data, product or article of manufacture, etc.), should be construed as including not only a particular feature but also other features known in the art that are not explicitly recited.

The term "consisting of … …" is meant to exclude any technical feature element not explicitly listed. If such term is used in a claim, the term will cause the claim to be closed, such that it does not include technical features other than those specifically listed, except for conventional impurities associated therewith. If the term is intended to appear in only a clause of a claim, it is intended to limit only the elements explicitly recited in that clause, and the elements recited in other clauses are not excluded from the overall claim.

Unless specifically stated or limited otherwise, the terms "mounted," "connected," "secured," and the like should be construed broadly to include, for example: the connecting device can be fixedly connected, detachably connected or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the terms herein above will be understood by those of ordinary skill in the art as the case may be.

The terms "center," "longitudinal," "transverse," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," etc. refer to an orientation or positional relationship based on that shown in the drawings, merely for ease of description and to simplify the description, and do not explicitly or implicitly indicate that the apparatus or element in question must have a particular orientation, be constructed and operated in a particular orientation, and therefore should not be construed as limiting the present disclosure.

What is not described in detail in the embodiments of the present invention belongs to the prior art known to those skilled in the art. The specific conditions are not noted in the examples of the present invention and are carried out according to the conditions conventional in the art or suggested by the manufacturer. The reagents or apparatus used in the examples of the present invention were conventional products commercially available without the manufacturer's knowledge.

The high conversion gain image sensor pixel structure of the present invention comprises a photodiode 101, a transfer transistor 103, a floating diffusion node 104, a reset transistor 105, a source follower transistor 107, a row strobe transistor 108, a power supply 106, and a pixel output 109 disposed in a semiconductor body;

By changing the overlap capacitance between the floating diffusion node 104 and the transfer transistor 103 and the reset transistor 105, the charge-voltage conversion factor is improved, thereby improving the sensitivity of the image sensor.

The overlap capacitance is changed by:

A reset transistor shallow trench oxide 115 and a transfer transistor shallow trench oxide 116 are provided at the overlapping portions of the floating diffusion node 104 and the transfer transistor 103 and the reset transistor 105, respectively, and a shallow trench isolation 117 is provided around.

The thickness of the reset transistor shallow trench oxide layer 115 and the transmission transistor shallow trench oxide layer 116 is 30 nm-80 nm, and the thickness of the shallow trench isolation 117 is 350 nm-400 nm.

The reset transistor shallow trench oxide layer 115, the transfer transistor shallow trench oxide layer 116 and the shallow trench isolation 117 are realized using a two-step photolithography method:

Firstly, exposing the shallow trench isolation 117, the reset transistor shallow trench oxide layer 115 and the transmission transistor shallow trench oxide layer 116 simultaneously, and etching into a trench with the depth of 30-80 nm;

step two, fully covering the photoresist again, and independently photoetching the shallow trench isolation 117 area, and continuing etching 320nm;

And finally, filling the trench with oxide, and forming a shallow trench oxide layer and shallow trench isolation.

In summary, embodiments of the present invention reduce input reference noise, improve signal-to-noise ratio (SNR), and implement high sensitivity image sensors by reducing overlap capacitance (overlap capacitance) between floating diffusion node (FD) and transfer Transistor (TX) and RESET transistor (RESET) to improve charge-to-voltage conversion factor (c.g.).

In order to more clearly demonstrate the technical scheme and the technical effects provided by the invention, the following detailed description of the embodiments of the invention is given by way of specific examples.

Example 1

As shown in fig. 1, the high conversion gain image sensor pixel structure at least includes a Photodiode (PD), a transfer Transistor (TX), a floating diffusion node (FD), a RESET transistor (RESET), a source follower transistor (SF), a row strobe transistor (SEL), a power supply (VDD), and a pixel output (VOUT) disposed in a semiconductor substrate.

The present embodiment improves the sensitivity (sensitivity) of the image sensor by increasing a charge-to-voltage Conversion factor (c.g.) by changing an overlap capacitance (overlap capacitance) between a floating diffusion node (FD) and a transfer Transistor (TX) and a RESET transistor (RESET).

The floating diffusion node capacitor is composed of a junction capacitor between the active region and the substrate at the floating diffusion node, an overlap capacitor between the active region and the grid at the floating diffusion node and an intermetallic capacitor connected with the floating diffusion node.

The present embodiment achieves a high-sensitivity image sensor by reducing the input reference noise by reducing the overlap capacitance (overlap capacitance) between the floating diffusion node (FD) and the transfer Transistor (TX) and RESET transistors (RESET) to increase the charge-to-voltage conversion factor (c.g.), improving the signal-to-noise ratio (SNR).

As shown in fig. 3 and 5, the thickness of the shallow trench oxide layer 115/116 is about 30nm to 80nm; shallow Trench Isolation (STI) 117 regions having a thickness of about 350nm to 400nm. In the process, the embodiment is implemented by using a two-step photolithography method, and in the first step, the shallow trench isolation 117 and the two areas of the shallow trench oxide layer 115/116 are exposed simultaneously, and etched into trenches with a depth of 30nm to 80 nm. And secondly, fully covering the photoresist again, and independently photoetching the shallow trench isolation 117 area to continue etching 320nm. And finally filling the groove with oxide, and forming a shallow groove oxide layer and shallow groove isolation.

The charge-to-voltage conversion factor (c.g.) indicates the magnitude of a voltage change caused by one electron of a pixel during operation, as follows

C.G.＝q/Cfd

From this, it is known that the smaller the capacitance of the FD point is, the higher the charge-voltage conversion factor (c.g.) is

As shown in fig. 5, the shallow trench oxide layer used in the present embodiment is located where the floating diffusion node FD overlaps with the transfer Transistor (TX) and the RESET transistor (RESET). The shallow trench oxide layer reduces the overlap capacitance of the transistor and the source/drain. In this embodiment, the shallow trench oxide layer can reduce the overlap capacitance between the floating diffusion node FD and the transfer Transistor (TX) and RESET transistor (RESET), and reduce Cfd, thereby improving conversion gain and obtaining a high-sensitivity image sensor.

The foregoing is only a preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present invention should be included in the scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims. The information disclosed in the background section herein is only for enhancement of understanding of the general background of the invention and is not to be taken as an admission or any form of suggestion that this information forms the prior art already known to those of ordinary skill in the art.

Claims (1)

1. A high conversion gain image sensor pixel structure comprising a photodiode (101), a transfer transistor (103), a floating diffusion node (104), a reset transistor (105), a source follower transistor (107), a row strobe transistor (108), a power supply (106), and a pixel output (109) disposed in a semiconductor body;

by changing the overlap capacitance between the floating diffusion node (104) and the transfer transistor (103) and reset transistor (105), the charge-to-voltage conversion factor is improved, thereby improving the sensitivity of the image sensor;

the overlap capacitance is changed by:

A reset transistor shallow trench oxide layer (115) and a transfer transistor shallow trench oxide layer (116) are respectively arranged at the overlapping part of the floating diffusion node (104) and the transfer transistor (103) and the reset transistor (105), and shallow trench isolation (117) is arranged around the floating diffusion node;

The thickness of the reset transistor shallow trench oxide layer (115) and the thickness of the transmission transistor shallow trench oxide layer (116) are 30-80 nm, and the thickness of the shallow trench isolation (117) is 350-400 nm;

-implementing the reset transistor shallow trench oxide layer (115), the transfer transistor shallow trench oxide layer (116) and the shallow trench isolation (117) using a two-step lithographic method:

Firstly, exposing a shallow trench isolation (117), a reset transistor shallow trench oxide layer (115) and a transmission transistor shallow trench oxide layer (116) at the same time, and etching into a trench with the depth of 30-80 nm;

Step two, fully covering the photoresist again, and independently photoetching the shallow trench isolation (117) area, and continuing etching for 320nm;

And finally, filling the trench with oxide, and forming a shallow trench oxide layer and shallow trench isolation.