CN104347419B - A kind of ESD protective device and preparation method thereof - Google Patents

Abstract

The invention provides an ESD protection device and a manufacturing method thereof. The manufacturing method comprises the steps of: 1) forming a Si _1-x Ge _x layer on the surface of a silicon substrate, and fabricating a gate on the surface of the Si _1-x Ge _x layer structure, wherein, 0<x<1; 2) forming a lightly doped drain in the Si _1‑x Ge _x layer through an ion implantation process and an annealing process; 3) removing the Si ₁ on both sides of the gate structure _‑x Ge _x layer, exposing the silicon substrate below both sides of the gate structure; 4) using wet etching to form grooves in the silicon substrate below both sides of the gate structure; forming a lightly doped semiconductor layer in the groove; 6) forming a heavily doped semiconductor layer on the surface of the lightly doped semiconductor layer, and performing annealing so that the dopant ions in the heavily doped semiconductor layer The semiconductor layer and the Si _1‑x Ge _x layer are advanced to form source and drain regions. The invention can effectively reduce the trigger voltage of the ESD protection device while ensuring the stable performance of the device. The invention is compatible with the CMOS process and is easy to realize industrialization.

Description

A kind of ESD protection device and manufacturing method thereof

technical field

The invention relates to a semiconductor device and a manufacturing method thereof, in particular to an ESD protection device and a manufacturing method thereof.

Background technique

Static electricity is an objective natural phenomenon, which can be produced in many ways, such as contact, friction, induction between electrical appliances, etc. Static electricity is characterized by long-term accumulation, high voltage, low power, small current and short action time. Static electricity causes serious harm in many fields. Friction electrification and human body static electricity are two major hazards in the electronics industry, which often cause unstable operation or even damage of electronic and electrical products. ESD is a subject formed since the middle of the 20th century to study the generation, harm and protection of static electricity. It is customary in the world to refer to the equipment used for electrostatic protection as ESD.

With the continuous development of integrated circuit technology, the size of transistors has been reduced to submicron or even deep submicron stage. The reduction of the physical size of the device has greatly improved the integration of the circuit, but the reliability of the highly integrated device has also followed. ESD (electro-static discharge, electrostatic discharge) is one of the most important causes of failure of electronic equipment and components. This is mainly because, as the size of components shrinks, for example, the thickness of the gate oxide layer of field effect elements gradually becomes thinner. Although this change can greatly improve the working efficiency of the circuit, it may make the circuit more fragile. , so that the circuit is prone to failure when subjected to electrostatic shock.

In order to solve the reliability problems of electronic equipment and components caused by ESD, the industry considers the introduction of ESD protection devices (also known as electrostatic resistors) with higher performance and higher tolerance into integrated circuits. The ESD protection device is generally arranged between the signal line of the circuit and the ground terminal. Under the normal working state of the circuit, the two ends of the ESD protection device are separated by the middle dielectric layer, showing a high-impedance state, and the signal will not flow through the ESD protection device. ground terminal. When the circuit is affected by ESD, for example, when the static electricity on the human skin is applied to the circuit, a large voltage value may appear in the circuit, and the generation of large voltage causes a large potential difference at both ends of the ESD protection device. At this time, the ESD protection device When it is broken down, it changes from a high-resistance state to a conduction state, so that static electricity is introduced to the ground terminal, thereby avoiding damage to the working circuit due to excessive voltage. After the static electricity is exported, the potential difference between the two ends of the ESD protection device disappears, and the ESD protection device returns to a high resistance state.

At present, there are more and more applications of high-speed signal transmission, and the demand for the performance of ESD protection devices is gradually increasing. People have higher requirements for the stability and trigger voltage of ESD protection devices. However, due to the limitations of materials and processes, it is difficult to further reduce the protection trigger voltage of the existing ESD protection device structure on the basis of ensuring device stability, which is extremely unfavorable to the development of electronic equipment and IC circuits.

Therefore, it is necessary to provide a stable ESD protection device with a lower protection trigger voltage.

Contents of the invention

In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide an ESD protection device and a manufacturing method thereof, which are used to solve the problem that the protection trigger voltage of the ESD protection device is difficult to further reduce in the prior art.

In order to achieve the above object and other related objects, the present invention provides a method for manufacturing an ESD protection device, which at least includes the following steps:

1) Provide a silicon substrate, form a Si _1-x Ge _x layer on the surface of the silicon substrate, and fabricate a gate structure on the surface of the Si _1-x Ge _x layer, where 0<x<1;

2) forming a lightly doped drain in the Si _1-x Ge _x layer by ion implantation process and annealing process;

3) removing the Si _1-x Ge _x layer below both sides of the gate structure to expose the silicon substrate below both sides of the gate structure;

4) Forming grooves in the silicon substrate under both sides of the gate structure respectively;

5) forming a lightly doped semiconductor layer in the groove;

6) Forming a heavily doped semiconductor layer on the surface of the lightly doped semiconductor layer, and performing annealing so that the doping ions in the heavily doped semiconductor layer flow toward the lightly doped semiconductor layer and the Si _1-x Ge _x layer Advance to form source and drain regions.

As a preferred solution of the manufacturing method of the ESD protection device of the present invention, in the Si _1-x Ge _x layer, x ranges from 0.3 to 0.6.

As a preferred solution of the manufacturing method of the ESD protection device of the present invention, the Si _1-x Ge _x layer is doped with B or BF ₂ at a concentration of 5e17/cm ³ -1e19/cm ³ .

As a preferred solution of the manufacturing method of the ESD protection device of the present invention, a wet etching process is used to form grooves in the silicon substrate under both sides of the gate structure.

As a preferred solution of the manufacturing method of the ESD protection device of the present invention, step 4) uses HF, HBr or CH ₃ COOH solution for wet etching.

As a preferred solution of the manufacturing method of the ESD protection device of the present invention, in step 4), the groove is an inverted triangle groove or a U-shaped groove, and the maximum depth of the groove is 30nm-100nm.

As a preferred solution of the manufacturing method of the ESD protection device of the present invention, the material of the lightly doped semiconductor layer and the heavily doped semiconductor layer is Si, SiC or SiGe.

The present invention also provides an ESD protection device, comprising at least:

a silicon substrate having two grooves spaced apart therein;

A Si _1-x Ge _x layer, bonded to the surface of the silicon substrate between the two grooves, and a lightly doped drain is formed in the Si _1-x Ge _x layer, where 0<x<1 ;

a gate structure, combined on the surface of the Si _1-x Ge _x layer;

The source region and the drain region are formed by a lightly doped semiconductor layer filling the bottom of the two grooves, and a heavily doped semiconductor region bonded to the surface of the lightly doped semiconductor layer and connected to the lightly doped drain.

As a preferred solution of the ESD protection device of the present invention, the heavily doped semiconductor region extends laterally to a preset depth in the Si _1-x Ge _x layer.

As a preferred solution of the ESD protection device of the present invention, the groove is an inverted triangle groove or a U-shaped groove, and the maximum depth of the groove is 30nm-100nm.

As a preferred solution of the ESD protection device of the present invention, the Si _1-x Ge _x layer is doped with B or BF ₂ at a concentration of 5e17/cm ³ -1e19/cm ³ .

As mentioned above, the present invention provides an ESD protection device and a manufacturing method thereof. The manufacturing method includes the steps of: 1) forming a Si 1-x Ge x layer on the surface of a silicon substrate, and forming a Si _1-x Ge _x layer on the Si _1-x Ge _x layer Fabricate a gate structure on the surface, where 0<x<1; 2) form a lightly doped drain in the Si _1-x Ge _x layer by ion implantation and annealing; 3) remove both sides of the gate structure The lower Si _1-x Ge _x layer exposes the silicon substrate below both sides of the gate structure; 4) wet etching is used to form grooves in the silicon substrate below both sides of the gate structure; 5 ) forming a lightly doped semiconductor layer in the groove; 6) forming a heavily doped semiconductor layer on the surface of the lightly doped semiconductor layer, and performing annealing so that the dopant ions in the heavily doped semiconductor layer The lightly doped semiconductor layer and the Si _1-x Ge _x layer are advanced to form a source region and a drain region. The invention can effectively reduce the trigger voltage of the ESD protection device while ensuring the stable performance of the device, and more effectively protect the circuit equipment. The invention is compatible with the existing CMOS technology, and is easy to realize industrialization.

Description of drawings

FIG. 1 is a schematic flow chart showing the steps of the manufacturing method of the ESD protection device of the present invention.

2 to 4 are schematic structural diagrams presented in step 1) of the manufacturing method of the ESD protection device of the present invention.

FIG. 5 shows a schematic structural diagram presented in step 2) of the manufacturing method of the ESD protection device of the present invention.

FIG. 6 shows a schematic structural diagram presented in step 3) of the manufacturing method of the ESD protection device of the present invention.

FIG. 7 shows a schematic structural diagram presented in step 4) of the manufacturing method of the ESD protection device of the present invention.

FIG. 8 shows a schematic structural diagram presented in step 5) of the manufacturing method of the ESD protection device of the present invention.

9 to 10 are schematic structural diagrams presented in step 6) of the manufacturing method of the ESD protection device of the present invention.

Component designation description

detailed description

Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.

Please refer to Figure 1 to Figure 10. It should be noted that the diagrams provided in this embodiment are only schematically illustrating the basic idea of the present invention, and only the components related to the present invention are shown in the diagrams rather than the number, shape and shape of the components in actual implementation. Dimensional drawing, the type, quantity and proportion of each component can be changed arbitrarily during actual implementation, and the component layout type may also be more complicated.

As shown in FIGS. 1 to 10 , this embodiment provides a method for manufacturing an ESD protection device, which at least includes the following steps:

As shown in Figures 1 to 4, step 1) S11 is firstly carried out, providing a silicon substrate 101, forming a Si 1-x Ge x layer 102 on the surface of the silicon substrate 101, and forming a Si _1-x Ge _x layer 102 on the Si _1-x Ge _x A gate structure 103 is formed on the surface of the layer 102, where 0<x<1.

As an example, in the Si _1-x Ge _x layer 102, x ranges from 0.3 to 0.6. Due to the difference in lattice size in the silicon substrate 101, the Si _1-x Ge _x layer 102 will introduce Stress, the stress can improve the performance of the Si _1-x Ge _x layer 102 as a channel.

As an example, the Si _1-x Ge _x layer 102 is a gradient Si _1-x Ge _x layer 102 with a gradually increasing Ge content, which can reduce the introduction of a large number of defects due to lattice mismatch and ensure that the Si _1-x Ge The mass of the _x -layer 102 .

As an example, the thickness of the Si _1-x Ge _x layer 102 is 20 nm˜50 nm.

As an example, the Si _1-x Ge _x layer 102 is doped with B or BF ₂ at a concentration of 5e17/cm ³ -1e19/cm ³ .

It should be noted that the substrate used in the present invention is a silicon substrate 101 , however, in other implementation processes, other expected semiconductor substrates, such as SiGe substrates, SiC substrates, etc., may also be used.

As an example, fabricating the gate structure 103 includes the following steps:

2-1) forming a gate oxide layer on the surface of the Si _1-x Ge _x layer 102;

2-2) forming a polysilicon layer on the surface of the gate oxide layer;

2-3) Etching and removing part of the polysilicon layer and the gate oxide layer according to the shape of the gate structure 103;

2-4) Forming sidewall structures on both sides of the gate oxide layer and the polysilicon layer.

As an example, other conductive materials may also be used to replace the polysilicon layer, and the sidewall structure may be silicon dioxide, silicon nitride, or a laminate composed of silicon dioxide and silicon nitride.

As shown in FIG. 1 and FIG. 5 , step 2) S12 is then performed to form a lightly doped drain 104 in the Si _{1- x} Ge _x layer 102 through an ion implantation process and an annealing process.

As an example, the lightly doped drain 104 is formed by implanting P or As into the Si _1-x Ge _x layer 102 and then performing an annealing process to diffuse the implanted ions.

As shown in FIG. 1 and FIG. 6, then proceed to step 3) S13, remove the Si _1-x Ge _x layer 102 below the two sides of the gate structure 103, and expose the silicon substrate below the two sides of the gate structure 103 101.

As an example, the Si _{1- x} Ge _x layer 102 under both sides of the gate structure 103 is removed by dry etching such as ICP etching, exposing the silicon substrate 101 under both sides of the gate structure 103 .

As shown in FIG. 1 and FIG. 7 , step 4) S14 is then performed to form grooves 105 in the silicon substrate 101 below both sides of the gate structure 103 .

As an example, a wet etching process is used to form grooves 105 in the silicon substrate 101 under both sides of the gate structure 103 respectively. Specifically, HF, HBr or CH ₃ COOH solution is used for wet etching, and in this embodiment, HF solution is used for wet etching.

As an example, the groove 105 is an inverted triangle groove 105 or a U-shaped groove 105, and the maximum depth of the groove 105 is 30 nm˜100 nm.

Of course, the shape of the groove 105 is generally limited by the crystal orientation of the silicon substrate 101 , therefore, the shape of the groove 105 can be changed by changing the crystal orientation of the silicon substrate 101 .

As shown in FIG. 1 and FIG. 8 , then step 5) S15 is performed to form a lightly doped semiconductor layer 106 in the groove 105 .

As an example, the material of the lightly doped semiconductor layer 106 is Si, SiC or SiGe.

As an example, the lightly doped semiconductor layer 106 can be formed by simultaneously injecting P or As plasma during vapor phase epitaxy, or the lightly doped semiconductor layer 106 can be formed by ion implantation and annealing after vapor phase epitaxy. semiconductor layer 106 . The lightly doped semiconductor layer 106 can effectively reduce the trigger voltage of the final ESD protection device.

In this embodiment, the lightly doped semiconductor layer 106 is formed by ion implantation process and annealing process after vapor phase epitaxy, the annealing temperature is 800-950° C., and the annealing time is 0.5 min-10 min. After the annealing is completed, the The ion doping concentration of the lightly doped semiconductor layer 106 is 5e17/cm ³ -5e18/cm ³ .

As shown in Figure 1 and Figures 9 to 10, step 6) S16 is finally performed to form a heavily doped semiconductor layer 107 on the surface of the lightly doped semiconductor layer 106, and annealing is performed to make the inside of the heavily doped semiconductor layer 107 The dopant ions in the lightly doped semiconductor layer 106 and the Si _1-x Ge _x layer 102 advance to form a heavily doped semiconductor region 108 to complete the fabrication of the source region and the drain region.

As an example, the material of the heavily doped semiconductor layer 107 is Si, SiC or SiGe.

As an example, a semiconductor layer is first formed on the surface of the lightly doped semiconductor layer 106 by vapor phase epitaxy, then a higher dose of P or As ions is implanted through an ion implantation process to form a heavily doped semiconductor layer 107, and finally the annealing process Propel P or As ions to the lightly doped semiconductor layer 106 and the Si _1-x Ge _x layer 102 to form a heavily doped semiconductor region 108 , and finally complete the fabrication of the source and drain regions of the ESD protection device.

In this embodiment, an epitaxial process is first used to form a semiconductor layer on the surface of the lightly doped semiconductor layer 106, then P ions are implanted by an ion implantation process to form a heavily doped semiconductor layer 107, and finally an annealing process is performed to make the P The ions advance to the lightly doped semiconductor layer 106 and the Si _{1-x Gex} layer 102 to form the heavily doped semiconductor region 108, the annealing temperature used here is 950°C-1100°C, the annealing time is 10s-30s, and the annealing is completed Afterwards, the ion doping concentration of the heavily doped semiconductor region 108 is 1e20/cm ³ -5e20/cm ³ .

As shown in Figure 10, this embodiment also provides an ESD protection device, including at least:

A silicon substrate 101 having two grooves 105 spaced apart in the silicon substrate 101;

The Si _1-x Ge _x layer 102 is bonded to the surface of the silicon substrate 101 between the two grooves 105, and a lightly doped drain 104 is formed in the Si _1-x Ge _x layer 102, wherein, 0<x<1;

a gate structure 103, bonded to the surface of the Si _1-x Ge _x layer 102;

The source region and the drain region are composed of a lightly doped semiconductor layer 106 filling the bottom of the two grooves 105, and a heavily doped semiconductor layer bonded to the surface of the lightly doped semiconductor layer 106 and connected to the lightly doped drain 104 Region 108 is formed.

As an example, the heavily doped semiconductor region extends laterally to a predetermined depth in the Si _1-x Ge _x layer. The preset depth can be controlled by controlling parameters such as ion doping concentration, annealing temperature and annealing time.

As an example, the Si _1-x Ge _x layer 102 is doped with B or BF ₂ at a concentration of 5e17/cm ³ -1e19/cm ³ .

As an example, in the Si _1-x Ge _x layer 102, x ranges from 0.3 to 0.6. Due to the difference in lattice size in the silicon substrate 101, the Si _1-x Ge _x layer 102 will introduce Stress, the stress can improve the performance of the Si _1-x Ge _x layer 102 as a channel.

As an example, the Si _1-x Ge _x layer 102 is a gradient Si _1-x Ge _x layer 102 with a gradually increasing Ge content, which can reduce the introduction of a large number of defects due to lattice mismatch and ensure that the Si _1-x Ge The mass of the _x -layer 102 .

As an example, the thickness of the Si _1-x Ge _x layer 102 is 20 nm˜50 nm.

As an example, the material of the lightly doped semiconductor layer 106 is Si, SiC or SiGe.

As an example, the groove 105 is an inverted triangle groove 105 or a U-shaped groove 105, and the maximum depth of the groove 105 is 30 nm˜100 nm.

As an example, the ion doping concentration of the lightly doped semiconductor layer 106 is 5e17˜5e18/cm ³ , and the ion doping concentration of the heavily doped semiconductor region 108 is 1e20/cm ³ ˜5e20/cm ³ .

In summary, the present invention provides an ESD protection device and a manufacturing method thereof. The manufacturing method includes the steps of: 1) forming a Si 1-x Ge x layer on the surface of a silicon substrate, and forming a Si _1-x Ge _x layer on the Si _1-x Ge _x Fabricate a gate structure on the surface of the Si 1-x Ge x layer, where 0<x<1; 2) Form a lightly doped drain in the Si _1-x Ge _x layer by ion implantation and annealing; 3) Remove both sides of the gate structure The Si _1-x Ge _x layer under the side, exposing the silicon substrate under the two sides of the gate structure; 4) using wet etching to form grooves in the silicon substrate under the two sides of the gate structure; 5) forming a lightly doped semiconductor layer in the groove; 6) forming a heavily doped semiconductor layer on the surface of the lightly doped semiconductor layer, and performing annealing so that the dopant ions in the heavily doped semiconductor layer The lightly doped semiconductor layer and the Si _1-x Ge _x layer are advanced to form a source region and a drain region. The invention can effectively reduce the trigger voltage of the ESD protection device while ensuring the stable performance of the device, and more effectively protect the circuit equipment. The invention is compatible with the existing CMOS technology, and is easy to realize industrialization. The invention can effectively reduce the trigger voltage of the ESD protection device while ensuring the stable performance of the device, and more effectively protect the circuit equipment. The invention is compatible with the existing CMOS technology, and is easy to realize industrialization. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial application value.

The above-mentioned embodiments only illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical ideas disclosed in the present invention should still be covered by the claims of the present invention.

Claims (11)

1. a preparation method of ESD protection device, is characterized in that, comprises the following steps at least: 1) A silicon substrate is provided, and a Si _1-x Ge _x layer is formed on the surface of the silicon substrate, wherein the Si _1-x Ge _x layer is a gradient Si _1-x Ge _x layer with gradually increasing Ge content , fabricating a gate structure on the surface of the Si _1-x Ge _x layer, wherein 0<x<1; 2) forming a lightly doped drain in the Si _1-x Ge _x layer by an ion implantation process and an annealing process, wherein the lightly doped drain extends below the gate structure; 3) removing the Si _1-x Ge _x layer under both sides of the gate structure, exposing the silicon substrate under both sides of the gate structure; 4) forming grooves in the silicon substrate under both sides of the gate structure respectively; 5) forming a lightly doped semiconductor layer in the groove; 6) forming a heavily doped semiconductor layer on the surface of the lightly doped semiconductor layer, and performing annealing so that the doping ions in the heavily doped semiconductor layer flow toward the lightly doped semiconductor layer and the Si _1-x Ge _x layer Advance to form a source region and a drain region, wherein the source region and the drain region are composed of a lightly doped semiconductor layer filled at the bottom of the two grooves, and are combined on the surface of the lightly doped semiconductor layer and combined with the lightly doped semiconductor layer A heavily doped semiconductor region connected to the drain is formed. 2 . The method for manufacturing an ESD protection device according to claim 1 , characterized in that: in the Si _1-x Ge _x layer, x ranges from 0.3 to 0.6. 3 . The method for manufacturing an ESD protection device according to claim 1 , wherein the Si _1-x Ge _x layer is doped with B or BF ₂ at a concentration of 5e17/cm ³ -1e19/cm ³ . 4. The manufacturing method of the ESD protection device according to claim 1, characterized in that: in step 4), grooves are respectively formed in the silicon substrate under both sides of the gate structure by using a wet etching process. 5 . The manufacturing method of the ESD protection device according to claim 4 , characterized in that: step 4) adopts HF, HBr or CH ₃ COOH solution for wet etching. 6 . 6 . The method for manufacturing an ESD protection device according to claim 1 , wherein in step 4), the groove is an inverted triangle groove or a U-shaped groove, and the depth of the groove is 30 nm˜100 nm. 7. The manufacturing method of the ESD protection device according to claim 1, characterized in that: the lightly doped semiconductor layer and the heavily doped semiconductor layer are made of Si, SiC or SiGe. 8. A kind of ESD protection device is characterized in that, at least comprises silicon substrate, Si _1-x Ge _x layer, gate structure, source region and drain region: There are two grooves spaced apart in the silicon substrate; The Si _1-x Ge _x layer is bonded to the surface of the silicon substrate between the two grooves, and a lightly doped drain is formed in the Si _1-x Ge _x layer, and the lightly doped drain extending below the gate structure, wherein the Si _1-x Ge _x layer is a gradient Si _1-x Ge _x layer with gradually increasing Ge content, 0<x<1, and the Si _1-x Gex layer is a stressed Si _1-x Ge _x layer; The gate structure is bonded to the surface of the Si _1-x Ge _x layer; The source region and the drain region are composed of a lightly doped semiconductor layer filled at the bottom of the two grooves, and a heavily doped semiconductor layer bonded to the surface of the lightly doped semiconductor layer and connected to the lightly doped drain area formation. 9. The ESD protection device according to claim 8, wherein the heavily doped semiconductor region extends laterally to a predetermined depth in the Si _1-x Ge _x layer. 10 . The ESD protection device according to claim 8 , wherein the groove is an inverted triangle groove or a U-shaped groove, and the depth of the groove is 30 nm˜100 nm. 11 . 11. The ESD protection device according to claim 8, characterized in that: the Si _1-x Ge _x layer is doped with B or BF ₂ at a concentration of 5e17/cm ³ -1e19/cm ³ .