CN104517883B - A kind of method that utilization ion implantation technique prepares semiconductor-on-insulator (ssoi) material - Google Patents

Abstract

The present invention provides a kind of method that utilization ion implantation technique prepares semiconductor-on-insulator (ssoi) material, including step：1）In the monocrystal thin films of the first substrate surface formation doping；2）Cushion and top layer semiconductors material are formed in monocrystal thin films surface；3）By foreign ion injection to monocrystal thin films；4）The position of predetermined depth of the ion implanting into the first substrate of monocrystal thin films lower section will be peeled off；5）It is bonded the top layer semiconductors material and the second substrate with insulating barrier；6）Made annealing treatment, first substrate is separated with the cushion at the monocrystal thin films, remove the cushion.Note the double action peeled off with doped single crystal film altogether present invention incorporates ion, effectively reduce stripping dosage.Implanting impurity ion, which makes monocrystal thin films produce stress, increases its adsorption capacity, realizes and peels off after the annealing of H ion implantings, peels off and occur at ultra-thin monocrystal thin films, crackle very little can obtain high-quality semiconductor-on-insulator (ssoi) material.

Description

A method of preparing semiconductor-on-insulator material by ion implantation technology

technical field

The invention relates to a method for preparing a semiconductor material, in particular to a method for preparing a semiconductor material on an insulator by ion implantation technology.

Background technique

In recent years, silicon-on-insulator (SOI) materials have been widely used in many fields such as low-voltage, low-power consumption, high-temperature, and radiation-resistant devices because of their unique insulating buried layer structure, which can reduce the parasitic capacitance and leakage current of the substrate. . The application technology of silicon-on-insulator in related fields has been very mature, and strained silicon-on-insulator (sSOI) has also received increasing attention from relevant technical personnel. Silicon-germanium-on-insulator (SGOI) combines the advantages of silicon-germanium materials and silicon-on-insulator, not only It can reduce the parasitic capacitance and leakage current of the substrate, and can also improve the carrier mobility, which has also received extensive attention. Manufacturing smaller-sized, higher-performance devices has always been the goal and direction of the development of the semiconductor industry. As VLSI technology enters the 22nm node and below, higher requirements are placed on the feature size of integrated circuits. In order to further miniaturize devices based on materials-on-insulator, the thickness of materials-on-insulator is required to be thinner, and ultra-thin materials-on-insulator have emerged as the times require.

Usually, the material on the insulator needs to be obtained through two processes of material preparation and layer transfer. The more common layer transfer realization technology is the bonding and peeling process. However, the traditional intelligent peeling method has a thick peeling surface, large peeling cracks, and the surface of the material on the insulator obtained after peeling is very rough, making it difficult to prepare ultra-thin materials on the insulator; and due to the need for a higher injection dose, it not only increases the production time and The cost and the damage to the crystal are relatively large, and it is more difficult to prepare high-quality ultra-thin materials on insulators.

Therefore, how to provide a method for preparing a high-quality semiconductor-on-insulator material with a low implant dose has become an urgent technical problem to be solved by practitioners in the field.

Contents of the invention

In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a method for preparing semiconductor-on-insulator materials using ion implantation technology, which is used to solve the need for higher doses of ion implantation in the prior art to prepare semiconductor-on-insulator materials, Moreover, it is difficult and costly.

In order to achieve the above purpose and other related purposes, the present invention provides a method for preparing a semiconductor-on-insulator material using ion implantation technology, which at least includes the following steps:

1) providing a first substrate, and forming a doped single crystal thin film on the surface of the first substrate;

2) forming a buffer layer on the surface of the single crystal thin film, and forming a top semiconductor material on the surface of the buffer layer;

3) implanting impurity ions into the single crystal thin film from the surface of the top semiconductor material;

4) implanting lift-off ions from the surface of the top-layer semiconductor material to a position at a predetermined depth in the first substrate below the single crystal thin film;

5) providing a second substrate with an insulating layer on the surface, and bonding the insulating layer to the top semiconductor material;

6) Perform annealing treatment to make the single crystal thin film absorb the stripping ions, finally separate the first substrate and the buffer layer from the single crystal thin film, and finally remove the buffer layer.

As a preferred solution of the method for preparing a semiconductor-on-insulator material using ion implantation technology of the present invention, the thickness of the single crystal thin film is not greater than 10 nm.

As a preferred solution of the method for preparing semiconductor-on-insulator materials using ion implantation technology in the present invention, the single crystal thin film is a superlattice structure formed of a single-layer single crystal or more than two layers of single crystal, and the single-crystal thin film The material includes one of Si, Ge, SiGe, GeSn, GaAs and AlGaAs.

Further, the doping ions of the single crystal thin film include one or more of C, B, P, Ga, In, As and Sb, and the total concentration of doping ions is 1E18/cm ³ -1E22/cm ³ .

As a preferred solution of the method for preparing a semiconductor-on-insulator material using ion implantation technology in the present invention, the material of the buffer layer is one of Si, Ge, SiGe, GeSn, GaAs, AlGaAs, and its thickness is not less than 30nm, and , the material of the buffer layer is different from the single crystal thin film.

As a preferred solution of the method for preparing a semiconductor-on-insulator material using ion implantation technology in the present invention, the material of the top layer semiconductor material includes one of Si, Ge, SiGe, GeSn, GaAs and AlGaAs, and the thickness is 5nm-200nm.

As a preferred solution of the method for preparing a semiconductor-on-insulator material using ion implantation technology of the present invention, the impurity ions include one of Si, Ge, H, and He, and the implantation dose is not less than 1E16/cm ² .

As a preferred solution of the method for preparing semiconductor-on-insulator materials using ion implantation technology in the present invention, the stripping ions are H ions, the implantation dose is 1E16/cm ² to 4E16/cm ² , and the preset depth is a single crystal thin film 20nm to 150nm below.

As a preferred solution of the method for preparing a semiconductor-on-insulator material using ion implantation technology in the present invention, in step 6), the buffer layer is removed by chemical etching.

As mentioned above, the present invention provides a method for preparing a semiconductor-on-insulator material using ion implantation technology, comprising the steps of: 1) providing a first substrate, and forming a doped single crystal thin film on the surface of the first substrate; 2) forming a buffer layer on the surface of the single crystal thin film, and forming a top semiconductor material on the surface of the buffer layer; 3) implanting impurity ions into the single crystal thin film from the surface of the top semiconductor material; 4) injecting impurity ions from the top semiconductor material Implanting lift-off ions into the first substrate below the single crystal thin film at a predetermined depth; 5) providing a second substrate with an insulating layer on the surface, and bonding the insulating layer to the top semiconductor material bonding; 6) performing annealing treatment to make the single crystal thin film absorb the stripping ions, finally separate the first substrate and the buffer layer from the single crystal thin film, and finally remove the buffer layer. The invention combines the dual functions of ion co-implantation and stripping of the doped single crystal thin film, and effectively reduces the stripping dosage. Impurity ions are implanted first to cause stress in the single crystal film to increase its adsorption capacity for H ions, and then the stripping is achieved after H ion implantation and annealing. If He is used as the impurity ion, on the one hand, the stress of the single crystal film can be increased, and on the other hand, He can be used as the stripping ion, which greatly reduces the implantation amount of H ions. The stripping crack occurs at the ultra-thin single crystal film, and the crack is very small. High quality semiconductor-on-insulator materials are available.

Description of drawings

FIG. 1 is a schematic flowchart of the steps of the method for preparing a semiconductor-on-insulator material using ion implantation technology according to the present invention.

FIG. 2 shows a schematic structural view of step 1) of the method for preparing a semiconductor-on-insulator material by using ion implantation technology according to the present invention.

FIG. 3 shows a schematic structural diagram presented in step 2) of the method for preparing a semiconductor-on-insulator material using ion implantation technology according to the present invention.

FIG. 4 shows a schematic structural diagram presented in step 3) of the method for preparing a semiconductor-on-insulator material using ion implantation technology according to the present invention.

FIG. 5 shows a schematic structural diagram presented in step 4) of the method for preparing a semiconductor-on-insulator material using ion implantation technology according to the present invention.

FIG. 6 shows a schematic structural diagram presented in step 5) of the method for preparing a semiconductor-on-insulator material by using ion implantation technology according to the present invention.

7 to 9 show the structural schematic diagrams presented in step 6) of the method for preparing a semiconductor-on-insulator material by utilizing ion implantation technology according to the present invention.

Component designation description

101 First Substrate

102 single crystal thin film

103 buffer layer

104 Top Semiconductor Materials

105 insulating layer

106 Second substrate

S11～S16 steps

detailed description

Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.

Please refer to Figure 1 to Figure 9. It should be noted that the diagrams provided in this embodiment are only schematically illustrating the basic idea of the present invention, and only the components related to the present invention are shown in the diagrams rather than the number, shape and shape of the components in actual implementation. Dimensional drawing, the type, quantity and proportion of each component can be changed arbitrarily during actual implementation, and the component layout type may also be more complicated.

As shown in Figures 1 to 9, a method for preparing a semiconductor-on-insulator material using ion implantation technology at least includes the following steps:

As shown in FIGS. 1 to 2 , step 1) S11 is firstly performed to provide a first substrate 101 and form a doped single crystal thin film 102 on the surface of the first substrate 101 .

As an example, the first substrate 101 is a Si substrate. The thickness of the doped single crystal thin film 102 is not more than 10nm, and the single crystal thin film 102 is a superlattice structure formed of a single-layer single crystal or more than two layers of single crystal, and its materials include Si, Ge, SiGe, GeSn, One of GaAs and AlGaAs, the doping ions of the single crystal thin film 102 include one or more of C, B, P, Ga, In, As and Sb, and the total concentration of doping ions is 1E18/ cm ³ ~1E22/cm ³ . Specifically, in this embodiment, a Si substrate is provided, and a SiGe single crystal thin film 102 doped with B is formed on its surface by vapor phase epitaxy, wherein, the thickness of the SiGe single crystal thin film 102 is 3 nm, and the thickness of the B The concentration is 3E19/cm ³ . Since the thickness of the single crystal film 102 is very thin, there is stress inside it, and it has a high ion doping concentration, it can efficiently absorb ions (such as H ions, etc.) for stripping in the subsequent intelligent stripping process. In the final fracture, there is basically no single crystal thin film 102 remaining on the peeled surface, and at most only some burrs exist, which can achieve a very good peeling effect.

As shown in FIG. 1 and FIG. 3 , step 2) S12 is then performed to form a buffer layer 103 on the surface of the single crystal thin film 102 , and to form a top semiconductor material 104 on the surface of the buffer layer 103 .

As an example, a buffer layer 103 is formed on the surface of the single crystal thin film 102 by vapor phase epitaxy, the material of the buffer layer 103 is one of Si, Ge, SiGe, GeSn, GaAs, AlGaAs, and its thickness is not less than 30nm, Moreover, the material of the buffer layer 103 is different from that of the single crystal thin film 102 . In this embodiment, the buffer layer 103 is made of Si and has a thickness of 60 nm. The buffer layer 103 can greatly improve the growth quality of the subsequent top-layer semiconductor material 104 , and can ensure that the subsequent ion stripping process will not introduce defects and other effects on the top-layer semiconductor material 104 .

As an example, the material of the top layer semiconductor material 104 includes one of Si, Ge, SiGe, GeSn, GaAs and AlGaAs, and the thickness is 5 nm˜200 nm. In this embodiment, the material of the top semiconductor material 104 is SiGe, and its thickness is 70nm. Certainly, in other embodiments, the top-layer semiconductor material 104 may also be other expected semiconductor materials selected according to requirements, and is not limited to the ones listed here.

As shown in FIG. 1 and FIG. 4 , step 3) S13 is then performed, and impurity ions are implanted into the single crystal thin film 102 from the surface of the top semiconductor material 104 .

As an example, the impurity ions include one of Si, Ge, H, and He, and the implantation dose is not less than 1E16/cm ² . The implantation of impurity ions can increase the stress in the single crystal thin film 102, so as to improve the adsorption of H ions by the single crystal thin film 102 during the subsequent stripping process. In this embodiment, the impurity ions are He, and the implantation dose is 1E16/cm ² . Using He as the impurity ions can increase the stress of the single crystal thin film 102 on the one hand, and on the other hand, He can be used as stripping ions, greatly The required implantation amount of subsequent H ions is reduced, the process cost is reduced, and the stripping quality is improved.

As shown in FIG. 1 and FIG. 5 , then proceed to step 4) S14 , implanting lift-off ions from the surface of the top semiconductor material 104 to a predetermined depth in the first substrate 101 below the single crystal thin film 102 .

As an example, the stripping ions are H ions, the implantation dose is 1E16/cm ² -4E16/cm ² , and the preset depth is 20 nm - 150 nm below the single crystal thin film 102 . In this embodiment, the implantation dose of H ions is 1E16/cm ² , and the implantation position is a place below the single crystal thin film 102 at a depth of 50 nm from the surface of the first substrate 101 . Certainly, in other embodiments, the stripping ions may also be selected as He, and are not limited to H ions here.

As shown in FIG. 1 and FIG. 6 , step 5) S15 is performed next, providing a second substrate 106 with an insulating layer 105 on its surface, and bonding the insulating layer 105 to the top semiconductor material 104 .

As an example, the second substrate 106 is a Si substrate with an oxide layer on its surface. Specifically, N ₂ is used to perform plasma treatment on the surface of the insulating layer 105 and the top semiconductor material 104 before bonding, and then bond them.

As shown in FIG. 1 and FIG. 7 to FIG. 9, step 6) S16 is finally carried out to perform annealing treatment, so that the single crystal thin film 102 absorbs the stripping ions, and finally the first substrate 101 and the buffer layer 103 is separated from the single crystal thin film 102, and finally the buffer layer 103 is removed.

As an example, the annealing atmosphere used in this embodiment is O ₂ . The annealing treatment includes the following steps: firstly, conduct the first heat preservation at about 300°C for about 120 minutes to strengthen the bonding strength between the insulating layer 105 and the top semiconductor material 104; then, heat at about 600°C Carry out the second heat preservation, and the heat preservation time is about 30 minutes, so that the single crystal thin film 102 absorbs the exfoliated ions in the first substrate 101, and the exfoliated ions gradually gather to generate a large number of bubbles, and finally the single crystal thin film 102 breaking to realize the peeling off of the first substrate 101 and the buffer layer 103 .

As an example, the buffer layer 103 is removed by chemical etching.

As mentioned above, the present invention provides a method for preparing a semiconductor-on-insulator material using ion implantation technology, including the steps: 1) providing a first substrate 101, and forming a doped single crystal film 102 on the surface of the first substrate 101 ; 2) forming a buffer layer 103 on the surface of the single crystal thin film 102, and forming a top semiconductor material 104 on the surface of the buffer layer 103; 3) implanting impurity ions from the surface of the top semiconductor material 104 into the single crystal thin film 102 ; 4) Implanting lift-off ions from the surface of the top semiconductor material 104 to a position at a predetermined depth in the first substrate 101 below the single crystal thin film 102; 5) Providing a second substrate 106 with an insulating layer 105 on its surface , and bond the insulating layer 105 with the top layer semiconductor material 104; 6) perform annealing treatment to make the single crystal thin film 102 absorb the stripping ions, and finally make the first substrate 101 and the The buffer layer 103 is separated from the single crystal thin film 102, and finally the buffer layer 103 is removed. The present invention combines the dual functions of ion co-implantation and stripping of the doped single crystal thin film 102, effectively reducing the stripping dosage. Impurity ions are implanted first to generate stress in the single crystal thin film 102 to increase its ability to absorb H ions, and then the stripping is achieved after H ion implantation and annealing. If impurity ion adopts He, then can increase the stress of single crystal film 102 on the one hand; Small, high-quality semiconductor-on-insulator materials can be obtained. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial application value.

The above-mentioned embodiments only illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical ideas disclosed in the present invention should still be covered by the claims of the present invention.

Claims (8)

1. A method utilizing ion implantation technology to prepare semiconductor-on-insulator material, is characterized in that, at least comprises the following steps: 1) providing a first substrate, forming a doped single crystal thin film on the surface of the first substrate; 2) forming a buffer layer on the surface of the single crystal thin film, and forming a top semiconductor material on the surface of the buffer layer; 3) implanting impurity ions into the single crystal thin film from the surface of the top semiconductor material; 4) implanting stripping ions from the surface of the top semiconductor material to a position at a preset depth in the first substrate below the single crystal film; 5) providing a second substrate with an insulating layer on the surface, and bonding the insulating layer to the top semiconductor material; 6) performing an annealing treatment so that the single crystal thin film absorbs the exfoliation ions located at a preset depth of the first substrate, and the single crystal thin film increases the stress by implanting the impurity ions therein, so as to improve The adsorption of the single crystal thin film to the stripping ions finally separates the first substrate and the buffer layer from the single crystal thin film, and finally removes the buffer layer; Wherein, the stripping ions are H ions, the implantation dose is 1E16/cm ² -4E16/cm ² , and the preset depth is 20nm-50nm below the single crystal thin film; In step 6), the annealing atmosphere is O ₂ , and the annealing treatment includes the steps of: firstly, conducting the first heat preservation at 300°C for 120 minutes to strengthen the bonding between the insulating layer and the top semiconductor material strength; then, conduct a second heat preservation at 600°C for 30 minutes, so that the single crystal thin film can absorb the exfoliation ions in the first substrate, and make the exfoliation ions gradually gather to generate a large number of bubbles , finally breaking the single crystal thin film to realize the peeling off of the first substrate and the buffer layer. 2 . The method for preparing a semiconductor-on-insulator material by ion implantation technology according to claim 1 , wherein the thickness of the single crystal thin film is not greater than 10 nm. 3. The method for preparing a semiconductor-on-insulator material using ion implantation technology according to claim 1, wherein the single crystal thin film is a superlattice structure formed of a single-layer single crystal or more than two layers of single crystals, and the The material of the single crystal thin film includes one of Si, Ge, SiGe, GeSn, GaAs and AlGaAs. 4. The method for preparing semiconductor-on-insulator materials by ion implantation technology according to claim 3, characterized in that: the doping ions of the single crystal thin film include C, B, P, Ga, In, As and Sb One or more than two, the total concentration of dopant ions is 1E18/cm ³ -1E22/cm ³ . 5. The method for preparing semiconductor-on-insulator materials by ion implantation technology according to claim 1, characterized in that: the material of the buffer layer is one of Si, Ge, SiGe, GeSn, GaAs, AlGaAs, and its thickness not less than 30nm, and the material of the buffer layer is different from the single crystal thin film. 6. The method for preparing semiconductor-on-insulator materials using ion implantation technology according to claim 1, characterized in that: the material of the top semiconductor material comprises one of Si, Ge, SiGe, GeSn, GaAs and AlGaAs, and the thickness 5nm to 200nm. 7. The method for preparing a semiconductor-on-insulator material using ion implantation technology according to claim 1, wherein the impurity ions include one of Si, Ge, H, and He, and the implantation dose is not less than 1E16/cm ² . 8. The method for preparing a semiconductor-on-insulator material by ion implantation technology according to claim 1, characterized in that: in step 6), the buffer layer is removed by chemical etching.