CN104347043A - Liquid crystal display panel and method for driving liquid crystal display - Google Patents
Liquid crystal display panel and method for driving liquid crystal display Download PDFInfo
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- CN104347043A CN104347043A CN201310335834.3A CN201310335834A CN104347043A CN 104347043 A CN104347043 A CN 104347043A CN 201310335834 A CN201310335834 A CN 201310335834A CN 104347043 A CN104347043 A CN 104347043A
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Abstract
The invention discloses a liquid crystal display panel and a method for driving a liquid crystal display, wherein the liquid crystal display panel comprises: multiple scanning signal lines Gn}, a plurality of data signal lines { DmA plurality of pixel units { P }n,mA gate driver, and a source driver. Wherein, in a picture period of the LCD panel, the number of scanning signal lines for simultaneously outputting the started scanning signals in the ith time interval is X1The duration of the i-th period is ti(ii) a In the j-th period, the number of scanning signal lines for simultaneously outputting the started scanning signals is X2The duration of the j-th period is tj(ii) a Wherein, if X1>X2Then t isi>tjAnd i is not equal to j, and i and j are positive integers larger than 0. The liquid crystal display panel of the invention adjusts the charging time sequence of the scanning signal, so that the ratio of the channel width to the channel length of the transistor in the pixel is not increased or is not increased too much to cause the loss of the aperture ratio.
Description
Technical field
The present invention is about a kind of method of display panels and driving liquid crystal displays, and particularly relating to one can not increase the display panels of channel width length ratio (W/L) and the method for driving liquid crystal displays.
Background technology
Liquid crystal display device comprises display panels, is formed by liquid crystal born of the same parents and pixel components, and this pixel components combines with corresponding liquid crystal born of the same parents and has liquid crystal capacitor and reservior capacitor; Thin film transistor (TFT), is electrically coupled to this liquid crystal capacitor and reservior capacitor.These pixel components arrange in a matrix fashion, have a large amount of pixel column and pixel column.Typically, sweep signal is sequentially supplied to pixel column for sequentially opening this pixel components by column.When being supplied to pixel column sweep signal, during in order to open the respective films transistor of the pixel components of this pixel column, the source signal (namely signal of video signal) of this pixel column is also provided to described pixel column simultaneously, to be liquid crystal capacitor and the reservior capacitor charging of the correspondence of this pixel column, thus correct the orientation of the corresponding liquid crystal born of the same parents relevant to this pixel column, to control its light transmission.Repeat said process to all pixel columns, then all pixel components have all been provided the corresponding source signal of signal of video signal, thus can show this signal of video signal.
As everyone knows, when this liquid crystal layer there being the voltage of an enough high volt there is the long period, the optical transmission property of liquid crystal molecule can change.This kind of change may be permanent, causes the display quality of this liquid crystal display that the degeneration that can not reverse occurs.In order to stop the degeneration of described liquid crystal molecule, liquid crystal display is driven by the technology of the polarity of voltage alternately changing this liquid crystal of supply born of the same parents usually.These technology can comprise conversion plan (inversion schemes), as frame conversion (frame inversion), row conversion (row inversion), row conversion (column inversion) and some conversion (dot inversion).Typically, although take conversion plan, the image of display better quality still can produce more power consumption because of dipole inversion frequently.Described liquid crystal display, especially tft liquid crystal display device, can consume a large amount of power.
For reaching the method that the power consumption that reduces known liquid crystal display is taked, half source drive (the half source driving of such as pixel, HSD2) framework, wherein each pixel is defined between two adjacent scan signal lines, and be set as comprising first and second switch module (switch module is such as transistor TFT), be electrically coupled to this two adjacent scan signal lines respectively.HSD2 framework by the number of the source electrode distribution that reduces by half, the object that also can reduce by half with the usage quantity reaching source electrode driver (source driver).Therefore, the cost of panel module can significantly be reduced.But the relative minimizing of data signal line, makes sweep signal doubling frequency, then the duration of charging of data signal line to pixel becomes original 1/2, and the impedance as TFT is constant, is difficult to ensure pixel charging complete.For reducing the impedance of TFT, certainly will increase TFT channel width length ratio (W/L, wherein, W is the channel width of TFT, and L is the passage length of TFT), also such as W/L need be greater than same resolution product 2 times, and then increase TFT area, sub-pixel aperture opening ratio is declined.
And in order to further reduce production cost, one is called that three/one source pole drives (one third source driving, OTSD) picture element array structure of framework is suggested, this kind of framework can by the decreased number of source electrode distribution to 1/3rd of script framework, each pixel is defined between two adjacent scan signal lines, and is set as comprising first, second and the 3rd switch.This first and second switch is electrically coupled to this two adjacent scan signal lines respectively, and the 3rd switch is electrically coupled to this first and second switch and is close to the 3rd scan signal line of these adjacent two articles of scan signal lines simultaneously.Therefore more production cost can be saved.But also there is the display panels Problems existing of above-mentioned semi-source pole driving architecture equally.
Summary of the invention
Therefore, an object of the present invention is a kind of method providing display panels and driving liquid crystal displays, it is adjusted by the charging sequential for sweep signal, makes the channel width of transistor in pixel/channel length ratio can not increase or increase too much and cause aperture opening ratio to lose.
For reaching above-mentioned purpose, the invention provides a kind of display panels, this display panels comprises: multi-strip scanning signal wire { G
n, make space arrangement along column direction, wherein n=1,2 ..., N, and N be greater than 0 integer; Many data signal line { D
m, perpendicular to this multi-strip scanning signal wire { G
n, and these many data signal lines make space arrangement, wherein m=1,2 along the line direction of this column direction vertical ..., M, M be greater than 0 integer; Multiple pixel cell { P
n,m, make space arrangement in a matrix fashion and form pel array, each pixel cell P
n,mall be defined in adjacent two scan signal line G
nand G
n+1and adjacent two data signal line D
mand D
m+1between, and each pixel cell comprises multiple sub-pixel; Gate drivers, puts on this multi-strip scanning signal wire { G respectively in order to produce
nmultiple sweep signals; And source electrode driver, put on this many data signal line { D respectively in order to produce
mmultiple data-signals.Wherein, in a picture cycle of display panels, during the i-th period, the quantity simultaneously exporting the scan signal line of the sweep signal of startup is X
1, the duration of this i-th period is t
i; During the jth period, the quantity simultaneously exporting the scan signal line of the sweep signal of startup is X
2, the duration of this jth period is t
j; Wherein, if X
1>X
2, then t
i>t
j, and i is not equal to j, i, j be greater than 0 positive integer.
As optional technical scheme, in this picture cycle, during this i-th period, the quantity simultaneously exporting the scan signal line of the sweep signal of startup is maximum; During this jth period, export the minimum number of the scan signal line of the sweep signal of startup simultaneously.
As optional technical scheme, X
1=bX
2, and t
i=bt
j, wherein b be greater than 1 positive integer.
As optional technical scheme, each sweep signal all has waveform, this waveform has first volt of voltage V1 of first period Γ 1, second volt of voltage V2 of second phase Γ 2, between the third phase, the three volts voltage V3 of Γ 3, wherein follows the second phase closely between the third phase, the second phase follows first period closely, V1=V3>V2, Γ 2=Γ 3/2, Γ 1=Γ 2.
As optional technical scheme, be sequentially shifted for interval with Γ 1+ Γ 2 between the waveform of each sweep signal.
As optional technical scheme, each sweep signal all has waveform, this waveform has first volt of voltage V1 of first period Γ 1, second volt of voltage V2 of second phase Γ 2, the three volts voltage V3 of Γ 3 between the third phase, the 4th volt of voltage V4 of Γ 4 between the fourth phase, and the 5th volt of voltage V5 of Γ 5 between the fifth phase, after wherein (k+1) period Γ (k+1) follows kth period Γ k closely, j=1,2,3,4, V1=V3=V5>V2=V4, Γ 1=Γ 3/2=Γ 5/3, Γ 4=Γ 1, Γ 2=Γ 3.
As optional technical scheme, be sequentially shifted for interval with Γ 1+ Γ 2 between the waveform of each sweep signal.
As optional technical scheme, each pixel cell P
n,mat least comprise the first sub-pixel P
n,m1 and the second sub-pixel P
n,m2, wherein each this first sub-pixel comprises the first pixel electrode and the first transistor, this the first transistor has grid, source electrode and drain electrode and is electrically coupled to this first pixel electrode, each this second sub-pixel includes the second pixel electrode and transistor seconds, this transistor seconds has grid, source electrode and drain electrode and is electrically coupled to this second pixel electrode, wherein:
At pixel cell P
n,min, the first sub-pixel P
n,mthe grid of the first transistor of 1 and source electrode are respectively and be electrically coupled to scan signal line G accordingly individually
n+1with data signal line D
m, and the second sub-pixel P
n,mthe grid of the transistor seconds of 2, source electrode and drain electrode are respectively and be electrically coupled to scan signal line G accordingly individually
n, this first sub-pixel P
n,mthe drain electrode of the first transistor of 1 and this second sub-pixel P
n,msecond pixel electrode of 2; And
At pixel cell P
n+1, min, the first sub-pixel P
n+1, mthe grid of the first transistor of 1 and source electrode are respectively and be electrically coupled to scan signal line G accordingly individually
n+2with data signal line D
m+1, and the second sub-pixel P
n+1, mthe grid of the transistor seconds of 2, source electrode and drain electrode are respectively and be electrically coupled to scan signal line G accordingly individually
n+1, this first sub-pixel P
n+1, mthe drain electrode of the first transistor of 1 and this second sub-pixel P
n+1, msecond pixel electrode of 2.
As optional technical scheme, each pixel cell P
n,mat least comprise the first sub-pixel P
n,m1, the second sub-pixel P
n,m2 and the 3rd sub-pixel P
n,m3, wherein each this first sub-pixel comprises the first pixel electrode and the first transistor, this the first transistor has grid, source electrode and drain electrode are electrically coupled to this first pixel electrode, each this second sub-pixel includes the second pixel electrode and transistor seconds, this transistor seconds has grid, source electrode and drain electrode are electrically coupled to this second pixel electrode, , each the 3rd sub-pixel includes the 3rd pixel electrode and third transistor, this third transistor has grid, source electrode and drain electrode are electrically coupled to the 3rd pixel electrode, wherein:
At pixel cell P
n,min, the first sub-pixel P
n,mthe grid of the first transistor of 1 and source electrode are respectively and be electrically coupled to scan signal line G accordingly individually
nwith data signal line D
m, and the second sub-pixel P
n,mthe grid of the transistor seconds of 2 and drain electrode are respectively and be electrically coupled to scan signal line G accordingly individually
nwith this second sub-pixel P
n,msecond pixel electrode of 2, the 3rd sub-pixel P
n,mthe grid of the third transistor of 3 and drain electrode are respectively and be electrically coupled to scan signal line G accordingly individually
nwith the 3rd sub-pixel P
n,m3rd pixel electrode of 3; And
At pixel cell P
n+1, min, the first sub-pixel P
n+1, mthe grid of the first transistor of 1, source electrode and drain electrode are respectively and be electrically coupled to scan signal line G accordingly individually
n+1, data signal line D
mand this second sub-pixel P
n,mthe source electrode of the transistor seconds of 2, and the second sub-pixel P
n+1, mthe grid of the transistor seconds of 2 and drain electrode are respectively and be electrically coupled to scan signal line G accordingly individually
n+1and the 3rd sub-pixel P
n,mthe source electrode of the third transistor of 3, the 3rd sub-pixel P
n+1, mthe grid of the third transistor of 3 and drain electrode are respectively and be electrically coupled to scan signal line G accordingly individually
n+1and the 3rd sub-pixel P
n+1, m3rd pixel electrode of 3; And
At pixel cell P
n+2min, the first sub-pixel P
n+2, mthe grid of the first transistor of 1, source electrode and drain electrode are respectively and be electrically coupled to scan signal line G accordingly individually
n+2, data signal line D
mand this second sub-pixel P
n+1, mthe source electrode of the transistor seconds of 2, and the second sub-pixel P
n+2, mgrid and the drain electrode of the transistor seconds of 2 are electrically coupled to scan signal line G respectively
n+2and the 3rd sub-pixel P
n+1, mthe source electrode of the third transistor of 3, the 3rd sub-pixel P
n+2, mgrid and the drain electrode of the third transistor of 3 are electrically coupled to scan signal line G respectively
n+1and the 3rd sub-pixel P
n+2, m3rd pixel electrode of 3.
As optional technical scheme, any two neighbors wherein in the plurality of data-signal have opposite polarity.
The present invention also provides a kind of method of driving liquid crystal displays, and the method comprises the following steps: provide a kind of display panels as above; And apply the plurality of sweep signal respectively to this multi-strip scanning signal wire { G
n, apply the plurality of data-signal respectively to these many data signal line { D
m, wherein the plurality of sweep signal is connected to this multi-strip scanning signal wire { G with a set sequential conducting
ncorresponding transistor.
Compared with prior art, the method of display panels of the present invention and driving liquid crystal displays, it adjusts the duration of charging of this period according to the quantity that each period in a picture cycle opens scan signal line simultaneously, the quantity of the scan signal line such as simultaneously opened is more, the duration of charging of this period is relatively longer, it is the longest that scan signal line opens maximum duration of charging period simultaneously, sequentially successively decreases, and it is the shortest that scan signal line opens minimum duration of charging period simultaneously.Thus make the channel width of the transistor in pixel itself/channel length ratio can not increase or increase too much and cause aperture opening ratio to lose whereby.
Can be further understood by following detailed Description Of The Invention and institute's accompanying drawings about the advantages and spirit of the present invention.
Accompanying drawing explanation
Figure 1 shows that the schematic section layout view of the display panels of first embodiment of the invention;
Figure 2 shows that another part layout view of the panel of LCD of the first embodiment of the present invention;
Figure 3 shows that the oscillogram of the drive singal being applied to display panels in Fig. 2;
Figure 4 shows that the schematic section layout view of the display panels of second embodiment of the invention;
Figure 5 shows that the oscillogram of the drive singal being applied to display panels in Fig. 4.
Embodiment
Hereafter with various embodiment, the present invention is described in detail, but the use for illustrative purposes only of embodiment herein, because those skilled in the art are when making various retouching and amendment based on the present invention.Hereafter will be elaborated various embodiments of the present invention, the identical label of appended accompanying drawing represents same components.In this instructions and claims, " one ", " this " and " this " of indication includes many, unless herein clear stipulaties its represent the meaning of odd number.Equally, unless separately had clear stipulaties herein, herein indication " ... interior " also comprise " and ... on " meaning.
The term of stating in this instructions generally represents the ordinary meaning of this area.Particular term in this instructions other parts or hereinafter will be inquired into, the invention provides additional guiding for implementer understands.Each embodiment involved by this instructions, comprises various term, only for illustrating the present invention, and does not make any restriction to scope of the present invention and main idea.Equally, the present invention is also not limited to the embodiment that this instructions provides.
Hereafter composition graphs 1-Fig. 5 is described in detail embodiments of the invention.According to object of the present invention, as deeply disclosed widely, one aspect of the present invention, about a kind of display panels herein; The present invention also comprises the method for the liquid crystal display of described display panels about a kind of driving on the other hand.Liquid crystal display includes display panels and backlight module, and backlight module provides light source for display panels.
Refer to Fig. 1, Figure 1 shows that the schematic section layout view of the display panels of first embodiment of the invention.Display panels provided by the invention (Liquid Crystal Display; LCD) 100 comprise source electrode driver (source driver), gate drivers (gatedriver) and time schedule controller (timing controller, T-con), time schedule controller connects source electrode driver and gate drivers, in order to control the running of source electrode driver and gate drivers.In addition, display panels 100 comprises multi-strip scanning signal wire { G
n, that is G
1, G
2... G
n, G
n+1, G
n+2, G
n+3... G
n, make space arrangement along row (horizontal, level) direction 140; And many data signal line { D
m, that is D
1, D
2... D
m, D
m+1, D
m+2, D
m+3..., D
mthrough this multi-strip scanning signal wire G
1, G
2... G
n, G
n+1, G
n+2, G
n+3... GN makes space arrangement along the line direction (vertical, vertical) 130 of this column direction vertical.Wherein, n=1,2 ..., N, m=1,2 ..., M, and M and N be greater than 0 integer.LCD 100 also comprises multiple pixel cell { P
n,m, make space arrangement in a matrix fashion and form pel array.Each pixel cell P
n,mall be defined in two adjacent scan signal line G
nand G
n+1, and adjacent two data signal line D
mand D
m+1between.Each pixel cell P
n,mbe made up of two or more sub-pixels.Wherein, above-mentioned picture element array structure can be that semi-source pole driving architecture (half source driving, HSD) or three/one source pole drive framework (one third source driving, OTSD).
Please continue see Fig. 1, it is also the schematic diagram that half source drives the picture element array structure of the display panels of framework, and the present embodiment for convenience of description, Fig. 1 only depicts three scan signal line G of the arranged adjacent successively in LCD 100
n, G
n+1, G
n+2, and two data signal line D
mwith D
m+1, and two corresponding pixels.Pixel cell P
n,mthere is the first sub-pixel P
n,m1 and the second sub-pixel P
n,m2.Wherein the first sub-pixel P
n,m1 comprise the first pixel electrode 115a, be electrically coupled to the first liquid crystal capacitance between the first pixel electrode 115a and shared electrode and the first transistor 112 in parallel, the first transistor 112 has grid 112g, source electrode 112s and drain electrode 112d is electrically coupled to the first pixel electrode 115a, the second sub-pixel P
n,m2 comprise the second pixel electrode 115b, be electrically coupled to the second liquid crystal capacitance between the second pixel electrode 115b and shared electrode and transistor seconds 116 in parallel, transistor seconds 116 has grid 116g, source electrode 116s and drain electrode 116d is electrically coupled to the second pixel electrode 115b.Wherein shared electrode (not drawing in figure), itself and each pixel cell P
n,mthe first pixel electrode relevant to the second pixel electrode and formed.In one embodiment, each pixel cell P
n,mthe first sub-pixel P
n,mthe first pixel electrode 115a of 1 and the second sub-pixel P
n,mthe second pixel electrode 115b deposition of 2 (does not show) on the first substrate herein, and shared electrode is then deposited over and second substrate (does not show) and spatially spaced apart with first substrate herein.Liquid crystal molecule is then filled between aforesaid first substrate and second substrate.Each unit is associated with a pixel cell P of display panels 100
n,m, the voltage be applied on pixel electrode then arranges in order to the direction controlled corresponding to the liquid crystal molecule of sub-pixel.
In one embodiment, this the first transistor 112, transistor seconds 116 are such as thin film transistor (TFT) (Thin Film Transistor) or mos field effect transistor (Metal Oxide Semiconductor Field Effect Transistor), and are applicable to start the first sub-pixel P respectively
n,m1 and the second sub-pixel P
n,m2.The transistor of other type also may be used for realizing the present invention.By applying sweep signal to the scan signal line G with the grid 112g of the first transistor 112 and the grid 116g electric property coupling of transistor seconds 116
n+1and G
n, the first transistor 112 and transistor seconds 116 are chosen to and then conducting, now, by respectively to the first sub-pixel P
n,m1 and the second sub-pixel P
n,mthe mode of the corresponding liquid crystal capacitance charging of 2, puts on corresponding data signal wire D
mor D
m+1data-signal be incorporated in the first sub-pixel P
n,m1 and the second sub-pixel P
n,m2.Pixel cell P
n,mthe first sub-pixel P
n,m1 and the second sub-pixel P
n,mthe charging voltage of the liquid crystal capacitance of 2 is corresponding with the electric field putting on liquid crystal molecule corresponding between first substrate and second substrate.
At pixel cell P
n,min, the first sub-pixel P
n,mthe grid 112g of the first transistor 112 of 1 and source electrode 112s respectively and be electrically coupled to scan signal line G accordingly individually
n+1with data signal line D
m, and the second sub-pixel P
n,mgrid 116g, the source electrode 116s of the transistor seconds 116 of 2 and drain electrode 116d are respectively and be electrically coupled to scan signal line G accordingly individually
n, the first sub-pixel P
n,mthe drain electrode 112d(of the first transistor 112 of 1 or the first pixel electrode 115a) and the second sub-pixel P
n,mthe second pixel electrode 115b of 2; Further,
At pixel cell P
n+1, min, the first sub-pixel P
n+1, mthe grid 112g of the first transistor 112 of 1 and source electrode 112s respectively and be electrically coupled to scan signal line G accordingly individually
n+2with data signal line D
m+1, and the second sub-pixel P
n+1, mgrid 116g, the source electrode 116s of the transistor seconds 116 of 2 and drain electrode 116d are respectively and be electrically coupled to scan signal line G accordingly individually
n+1, the first sub-pixel P
n+1, mthe drain electrode 112d of the first transistor 112 of 1 and the second sub-pixel P
n+1, mthe second pixel electrode 115b of 2.
Gate drivers is applied to multi-strip scanning signal wire { G respectively in order to produce
nmultiple sweep signal { g
n.Multiple sweep signal { g
nto open with set sequential and be connected to multi-strip scanning signal wire { G
nthe first transistor 112 and transistor seconds 116.Source electrode driver puts on many data signal line { D respectively in order to produce
mmultiple data-signal { d
m.Multiple data-signal { d
min wantonly two neighbors, as d
mand d
m+1, there is opposite polarity, such as, if data-signal d
mthere is just/high voltage, then data-signal d
m+1have negative/low-voltage, vice versa.
Under the framework of this pixel arrangement and pixel driver, the data for the image of display are applied to data signal line { D with row inversion mode
m, multiple pixel cell { P at this moment
n,mimage display present with the some inversion mode with high display quality.Because each data signal line D
mall be electrically coupled to the capable P of pixel cell
{ n}, mthe pixel cell capable P adjacent with it
{ n}, m+1, so compared to using traditional some inversion mode, the some reversion of display panels 100 only needs the data signal line { D of half quantity
mcan reach.So panel of LCD 100 also can save the power consumption of traditional some inversion mode display panels half.
In addition, contrast the present invention, in a picture cycle of display panels, during the i-th period, the quantity simultaneously exporting the scan signal line of the sweep signal of startup is X
1, the duration of the i-th period is t
i; During the jth period, the quantity simultaneously exporting the scan signal line of the sweep signal of startup is X
2, the duration of jth period is t
j; Wherein, if X
1>X
2, then t
i>t
j, and i is not equal to j, i, j be greater than 0 positive integer.Further, in this picture cycle, during this i-th period, the quantity simultaneously exporting the scan signal line of the sweep signal of startup is maximum; During this jth period, export the minimum number of the scan signal line of the sweep signal of startup simultaneously.
Wherein in an embodiment, X
1=bX
2, and t
i=bt
j, wherein b be greater than 1 positive integer.That is, the quantity simultaneously exporting the scan signal line of the sweep signal of startup when the i-th period is two, and the quantity that the jth period exports the scan signal line of the sweep signal of startup is 1 simultaneously, then the duration of the i-th period is then the twice of the duration of jth period.That is the optimal charge time i.e. duration of the day part of corresponding startup sweep signal is identical with the required pixel quantity filled, as X
1: X
2=2:1, then the W/L of transistor can be designed to (2+1)/2=1.5, can comparatively originally transistor design (W/L=2) reduce.In addition, above-mentioned i-th period and jth period, within the same picture cycle, can be adjacent period or the period at interval.Certain the present invention is not also limited with above-mentioned, in other embodiment, can adjust according to the duration of actual conditions to day part.
So, display panels of the present invention, by revising the sequential of sweep signal or adjust, according to the number adjustment duration of charging of the scan signal line opened simultaneously, scan signal line open simultaneously maximum during the duration of charging the longest, sequentially successively decrease, scan signal line open simultaneously minimum during shortest time.
The present invention will be described for the concrete sequential in conjunction with concrete LCD type structure and drive singal below.
Refer to Fig. 2 and Fig. 3, Figure 2 shows that another part layout view of the panel of LCD of the first embodiment of the present invention, Figure 3 shows that the oscillogram of the drive singal being applied to display panels in Fig. 2, and these waveforms are in order to charge to corresponding pixel electrode 215a and 215b.In specific embodiment, the display panels 200 in diagram only partly and schematically show 3 × 3 pixel cells.For example, the pixel in the first row of 3 × 3 pel arrays is called as pixel cell P respectively
0,0, P
1,0and P
2,0.Each pixel cell has the first pixel electrode 215a, the second pixel electrode 215b, the first transistor 212 and transistor seconds 216, and each transistor 212 or 216 has drain electrode, source electrode and grid.The first transistor 212 of each pixel cell and the grid electric property coupling of transistor seconds 216 to a pair adjacent scan signal line, as G
0and G
1, G
1and G
2, G
2and G
3, and define a pixel cell by said method.The first transistor 212 of each pixel cell and the drain electrode of transistor seconds 216 are electrically coupled to the first pixel electrode 215a and the second pixel electrode 215b of above-mentioned pixel cell respectively.
To by a pair adjacent scan signal line G
0and G
1the pixel cell P of the first pixel cell row defined
0,0, P
0,1and P
0,2, each pixel cell P
0,0, P
0,1or P
0,2the source electrode of the first transistor 212 be electrically connected to corresponding data signal line D
0, D
1or D
2, and each pixel cell P
0,0, P
0,1or P
0,2the source electrode of transistor seconds 216 be electrically connected to the first pixel electrode 215a of this pixel cell.But, to by a pair scan signal line G
1and G
2the pixel P of the second pixel cell row of definition
1,0, P
1,1and P
1,2, each pixel cell P
1,0, P
1,1or P
1,2the source electrode of the first transistor 212 be electrically connected to the second pixel electrode 215b of this pixel cell, and each pixel cell P
1,0, P
1,1or P
1,2the source electrode of transistor seconds 216 be electrically connected to corresponding data signal line D
1, D
2or D
3.As shown in Figure 3, the arrangement of pixel cell can repeat once between two adjacent pixel unit row.Scan signal line G
0with data signal line D
0be usually used in inputting mute signal (dummy signals).
In one embodiment, drive singal comprises and is applied to scan signal line G respectively
1, G
2and G
3three sweep signal g
1, g
2and g
3, be applied to data signal line D respectively
1and D
2two data-signal d
1and d
2, and be applied to the shared signal V of shared electrode (not showing) herein
com.Sweep signal g
1, g
2and g
3produced by gate drivers.Each sweep signal g
1, g
2and g
3there is waveform.Waveform has first volt of voltage V1 of first period Γ 1, second volt of voltage V2 of second phase Γ 2, the three volts voltage V3 of Γ 3 between the third phase, wherein follow the second phase closely between the third phase, the second phase follows first period closely, V1=V3>V2, Γ 2=Γ 3/2, Γ 1=Γ 2.In the present embodiment, V1 (V3) and V2 corresponding high volt voltage and low volt voltage respectively, in order to effectively open and close the corresponding transistor of corresponding pixel cell row, V1 (V3) and V2 is for laying respectively at corresponding high voltage and low-voltage.In order to according to both definite sequence activation three pixel cells row, each sweep signal g
1, g
2or g
3waveform in order by another one translation (shifted) it.In an instantiation, sweep signal g
2by sweep signal g
1translation cycle Γ 1+ Γ 2, and sweep signal g
3by sweep signal g
2translation cycle Γ 1+ Γ 2.
Share signal V
comthere is a constant voltage (current potential).Data-signal d
1and d
2produced according to the image being about to show in these pixels, and there is contrary polarity.In other words, if data-signal d
1there is positive voltage, data-signal d
2then have negative voltage, vice versa.In a particular embodiment, data-signal d
1there is positive voltage, data-signal d
2then there is negative voltage.
As shown in Figure 3, in T picture cycle (that is T frame), t
1during the period, scan signal line G
1, G
2open, scan signal line G
1, G
2on sweep signal g
1, g
2make the first transistor 212 and transistor seconds 216 conducting of electric property coupling with it, and be connected to scan signal line G
3the first transistor 212 and transistor seconds 216 for closing.Therefore, by data signal line D
1apply data-signal d
1(bearing) is to pixel cell P
1,0the source electrode of the first transistor 212, to pixel cell P
1,0the first sub-pixel and the second sub-pixel charging, pixel cell P
1,0the first pixel electrode 215a can produce positive voltage; At the same time, by data signal line D
2apply data-signal d
2(just) to pixel cell P
1,1the source electrode of the first transistor, to pixel cell P
1,1the first sub-pixel and the second sub-pixel charging, at pixel cell P
1,1the first pixel electrode 215a can produce negative voltage.In figure 3, respectively with "+" and "-" represent at pixel cell P
1,0the positive voltage that produces of the first sub-pixel 215a, and pixel cell P
1,1first sub-pixel 215a produce negative voltage.
In T picture cycle (that is T frame), t
2during the period, scan signal line G
1open, G2 and G
3close, be thus electrically connected to scan signal line G
1the first transistor 212 and transistor seconds 216 for opening, and be connected to scan signal line G
2and G
3brilliant the first transistor 212 and transistor seconds 216 for closing.Therefore, by data signal line D
1apply data-signal d
1(just) to pixel cell P
0,1the source electrode of the first transistor 212, to pixel cell P
0,1the first sub-pixel and the second sub-pixel charging, at pixel cell P
0,1the first pixel electrode can produce a positive voltage; At the same time, by data signal line D
2apply data-signal d
2(bearing) is to pixel cell P
0,2the source electrode of the first transistor 212, to pixel cell P
0,2the first sub-pixel and the second sub-pixel charging, at pixel cell P
0,2the first pixel electrode can produce negative voltage.In Figure 5, respectively with "+" and "-" represent at pixel cell P
0,1first sub-pixel produce positive voltage and pixel cell P
0,2first sub-pixel produce negative voltage.
In T picture cycle (that is T frame), t
3during the period, scan signal line G
1close, G
2and G
3open, be thus electrically connected to scan signal line G
1the first transistor 212 and transistor seconds 216 for closing, and be connected to scan signal line G
2and G
3the first transistor 212 and transistor seconds 216 for opening.Therefore, by data signal line D
1apply data-signal d
1(bearing) is to pixel cell P
2,1the source electrode of the first transistor 212, to pixel cell P
2,1the first sub-pixel and the second sub-pixel charging, at pixel cell P
2,1the second pixel electrode can produce positive voltage, at the same time, by data signal line D
2apply data-signal d
2(just) to pixel cell P
2,2the source electrode of the first transistor 212, to pixel cell P
2,2the first sub-pixel and the second sub-pixel charging, at pixel cell P
2,2the second pixel electrode can produce negative voltage.In Figure 5, respectively with "+" and "-" represent at pixel cell P
2,1second sub-pixel produce positive voltage and pixel cell P
2,2second sub-pixel produce negative voltage.
In T picture cycle (that is T frame), t
4during the period, scan signal line G
1and G
3close, G
2open, be thus electrically connected to scan signal line G
1and G
3the first transistor 212 and transistor seconds 216 for closing, and be connected to scan signal line G
2the first transistor 212 and transistor seconds 216 for opening.Therefore, by data signal line D
1apply data-signal d
1(just) to pixel cell P
1,0the source electrode of the first transistor 212, to pixel cell P
1,0the first sub-pixel and the second sub-pixel charging, at pixel cell P
1,0the second pixel electrode can produce positive voltage, at the same time, by data signal line D
2apply data-signal d
2(bearing) is to pixel cell P
1,1the source electrode of the first transistor 212, to pixel cell P
1,1the first sub-pixel and the second sub-pixel charging, at pixel cell P
1,1the second pixel electrode can produce negative voltage.
From the type of drive of the day part of an above-mentioned picture cycle, because the picture element array structure in present embodiment is semi-source pole driving architecture, so when corresponding scan signal line is opened, corresponding data signal line needs to charge to the first sub-pixel in the pixel cell of this scan signal line electric property coupling and the second sub-pixel, the present invention is directed to this kind of semi-source pole driving architecture, the period of simultaneously opening multi-strip scanning signal wire is lengthened, with realize when the channel width not increasing or unduly increase transistor and length than, the first sub-pixel of the pixel cell be connected with the scan signal line of this unlatching and the charging completely of the second sub-pixel can be realized.Wherein in present embodiment, such as, in T picture cycle, during the 1st period, the quantity of the scan signal line simultaneously opened is 2, and during the 2nd period, the quantity of the scan signal line simultaneously opened is 1, then the duration t of the 1st period
1the duration t of the 2nd period can be greater than
2, and the duration t of special 1st period
1equal the duration t of the 2nd period
2twice.
In addition, according to aforesaid pixel cell arrangement and type of drive, in present embodiment, in the mode of row reversion, data are inputed to data signal line, can at the matrix of pixel cells { P of the display panels 200 for the purpose of image display
n,min to reach some reversion.
Refer to Fig. 4, Figure 4 shows that the schematic section layout view of the display panels of second embodiment of the invention, it is also wherein the schematic diagram that 1/3rd sources drive the picture element array structure of the display panels of framework shown in Fig. 4, for aspect illustrates the present embodiment, three data signal lines only depicting be disposed adjacent between two four scan signal lines in display panels 300 in Fig. 4 and be disposed adjacent, and 6 corresponding pixels.Scan signal line is in order to determine whether to open the pixel of electric property coupling with it, and data signal line is then in order to provide display data to the pixel of electric property coupling with it.
Each pixel cell P
n,mat least comprise the first sub-pixel P
n,m1, the second sub-pixel P
n,m2 and the 3rd sub-pixel P
n,m3, wherein each first sub-pixel P
n,m1 comprises the first pixel electrode and the first transistor 311, and the first transistor 311 has grid 311g, source electrode 311s and drain electrode 311d is electrically coupled to this first pixel electrode, each second sub-pixel P
n,m2 include the second pixel electrode and transistor seconds 312, and transistor seconds 312 has grid 312g, source electrode 312s and drain electrode 312d is electrically coupled to this second pixel electrode, each the 3rd sub-pixel P
n,m3 include the 3rd pixel electrode and third transistor 313, and this third transistor 313 has grid 313g, source electrode 3113s and drain electrode 313d is electrically coupled to the 3rd pixel electrode, wherein:
At pixel cell P
n,min, the first sub-pixel P
n,mthe grid 311g of the first transistor 311 of 1 and source electrode 311s respectively and be electrically coupled to scan signal line G accordingly individually
nwith data signal line D
m, and the second sub-pixel P
n,mthe grid 312g of the transistor seconds 312 of 2 and drain electrode 312d respectively and be electrically coupled to scan signal line G accordingly individually
nwith the second sub-pixel P
n,msecond pixel electrode of 2, the 3rd sub-pixel P
n,mthe grid 313g of the third transistor 313 of 3 and drain electrode 313d respectively and be electrically coupled to scan signal line G accordingly individually
nwith the 3rd sub-pixel P
n,m3rd pixel electrode of 3; And
At pixel cell P
n+1, min, the first sub-pixel P
n+1, mthe grid of the first transistor of 1, source electrode and drain electrode are respectively and be electrically coupled to scan signal line G accordingly individually
n+1, data signal line D
mand this second sub-pixel P
n,mthe source electrode of the transistor seconds of 2, and the second sub-pixel P
n+1, mthe grid of the transistor seconds of 2 and drain electrode are respectively and be electrically coupled to scan signal line G accordingly individually
n+1and the 3rd sub-pixel P
n,mthe source electrode of the third transistor of 3, the 3rd sub-pixel P
n+1, mthe grid of the third transistor of 3 and drain electrode are respectively and be electrically coupled to scan signal line G accordingly individually
n+1and the 3rd sub-pixel P
n+1, m3rd pixel electrode of 3; And
At pixel cell P
n+2min, the first sub-pixel P
n+2, mthe grid of the first transistor of 1, source electrode and drain electrode are respectively and be electrically coupled to scan signal line G accordingly individually
n+2, data signal line D
mand this second sub-pixel P
n+1, mthe source electrode of the transistor seconds of 2, and the second sub-pixel P
n+2, mgrid and the drain electrode of the transistor seconds of 2 are electrically coupled to scan signal line G respectively
n+2and the 3rd sub-pixel P
n+1, mthe source electrode of the third transistor of 3, the 3rd sub-pixel P
n+2, mgrid and the drain electrode of the third transistor of 3 are electrically coupled to scan signal line G respectively
n+1and the 3rd sub-pixel P
n+2, m3rd pixel electrode of 3.
Specifically describe below in conjunction with Fig. 5 a kind of method that driving comprises the liquid crystal display of display panels in Fig. 4, Figure 5 shows that the oscillogram of the drive singal being applied to display panels in Fig. 4 is also and be sequentially supplied to scan signal line G
n, G
n+1, G
n+2, G
n+3drive singal g
n, g
(n+1), g
(n+2), and g
(n+3)and be supplied to the data-signal d of data signal line Dm, Dm+1
mand d
(m+1)sequential chart.G
n, g
(n+1), g
(n+2), and g
(n+3)produced by gate drivers.Each sweep signal g
n, g
(n+1), g
(n+2), and g
(n+3)there is waveform.Waveform has first volt of voltage V1 of first period Γ 1, second volt of voltage V2 of second phase Γ 2, the three volts voltage V3 of Γ 3 between the third phase, the 4th volt of voltage V4 of Γ 4 between the fourth phase, and the 5th volt of voltage V5 of Γ 5 between the fifth phase, after wherein (k+1) period Γ (k+1) follows kth period Γ k closely, j=1,2,3,4, V1=V3=V5>V2=V4, Γ 1=Γ 3/2=Γ 5/3, Γ 4=Γ 1, Γ 2=Γ 3.In the present embodiment, V1 (V3) and V2 corresponding high volt voltage and low volt voltage respectively, in order to effectively open and close the corresponding transistor of corresponding pixel cell row, V1 (V3, V5) and V2 (V4) is for laying respectively at corresponding high voltage and low-voltage.In order to according to both definite sequence activation three pixel cells row, each sweep signal g
n, g
(n+1), g
(n+2), or g
(n+3)waveform in order by another one translation (shifted) it.In an instantiation, sweep signal g
(n+1)by sweep signal g
ntranslation cycle Γ 1+ Γ 2, and sweep signal g
(n+2)by sweep signal g
(n+1)translation cycle Γ 1+ Γ 2, and sweep signal g
(n+3)by sweep signal g
(n+2)translation cycle Γ 1+ Γ 2.
Share signal V
comthere is a constant voltage (current potential).Data-signal d
mand d
(m+1)produced according to the image being about to show in these pixels, and there is contrary polarity.In other words, if data-signal d
mthere is positive voltage, data-signal d
(m+1)then have negative voltage, vice versa.In a particular embodiment, data-signal d
mthere is positive voltage, data-signal d
(m+1)then there is negative voltage.
As shown in Figure 5, in T picture cycle (that is T frame), t
1during the period, scan signal line G
n, G
n+1, G
n+2open, scan signal line G
n, G
n+1, G
n+2on sweep signal g
n, g
(n+1), g
(n+2)make the first transistor 311 of electric property coupling with it, transistor seconds 312, third transistor 313 conducting, and be connected to scan signal line G
n+3the first transistor 311, transistor seconds 312, third transistor 313 is for closing.
In T picture cycle (that is T frame), t
2during the period, scan signal line G
n, G
n+1open, scan signal line G
n, G
n+1on sweep signal g
n, g
(n+1)make the first transistor 311 of electric property coupling with it, transistor seconds 312, third transistor 313 conducting, and be connected to scan signal line G
n+2, G
n+3the first transistor 311, transistor seconds 312, third transistor 313 is for closing.
In T picture cycle (that is T frame), t
3during the period, scan signal line G
nopen, with scan signal line G
nthe first transistor 311 of electric property coupling, transistor seconds 312, third transistor 313 conducting, and be connected to scan signal line G
n+1, G
n+2, G
n+3the first transistor 311, third transistor 312, transistor seconds 313.
In T picture cycle (that is T frame), t
4during the period, scan signal line G
n+1, G
n+2, G
n+3open, with scan signal line G
n+1, G
n+2, G
n+3the first transistor 311 of electric property coupling, transistor seconds 312, third transistor 313 conducting, and be connected to scan signal line G
nthe first transistor 311, transistor seconds 312, third transistor 313 is for closing.
In T picture cycle (that is T frame), t
5during the period, scan signal line G
n+1, G
n+2open, with scan signal line G
n+1, G
n+2the first transistor 311 of electric property coupling, transistor seconds 312, third transistor 313 conducting, and be connected to scan signal line G
n, G
n+3the first transistor 311, transistor seconds 312, third transistor 313 is for closing.
In T picture cycle (that is T frame), t
6during the period, scan signal line G
n+1open, with scan signal line G
n+1the first transistor 311 of electric property coupling, transistor seconds 312, third transistor 313 conducting, and be connected to scan signal line G
n, G
n+2, G
n+3the first transistor 311, third transistor 312, transistor seconds 313 is for closing.
In T picture cycle (that is T frame), t
7during the period, scan signal line G
n+2, G
n+3open, with scan signal line G
n+2, G
n+3the first transistor 311 of electric property coupling, transistor seconds 312, third transistor 313 conducting, and be connected to scan signal line G
n, G
n+1the first transistor 311, transistor seconds 312, third transistor 313 is for closing.
In T picture cycle (that is T frame), t
8during the period, scan signal line G
n+2, G
n+3open, with scan signal line G
n+2, G
n+3the first transistor 311 of electric property coupling, transistor seconds 312, third transistor 313 conducting, and be connected to scan signal line G
n, G
n+1the first transistor 311, transistor seconds 312, third transistor 313 is for closing.
In T picture cycle (that is T frame), t
9during the period, scan signal line G
n+2open, with scan signal line G
n+2the first transistor 311 of electric property coupling, transistor seconds 312, third transistor 313 conducting, and be connected to scan signal line G
n, G
n+1, G
n+3the first transistor 311, transistor seconds 312, third transistor 313 is for closing.
From the type of drive of the day part of an above-mentioned picture cycle, because the picture element array structure in present embodiment is that three/one source pole drives framework, so when corresponding scan signal line is opened, corresponding data signal line need to the first sub-pixel in the pixel cell of this scan signal line electric property coupling, second sub-pixel and the 3rd sub-pixel charge, the present invention is directed to this kind and drive framework, the period of simultaneously opening multi-strip scanning signal wire is lengthened, with realize when the channel width not increasing or unduly increase transistor and length than, the first sub-pixel of the pixel cell be connected with the scan signal line of this unlatching can be realized, the charging completely of the second sub-pixel and the 3rd sub-pixel.Wherein in present embodiment, such as, in T picture cycle, during the 1st period, the quantity of the scan signal line simultaneously opened is 3, and during the 2nd period, the quantity of the scan signal line opened is 2 simultaneously, and during the 3rd period, the quantity of the scan signal line simultaneously opened is 1, then the duration t of the 1st period
1the duration t of the 2nd period can be greater than
2, the duration t of the 2nd period
2the duration t of the 3rd period can be greater than
3, and the duration t of special 1st period
1equal the duration t of the 2nd period
2twice, the duration t of the 1st period
1equal the duration t of the 3rd period
3three times, for t
4-t
9period is also so same.
In addition, according to aforesaid pixel arrangement and type of drive, in present embodiment, in the mode of row reversion, data are inputed to data signal line, can at the picture element matrix { P of the display panels 300 for the purpose of image display
n,min to reach some reversion.
In sum, the method of display panels of the present invention and driving liquid crystal displays, it adjusts the duration of charging of this period according to the quantity that each period in a picture cycle opens scan signal line simultaneously, the quantity of the scan signal line such as simultaneously opened is more, the duration of charging of this period is relatively longer, it is the longest that scan signal line opens maximum duration of charging period simultaneously, sequentially successively decreases, and it is the shortest that scan signal line opens minimum duration of charging period simultaneously.Thus make the channel width of the transistor in pixel itself/channel length ratio can not increase or increase too much and cause aperture opening ratio to lose whereby.
By the above detailed description of preferred embodiments, be wish clearly to describe feature of the present invention and spirit, and not with above-mentioned disclosed preferred embodiment, protection scope of the present invention limited.On the contrary, its objective is wish to contain various change and tool equality be arranged in the present invention institute in the protection domain of claim applied for.Therefore, the protection domain of the claim that the present invention applies for should do the broadest explanation, with the arrangement causing it to contain all possible change and tool equality according to above-mentioned explanation.
Claims (10)
1. a display panels, is characterized in that this display panels comprises:
Multi-strip scanning signal wire { G
n, make space arrangement along column direction, wherein n=1,2 ..., N, and N be greater than 0 integer;
Many data signal line { D
m, perpendicular to this multi-strip scanning signal wire { G
n, and these many data signal lines make space arrangement, wherein m=1,2 along the line direction of this column direction vertical ..., M, M be greater than 0 integer;
Multiple pixel cell { P
n,m, make space arrangement in a matrix fashion and form pel array, each pixel cell P
n,mall be defined in adjacent two scan signal line G
nand G
n+1and adjacent two data signal line D
mand D
m+1between, and each pixel cell comprises multiple sub-pixel;
Gate drivers, puts on this multi-strip scanning signal wire { G respectively in order to produce
nmultiple sweep signals; And
Source electrode driver, puts on this many data signal line { D respectively in order to produce
mmultiple data-signals;
Wherein, in a picture cycle of display panels, during the i-th period, the quantity simultaneously exporting the scan signal line of the sweep signal of startup is X
1, the duration of this i-th period is t
i; During the jth period, the quantity simultaneously exporting the scan signal line of the sweep signal of startup is X2, and the duration of this jth period is t
j; Wherein, if X
1>X
2, then t
i>t
j, and i is not equal to j, i, j be greater than 0 positive integer.
2. display panels as claimed in claim 1, it is characterized in that in this picture cycle, during this i-th period, the quantity simultaneously exporting the scan signal line of the sweep signal of startup is maximum; During this jth period, export the minimum number of the scan signal line of the sweep signal of startup simultaneously.
3. display panels as claimed in claim 1, is characterized in that X
1=bX
2, and t
i=bt
j, wherein b be greater than 1 positive integer.
3. display panels as claimed in claim 1, it is characterized in that each sweep signal all has waveform, this waveform has first volt of voltage V1 of first period Γ 1, second volt of voltage V2 of second phase Γ 2, between the third phase, the three volts voltage V3 of Γ 3, wherein follows the second phase closely between the third phase, the second phase follows first period closely, V1=V3>V2, Γ 2=Γ 3/2, Γ 1=Γ 2.
4. display panels as claimed in claim 3, is characterized in that, be sequentially shifted between the waveform of each sweep signal with Γ 1+ Γ 2 for interval.
5. display panels as claimed in claim 1, it is characterized in that each sweep signal all has waveform, this waveform has first volt of voltage V1 of first period Γ 1, second volt of voltage V2 of second phase Γ 2, the three volts voltage V3 of Γ 3 between the third phase, the 4th volt of voltage V4 of Γ 4 between the fourth phase, and the 5th volt of voltage V5 of Γ 5 between the fifth phase, after wherein (k+1) period Γ (k+1) follows kth period Γ k closely, j=1,2,3,4, V1=V3=V5>V2=V4, Γ 1=Γ 3/2=Γ 5/3, Γ 4=Γ 1, Γ 2=Γ 3.
6. display panels as claimed in claim 5, is characterized in that, be sequentially shifted between the waveform of each sweep signal with Γ 1+ Γ 2 for interval.
7. display panels as claimed in claim 1, is characterized in that each pixel cell P
n,mat least comprise the first sub-pixel P
n,m1 and the second sub-pixel P
n,m2, wherein each this first sub-pixel comprises the first pixel electrode and the first transistor, this the first transistor has grid, source electrode and drain electrode and is electrically coupled to this first pixel electrode, each this second sub-pixel includes the second pixel electrode and transistor seconds, this transistor seconds has grid, source electrode and drain electrode and is electrically coupled to this second pixel electrode, wherein:
At pixel cell P
n,min, the first sub-pixel P
n,mthe grid of the first transistor of 1 and source electrode are respectively and be electrically coupled to scan signal line G accordingly individually
n+1with data signal line D
m, and the second sub-pixel P
n,mthe grid of the transistor seconds of 2, source electrode and drain electrode are respectively and be electrically coupled to scan signal line G accordingly individually
n, this first sub-pixel P
n,mthe drain electrode of the first transistor of 1 and this second sub-pixel P
n,msecond pixel electrode of 2; And
At pixel cell P
n+1, min, the first sub-pixel P
n+1, mthe grid of the first transistor of 1 and source electrode are respectively and be electrically coupled to scan signal line G accordingly individually
n+2with data signal line D
m+1, and the second sub-pixel P
n+1, mthe grid of the transistor seconds of 2, source electrode and drain electrode are respectively and be electrically coupled to scan signal line G accordingly individually
n+1, this first sub-pixel P
n+1, mthe drain electrode of the first transistor of 1 and this second sub-pixel P
n+1, msecond pixel electrode of 2.
8. display panels as claimed in claim 1, is characterized in that each pixel cell P
n,mat least comprise the first sub-pixel P
n,m1, the second sub-pixel P
n,m2 and the 3rd sub-pixel P
n,m3, wherein each this first sub-pixel comprises the first pixel electrode and the first transistor, this the first transistor has grid, source electrode and drain electrode are electrically coupled to this first pixel electrode, each this second sub-pixel includes the second pixel electrode and transistor seconds, this transistor seconds has grid, source electrode and drain electrode are electrically coupled to this second pixel electrode, , each the 3rd sub-pixel includes the 3rd pixel electrode and third transistor, this third transistor has grid, source electrode and drain electrode are electrically coupled to the 3rd pixel electrode, wherein:
At pixel cell P
n,min, the first sub-pixel P
n,mthe grid of the first transistor of 1 and source electrode are respectively and be electrically coupled to scan signal line G accordingly individually
nwith data signal line D
m, and the second sub-pixel P
n,mthe grid of the transistor seconds of 2 and drain electrode are respectively and be electrically coupled to scan signal line G accordingly individually
nwith this second sub-pixel P
n,msecond pixel electrode of 2, the 3rd sub-pixel P
n,mthe grid of the third transistor of 3 and drain electrode are respectively and be electrically coupled to scan signal line G accordingly individually
nwith the 3rd sub-pixel P
n,m3rd pixel electrode of 3; And
At pixel cell P
n+1, min, the first sub-pixel P
n+1, mthe grid of the first transistor of 1, source electrode and drain electrode are respectively and be electrically coupled to scan signal line G accordingly individually
n+1, data signal line D
mand this second sub-pixel P
n,mthe source electrode of the transistor seconds of 2, and the second sub-pixel P
n+1, mthe grid of the transistor seconds of 2 and drain electrode are respectively and be electrically coupled to scan signal line G accordingly individually
n+1and the 3rd sub-pixel P
n,mthe source electrode of the third transistor of 3, the 3rd sub-pixel P
n+1, mthe grid of the third transistor of 3 and drain electrode are respectively and be electrically coupled to scan signal line G accordingly individually
n+1and the 3rd sub-pixel P
n+1, m3rd pixel electrode of 3; And
At pixel cell P
n+2min, the first sub-pixel P
n+2, mthe grid of the first transistor of 1, source electrode and drain electrode are respectively and be electrically coupled to scan signal line G accordingly individually
n+2, data signal line D
mand this second sub-pixel P
n+1, mthe source electrode of the transistor seconds of 2, and the second sub-pixel P
n+2, mgrid and the drain electrode of the transistor seconds of 2 are electrically coupled to scan signal line G respectively
n+2and the 3rd sub-pixel P
n+1, mthe source electrode of the third transistor of 3, the 3rd sub-pixel P
n+2, mgrid and the drain electrode of the third transistor of 3 are electrically coupled to scan signal line G respectively
n+1and the 3rd sub-pixel P
n+2, m3rd pixel electrode of 3.
9. display panels as claimed in claim 1, it is characterized in that, any two neighbors wherein in the plurality of data-signal have opposite polarity.
10. a method for driving liquid crystal displays, is characterized in that the method comprises the following steps:
There is provided a kind of as the display panels in claim 1-9 as described in any one; And
Apply the plurality of sweep signal to this multi-strip scanning signal wire { G
n, and apply the plurality of data-signal to these many data signal line { D
m, wherein the plurality of sweep signal is connected to this multi-strip scanning signal wire { G with a set sequential conducting
ncorresponding transistor.
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|---|---|---|---|
| CN201310335834.3A CN104347043A (en) | 2013-08-02 | 2013-08-02 | Liquid crystal display panel and method for driving liquid crystal display |
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|---|---|---|---|
| CN201310335834.3A CN104347043A (en) | 2013-08-02 | 2013-08-02 | Liquid crystal display panel and method for driving liquid crystal display |
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|---|---|
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| CN110930926A (en) * | 2019-12-09 | 2020-03-27 | 厦门天马微电子有限公司 | Display panel driving method, display driving device and electronic equipment |
| CN110930926B (en) * | 2019-12-09 | 2023-07-25 | 厦门天马微电子有限公司 | Display panel driving method, display driving device and electronic equipment |
| CN113808518A (en) * | 2021-02-23 | 2021-12-17 | 友达光电股份有限公司 | Source driving circuit and driving method thereof |
| CN113808518B (en) * | 2021-02-23 | 2023-09-26 | 友达光电股份有限公司 | Source driving circuit and driving method thereof |
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Application publication date: 20150211 |