CN104303405B - For the gate drivers of power inverter - Google Patents

Abstract

Provide a kind of gate drivers for power inverter, wherein described gate drivers include low-side circuitry and are coupled to the high lateral circuit of low-side circuitry, wherein described high side circuit includes detection circuit, and the detection circuit is adapted to provide the error signal of the fault condition of instruction low-side circuitry.

Description

Gate Drivers for Power Converters

technical field

The present invention relates to the field of gate drivers for power converters, in particular to gate drivers for power converters having a plurality of power converter modules. Furthermore, the invention relates to a power converter comprising a gate driver. Furthermore, the invention relates to a method of operating a gate driver.

Background technique

Electronic converters for multi-megawatt power usually employ a modular approach using multiple inverter modules connected in soft parallel. In such systems, the output of each module is connected to a common load via balanced reactors. The main purpose of the balancing reactor is to accommodate the unavoidable timing and voltage differences between the inverter modules and then provide an important part of the facility by which real current balancing is achieved between the inverter modules.

FIG. 1 schematically shows the electrical system of a wind turbine 100 . The blades 101 of the wind turbine are coupled to a generator 102 which is coupled to the electrical system via a generator circuit breaker (GCB) 103 . The electrical system includes a plurality of balancing reactors 104 that are coupled to the GCB and are used to divert the power generated by the generator into a plurality of inverter or power converter modules 105 connected in parallel for example at several megawatts A range of high power outputs can be handled by the wind turbine's electrical system. The power converters are only schematically depicted in FIG. 1 and each includes a generator bridge 106 , a voltage clamp 107 and a network bridge 108 . The output of the inverter or power converter is coupled to a further balancing reactor 109 which is used to perform unavoidable timing and handle voltage differences between the inverter modules. The output of the further balancing reactor is connected to a network circuit breaker (NCB) 110 and a pulse width modulation filter (PWM) 112 via an inductive device (LN) 111 . The output of the NCB is in turn coupled to a wind turbine transformer 113 and via a further circuit breaker (MVCN) 114 for self-protection of the network to a wind park collector network 115 for conducting the generated electrical power of the wind park.

Furthermore, the electrical system includes a wind turbine controller 116 and a controller 117, both for controlling the inverter or power converter modules.

In a typical LV power converter, a controller operating at ground potential generates turn-on and turn-off command signals for each insulated-gate bipolar transistor (IGBT) gate of a balancing reactor. The IGBT gate operates at a potential of several hundred volts from ground potential and therefore low voltage command signals must be galvanically isolated from the IGBT gate potential. This signal conditioning and isolation is performed by a gate drive circuit or gate driver. The gate drive board has "low side" circuitry that transfers signals to and from the "high side" circuitry by using pulse transformers.

For certain internal component fault conditions, the IGBT turn-off signal from the controller cannot be transmitted to the high side via the pulse transformer in order to turn off the IGBT of the balancing reactor. This represents a temporary loss of control of the conduction state of the IGBT, which may lead to failure of the power converter or inverter.

Thus, there may be a need to provide a method that avoids or at least reduces the probability of such a loss of control.

Contents of the invention

This need can be met by the subject matter according to the independent claims. Advantageous embodiments are described by the dependent claims.

According to an exemplary aspect, there is provided a gate driver for a power converter, wherein the gate driver includes a low-side circuit and a high-side circuit coupled to the low-side circuit, wherein the high-side circuit includes a detection circuit, the The detection circuit is adapted to provide an error signal indicative of a fault condition of the low side circuit.

In particular, the low-side circuit and the high-side circuit may be coupled to each other via a coupling element adapted to transmit signals such as electrical or optical signals, and/or transmit AC current but block DC current.

Thus, the low-side circuit and the high-side circuit can be isolated from each other with respect to DC current. For example, the coupling element may be a transformer or a capacitor. However, the coupling element may be an optical fiber or an optical coupler, both of which are suitable for transmitting signals but blocking current.

It should be noted that the term "gate driver" is not limited to a device adapted to drive the gate of a transistor but has to be understood in a broader sense. In particular, any device adapted or suitable for driving or controlling a switching element by providing a drive, control or switching signal to an input terminal of the switching element may be considered as a gate driver.

The term "detection circuit" may particularly refer to any electronic circuit arrangement adapted and/or adapted to detect a fault condition of the low-side circuit and to provide and/or generate a detection and/or error signal indicative of the fault condition based on the detection .

According to an exemplary aspect, there is provided an electronic converter comprising a gate driver according to an exemplary aspect and a switching element having an input terminal coupled to an output terminal of the gate driver.

According to an exemplary aspect, there is provided a method of operating a gate driver according to any of the exemplary aspects, wherein the method includes detecting an error condition of a low-side circuit at a high-side circuit, the high-side circuit upon detecting the error condition An error signal is generated and provided to the switching element.

According to an exemplary aspect, there is provided a computer program which, when executed by a processor, is adapted for controlling the method according to the exemplary aspect.

As used herein, reference to a computer program is intended to be equivalent to a reference to a program element and/or to a computer-readable medium containing instructions for controlling a processor or computer system to coordinate control of the gate driver The execution of the method that performs the operation. The computer program elements can be implemented as computer-readable instruction code in any suitable programming language (such as, for example, JAVA, C++) and can be stored on a computer-readable medium (removable disk, volatile or non-volatile memory, embedded memory/processor, etc.). The instruction code is operable to program a computer or any other programmable device to carry out the intended functions. The computer program may be available from a network, such as the World Wide Web, from which it may be downloaded.

In particular, the switching element may be a transistor of an electronic converter. In particular, the electronic converter may include a plurality of converter stages or modules, each including at least one gate driver and coupled in parallel in order to increase the amount of current and/or power that can be provided by the electronic converter. The electronic converter, which may be a multi-megawatt power electronic converter, may include balancing reactors adapted to provide timing and/or voltage adaptation or matching for the different converter stages of the electronic converter .

By providing a gate driver adapted to provide an error signal indicative of a fault or a fault condition of a low-side circuit of the gate driver, it may be possible to reduce the probability of inverter or power converter failure. This may be especially true for certain internal component failure conditions, such as sudden loss of power on the "low side" circuit due to shorted components and/or loss of gate drive clock signal. In such a case, a switch-off signal for a switching element, eg a transistor (like an IGBT), may be transmitted from the controller fast enough to be able to switch off the switching element. Thus, temporary loss of control of the conduction state of the switching element can be avoided. In particular, it may be possible to avoid a situation where, if a switching element is on and conducting current at the moment of a fault, it will remain on and conduct current until the power supply to the "high side" electronics fails (restrained by the high side local reservoir capacitor support) collapses to its undervoltage lockout threshold.

Further embodiments of gate drivers are described next. However, corresponding features can also be combined with the electronic converter, the method of operating a gate driver and the computer program.

According to an exemplary embodiment of the gate driver, the low-side circuit and the high-side circuit are galvanically separated from each other. In particular, separation or isolation may be performed by providing a transformer, by an optical fiber or by an optical coupler.

According to an exemplary embodiment, the gate driver further comprises a pulse transformer, wherein the pulse transformer is adapted to couple the low-side circuit to the high-side circuit.

Using a pulse transformer as a means of coupling or isolation provides signal latency (and variation in latency), skew (and variation in skew), voltage isolation capability, lifetime/performance degradation, and cost compared to fiber optic or optical couplers Optimization. A pulse transformer can be used in the form of a voltage pulse latched by the high side to turn on and a pulse to turn off.

According to an exemplary embodiment, the gate driver furthermore comprises an output terminal adapted to be coupled to the switching element in such a way that an error signal is provided at a switching input terminal of the switching element.

In particular, the switching element may be a transistor, preferably a power transistor, and may be an IGBT, MOSFET, BPT, GTO or IGCT.

According to an exemplary embodiment of the gate driver, the fault condition is loss of low-side power supply and/or loss of clock signal of the low-side circuit.

For example, loss of low-side power supply may be caused by a shorted component.

According to an exemplary embodiment of the gate driver, the detection circuit is adapted to provide the error signal in time spans below a predetermined limit.

In particular, the predetermined limit may be defined as a time span short enough to protect the switching element when said switching element is coupled to the gate driver. Examples of predetermined limits may be 1 millisecond, 100 microseconds, 50 microseconds or even 10 microseconds.

According to an exemplary embodiment of the gate driver, the high-side circuit includes a top part and a bottom part.

According to an exemplary embodiment of the gate driver, the high-side circuit includes a power supply circuit and a logic circuit, wherein the high-side power supply circuit is coupled to the low-side power supply circuit.

In particular, the detection circuit may be part of a logic circuit or at least some parts or components of the detection circuit may be part of a logic circuit. However, the detection circuit or at least some parts or components of the detection circuit may be part of the power supply circuit.

According to an exemplary embodiment of the gate driver, the detection circuit comprises a pair of diodes and an RC filter coupled to each other in such a way that a detection signal is generateable.

In particular, the detection circuit may be part of the high-side power supply circuit and the pair of diodes and the RC filter are coupled to each other in such a way that the detection signal is supplied to the logic circuit. The detection signal can be used to generate an error signal or can be an error signal itself, depending on the particular implementation of the detection circuit.

Alternatively or additionally to feeding a pair of diodes and RC filters, it is possible to use ) any other configuration of logic signals. For example, another number of diodes may be used and may thus form at least part of the detection circuit. Likewise, a detection circuit or logic circuit adapted to detect a square wave carrier or a square wave signal modulated onto the power supply may be used. In such cases, an edge-triggered timer/monostable or phase-locked loop can be used to provide a high-speed signal based on the detected presence of a square wave carrier as a detection signal and/or an error signal, which can then be Switching element for switching off the corresponding balancing reactor.

According to an exemplary embodiment of the gate driver, the logic signal is supplied to an AND and/or NAND element having an output terminal, wherein the AND and/or NAND element is adapted to be connected at the output terminal provides an error signal.

The gist of the generalized exemplary embodiments can be seen in providing or generating a detection or error signal indicative of a fault condition and generated at the high side (ie, the high side circuitry of the gate driver). This must be distinguished from phase current measurements performed on the low-side circuit for closed-loop current control, current balancing and overcurrent protection. However, detection on the low side may have some disadvantages in certain cases, which can be avoided when an error signal is generated at the high side. For example, since the error signal is already generated on the high side, the following disadvantages can be avoided: sudden loss of power on the "low side" circuit caused by certain internal component failure conditions (e.g. due to shorted components or loss of gate drive clock signal) Lost), the transistor (eg IGBT) turn-off signal from the controller cannot be transferred to the high side via the pulse transformer to turn off the corresponding transistor.

Generating the error signal on the high side avoids a temporary loss of control of the conduction state of the transistor, which would result in the fact that the IGBT would remain Turns on and conducts current until the power supply to the "high side" electronics fails (supported by the high side local reservoir capacitor) collapses to its undervoltage lockout threshold. At this point, in time (possibly several milliseconds after the fault occurred) the transistor gate will be turned off. However, this delay in turning off the transistor, which could cause damage to the transistor, can be avoided if an error signal has been generated on the high-side circuit.

Using a gate driver according to example embodiments may be particularly useful in situations where:

a) inverter modules or power converter modules are operated in parallel (for example, in a multi-megawatt inverter) and/or

b) Inverter modules are connected to loads that are voltage sources for extended periods of time (e.g. large inductive/PM motors/generators or supply networks), since then additional more serious consequences can occur which need to be sub-millisecond The transistor is turned off within a much shorter time (for example, a few microseconds), otherwise transistor destruction may occur.

Thus, according to an exemplary embodiment, a simple facility on the high side of the gate driver or gate drive electronics can be provided which monitors the health of the low side of the gate driver electronics and possibly autonomously The transistor is turned off for a time (microseconds rather than milliseconds) that is short enough to prevent current from building up to damaging levels during some fault conditions specific to parallel inverters and for connections to AC voltage sources.

Furthermore, inventive ideas can be found in using high-speed monitoring of the existing high-frequency (approximately 500 kHz) power supply (generated by the low-side circuit) as a means of detecting low-side circuit failures quickly enough that no additional complex circuitry or Additional signals to be transmitted across the isolation barrier.

It has to be noted that embodiments have been described with reference to different subject matter. In particular, some embodiments have been described with reference to method type claims whereas other embodiments have been described with reference to apparatus type claims. However, a person skilled in the art will appreciate from the above and the following description that, unless otherwise informed, there is no difference between features relating to different subject matter, especially among method types, apart from any combination of features belonging to one type of subject matter. Any combination between features of the claims and features of device-type claims is also considered to be disclosed together with the present application.

The aspects defined above and further aspects are apparent from the examples of embodiment to be described hereinafter and are explained with reference to the examples of embodiment. The invention will be described in more detail hereinafter with reference to examples of embodiment but the invention is not limited to said examples of embodiment.

Description of drawings

Figure 1 schematically shows a wind turbine.

Figure 2 schematically shows the schematic layout of the gate driver.

FIG. 3 schematically shows a layout of a gate driver according to an exemplary embodiment.

Figure 4 schematically shows a circuit that is used to interpret a fault condition.

Fig. 5 schematically shows an example of a specific fault.

Detailed ways

The illustrations in the figures are schematic. It is noted that in different figures, similar or equivalent elements may be provided with the same reference numerals or reference numerals which differ from the corresponding reference numerals only in the first digit.

FIG. 2 schematically shows the principle layout of the gate driver 200 . In particular, FIG. 2 shows a low-side circuit 201 and a high-side circuit 202 comprising a top portion 203 and a symmetrical bottom portion 204 . The low side circuit and the high side circuit are coupled to each other via a phase transformer or power supply transformer 205 that provides a power supply for the high side circuit. Furthermore, additional transformers 206 and 207 are provided, which couple the low-side circuit with the top and bottom parts of the high-side circuit, respectively.

Additionally, the high-side circuitry includes a power supply circuit 208 that is coupled to a power supply transformer 205 and provides power to the high-side circuitry. In particular, the power supply circuit 208 comprises two parts 209 and 210 forming the power supply for the top part and the bottom part of the high-side circuit, respectively. Each of the two parts of the power supply circuit 208 includes a diode and a capacitor (eg, a local reservoir capacitor), and is connected to the logic part of the top part 211 of the high side circuit and the bottom part 212 of the high side circuit, respectively.

The logic part of the top part 211 of the high side circuit comprises control logic 213 coupled on one side to a signal conditioning unit 214 which is then coupled to a first terminal 215 of the gate driver. On the other side, the control logic 213 is coupled to one 206 of the additional transformers. Similarly, the logic portion of the bottom portion 212 of the high side circuitry includes control logic 216 coupled on one side to a signal conditioning unit 217 which is then coupled to a second terminal 218 of the gate driver. On the other side, the control logic 216 is coupled to another 207 of the additional transformers. Via an additional transformer, a top command signal or top control signal and a bottom command signal or bottom control signal are provided to the top and bottom parts of the high-side circuit, respectively.

The first terminal 215 and the second terminal 218 are coupled to a phase connection element 219 comprising a first transistor 220 coupled in parallel with a diode 221 , wherein the first terminal 215 is connected to the gate of the first transistor 220 . A second transistor 222 of the phase connection element 219 is coupled to the second terminal 218 and is connected in parallel to a second diode 223 . The source of transistor 220 is coupled to voltage DC+ and the source of transistor 222 is coupled to voltage DC−. The drains of the transistors are each coupled to a phase connection, which is then coupled to a balancing reactor 224 .

FIG. 3 schematically shows a layout of a gate driver according to an exemplary embodiment. The gate driver of FIG. 3 is substantially identical to the gate driver depicted in FIG. 2 so that only the differences are described below. In particular, the power supply circuit of the gate driver according to FIG. 3 comprises detection circuits or elements, wherein one detection circuit 330 is provided for the top part of the power supply circuit and a second detection circuit 331 is provided for the bottom part of the power supply circuit part. In particular, each of the first and second detection circuits 330 and 331 includes a pair of diodes 332 and 333 and 334 and 335, respectively, and RC filters 336 and 337, which have time constants in the microsecond range, e.g. Less than 100 microseconds, such as about 2 microseconds. An additional diode combined with a very short time constant RC filter for small discontinuities occurring in the rectified 500kHz square wave) provides rapid drop-off in case of loss of low-side power supply or in case of loss of clock signal signal (which will cause the command signal to freeze in its current state). Thus, the detection circuit provides a function effectively as an "IGBT turn-on enable" signal. The corresponding signal is ANDed with the existing "high side" gate command signal provided by the control logic by AND or NAND elements 338 and 339 respectively. The resulting ANDed signal is provided to a signal conditioning unit and turns off the IGBT within microseconds of a fault occurring on the low side, preventing destructive current evolution.

Alternative solutions include rapid detection (<10 microseconds) of voltage loss and absence of switching of the power supply while maintaining the high-side power supply (energy stored in the reservoir capacitor) for a sufficient time to withstand the Any method of turning off an IGBT in a controlled manner.

These alternative solutions include:

Alternative diode arrangements which result in the generation of the same effective (fast) error signal;

By using an edge triggered timer/monostable or phase locked loop to detect the presence of a square wave carrier, the high speed signal from it can be used to turn off the IGBT.

In the following, some specific fault conditions that may occur are described in more detail.

First the consequences of fault conditions that may occur when inverter modules are operated in parallel will be explained. At any given moment, the total load current on a particular phase is shared equally among the "n" soft-parallel inverter modules so that the current rating of each inverter module is not exceeded. However, if a fault condition (eg, loss of power supply or loss of clock signal) occurs on one of the inverter modules connected in parallel, such that a single IGBT is erroneously held in the ON state for an extended period of time, and the resulting command is issued to turn off the IGBTs, then n-1 IGBTs will turn off immediately, followed by the IGBT with a fault on its gate drive to turn off after a few milliseconds.

The consequence of this is that the prevailing phase current (at the moment of the fault) of n parallel-connected inverter modules will be diverted into the single IGBT that has been kept on, in an amount determined only by the inductance of the balancing reactor rate. Within a few microseconds, the total dominant phase current is delivered to the individual IGBTs. If the prevailing phase current (for n paralleled inverter modules) is greater than the current commutation limit of a single IGBT, this will cause the IGBT to exceed its maximum commutation limit and lead to destruction. The maximum acceptable delay time for safe shutdown after this fault condition is thus:

in , n = number of inverter modules, I = IGBT commutation limit current - instantaneous inverter module phase current before tripping, and V = DC link voltage.

Figure 4 schematically shows a circuit that is used to interpret a fault condition. FIG. 4 schematically shows a plurality of inverter modules 440 , 441 and 442 . For reasons of clarity, for each inverter module only two transistors are shown connected to the balancing reactor via phase connections (cf. Figs. 2 and 3).

In the following, different failure examples are explained with some keywords

• Initial conditions: AC current waveform is negative while operating at the load. Bottom IGBT ( to ) is in the on state and thus conducts the predominant phase current due to the negative polarity of the current. (Over the short time intervals considered below (a few microseconds), and the relatively large supply inductance, the AC current can be viewed as a constant negative current source)

● Malfunction occurs in the above-mentioned low side of the gate driver so that Shutdown command cannot be followed.

● Shutdown command is sent to to , either a) as a result of a fault initiating a trip, or b) as a normal shutdown event.

●Result: to is turned off and keep on

● Instantaneously, at to The corresponding share of the total phase current flowing in is commutated to the corresponding top diode to , while at the same time by The fraction of the current conducted remains at medium conduction (and does not commutate to ).

● obtained to The applied voltage across the current is now opposed to the current, causing the current to decrease, while at the same time The applied voltage across is at the same polarity as the current, causing a corresponding increase in current. The rate of change of current is determined by the DC link voltage as well as to determined by the value of . (as previously described)

● The current eventually (after a few microseconds) at to (and therefore to ) decreases to zero at which point, to is no longer forward biased, and therefore and to The applied voltage across becomes zero, resulting in (almost) zero additional current change (over the microsecond timeframe considered in this scenario)

● The total dominant phase current now flows in middle

● If immediately before the fault, the dominant total phase current for n parallel inverters is greater than The peak current commutation limit, then Neither can it be turned off without breaking it anymore, nor can it stay on without breaking it.

In the following, another situation is described, which corresponds to the situation in which single/parallel inverters or power converters are connected to an AC voltage source.

If a single IGBT is erroneously kept on for an extended period (several milliseconds), then during a half-cycle of the AC voltage source there is a short circuit via:

● Load reactance (main reactor (LN) for network inverters or generator leakage inductance for generator inverters)

●Wrongly turned on IGBT

• Diodes in adjacent phases of the falsely conducting IGBT.

Fig. 5 schematically shows an example of a specific fault. In particular, Figure 5 shows a single IGBT ( ) (maintained in conduction) is an example of the resulting short path (bold). As in Figure 4, only three transistor pairs 550, 551 and 552 connected to balancing reactor 553 are shown for a given inverter module. These three pairs correspond to different phases of the AC current. Additionally, FIG. 5 shows an AC voltage source 554 to which the balancing reactor is coupled.

During the half-cycle of conduction (this can be multiple periods depending on how long the IGBT takes to be off), there will be The determined increase in IGBT/diode current, where E is the EMF of the voltage source and L is the total loop inductance.

Depending on the supplied voltage and inductance, the failure mode of an IGBT can be any of the following:

i) The current exceeds the maximum commutation current.

ii) Damage caused by excessive junction temperature (Tj) due to the heating effect of small (but still excessive) currents for extended periods of time (several milliseconds).

Additionally, the two scenarios described above can be combined in one scenario, resulting in the superposition of the consequences described in the context of Figure 4 and those described in the context of Figure 5:

The dominant phase currents of all paralleled inverters will be delivered to the wrongly conducting IGBTs at a (rapid) rate determined by the balancing reactors.

At the same time, the total prevailing current will also increase at a (less rapid) rate determined by the instantaneous supply EMF and supply/generator impedance.

It should be noted that the term "comprising" does not exclude other elements or steps and "a" or "an" does not exclude a plurality. Likewise, elements described in association with different embodiments may be combined. It should also be noted that reference signs in the claims should not be construed as limiting the scope of the claims.

List of reference signs:

100 wind turbines

101 blade

102 generator

103 Generator circuit breaker

104 Balance reactor

105 Inverter module

106 generator bridge

107 Voltage Clamp

108 network bridge

109 Balance reactor

110 Network circuit breaker

111 Inductive device

112 PWM filter

113 transformer

114 MVCN

115 Collector network

200 gate driver

201 Low side circuit

202 High side circuit

203 The top part of the high-side circuit

204 Bottom part of the high side circuit

205 Power supply transformer

206 Additional transformer

207 Additional transformer

208 Power supply circuit

209 Top part of the power supply circuit

210 Bottom part of power supply circuit

211 The logic part of the top part of the high-side circuit

212 The logic part of the bottom part of the high-side circuit

213 Control logic

214 Signal conditioning unit

215 first terminal

216 Control logic

217 Signal conditioning unit

218 Second terminal

219 phase connection components

220 first transistor

221 first diode

222 second transistor

223 second diode

224 Balance reactor

330 The first detection circuit

331 Second detection circuit

332-335 Diodes

336 The first RC filter

337 Second RC filter

338 AND/AND NOT COMPONENTS

339 AND/AND NOT COMPONENTS

440-442 inverter module

550-552 Transistor pairs

553 Balance reactor

554 AC voltage source.

Claims (12)

1. A gate driver (200) for a power converter, the gate driver comprising: low side circuit (201), a high-side circuit (202) coupled to a low-side circuit (201), wherein the high-side circuit (202) comprises a detection circuit (330, 331) adapted to provide an error signal indicative of a fault condition of the low-side circuit (201), Wherein said detection circuit (330, 331) is adapted to provide the error signal in a time span below a predetermined limit. 2. The gate driver (200) according to claim 1, wherein the low-side circuit (201) and the high-side circuit (202) are galvanically separated from each other. 3. The gate driver (200) according to claim 1 or 2, wherein the gate driver (200) further comprises a pulse transformer (205), wherein the pulse transformer (205) is adapted to convert the low-side A circuit (201) is coupled to a high-side circuit (202). 4. The gate driver (200) according to claim 1 or 2, wherein the gate driver (200) further comprises an output terminal (215, 218) adapted such that at the switching element The switching element (220, 222) is coupled to the switching element (220, 222) by providing an error signal at the switching input terminal of (220, 222). 5. The gate driver (200) according to claim 1 or 2, wherein the fault condition is loss of low-side power supply and/or loss of a clock signal of the low-side circuit. 6. The gate driver (200) according to claim 1 or 2, wherein the high side circuit (202) comprises a top part (203) and a bottom part (204). 7. The gate driver (200) according to claim 1 or 2, wherein the high-side circuit (202) comprises a power supply circuit (209) and a logic circuit (211), wherein the high-side power supply circuit ( 209) coupled to the low side power supply circuit. 8. The gate driver (200) according to claim 1 or 2, wherein the detection circuit (330, 331 ) comprises a pair of diodes (332, 333) coupled to each other in such a way that a detection signal is generateable , 334, 335) and RC filters (336, 337). 9. The gate driver (200) according to claim 1 or 2, wherein the logic signal is supplied to an AND and/or NAND element (338, 339) having an output terminal, wherein the AND and/or NAND The element is adapted to provide an error signal at an output terminal. 10. An electronic converter comprising: The gate driver (200) according to any one of claims 1 to 9, A switching element (220, 221) having an input terminal coupled to an output terminal (215, 218) of a gate driver (200). 11. A method of operating a gate driver (200) according to any one of claims 1 to 9, comprising the steps of: detecting an error condition of the low side circuit (201) at the high side circuit (202); generating an error signal when an error condition is detected; and An error signal is provided to a switching element (220, 222). 12. An apparatus for operating a gate driver (200) according to any one of claims 1 to 9, comprising: means for detecting an error condition of the low side circuit (201) at the high side circuit (202); means for generating an error signal when an error condition is detected; and Means for providing an error signal to a switching element (220, 222).