CN104300961A - Variable-gain analog adder - Google Patents
Variable-gain analog adder Download PDFInfo
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- CN104300961A CN104300961A CN201310298979.0A CN201310298979A CN104300961A CN 104300961 A CN104300961 A CN 104300961A CN 201310298979 A CN201310298979 A CN 201310298979A CN 104300961 A CN104300961 A CN 104300961A
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Abstract
The invention discloses a variable-gain analog adder. The variable-gain analog adder comprises a first bias current source, a first MOS (Metal Oxide Semiconductor) transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, an eighth MOS transistor, a ninth MOS transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor and a sixth resistor. The eighth MOS transistor, the ninth MOS transistor, the first resistor, the second resistor, the third resistor, the fourth resistor, the fifth resistor and the sixth resistor are taken as output loads of the analog adder. The turn-on resistance of the eighth MOS transistor and the ninth MOS transistor is changed by regulating control voltages Vb1 and Vb2, so that the output resistance of the whole analog adder is regulated, and is reflected as the gain change of the analog adder at differential output ends (Vop and Von).
Description
Technical field
The present invention relates to analog integrated circuit technical field, relate to a kind of analog adder of variable gain.
Background technology
Along with the development of analog integrated circuit technology, more and more higher requirement is proposed to the area of chip and power consumption, need that the circuits as practical structure realizing analog is simple, area is little and low in energy consumption.Analog adder and variable gain amplifier are two modules conventional in analog, and be that frequent level is linked togather use, independently realize the addition of signal and the change function of gain, the addition of signal and the change of gain after two model calling, can be realized.Because employ two modules, so circuit structure is complicated, the large power consumption of chip area is high.
Summary of the invention
The present invention, in order to solve the deficiencies in the prior art, proposes a kind of analog adder of variable gain, realizes addition and the change in gain function of signal simultaneously, greatly will simplify circuit structure, reduces chip area and power consumption.
Technical solution of the present invention is: a kind of analog adder of variable gain, comprises the first bias current sources, the first MOS transistor, the second MOS transistor, the 3rd MOS transistor, the 4th MOS transistor, the 5th MOS transistor, the 6th MOS transistor, the 7th MOS transistor, the 8th MOS transistor, the 9th MOS transistor, the first resistance, the second resistance, the 3rd resistance, the 4th resistance, the 5th resistance and the 6th resistance.
Wherein first bias current sources one end is connected to voltage source V DD, and the other end is connected to the grid of the drain electrode of the first MOS transistor, the grid of the first MOS transistor, the grid of the second MOS transistor and the 3rd MOS transistor;
The drain electrode of the first MOS transistor is connected to the grid of self, and is connected to the grid of the second MOS transistor and the grid of the 3rd MOS transistor, and the source class of the first MOS transistor is connected to ground;
The drain electrode of the second MOS transistor is connected to the source class of the 4th MOS transistor and the source class of the 5th MOS transistor, the grid of the second MOS transistor is connected to the grid of the grid of the first MOS transistor, the drain electrode of the first MOS transistor and the 3rd MOS transistor, the source class ground connection of the second MOS transistor, the effect of the second MOS transistor is tail current source;
The drain electrode of the 3rd MOS transistor is connected to the source class of the 6th MOS transistor and the source class of the 7th MOS transistor, the grid of the 3rd MOS transistor is connected to the grid of the second MOS transistor, the grid of the first MOS transistor and drain electrode, the source class ground connection of the 3rd MOS transistor, the effect of the 3rd MOS transistor is tail current source;
The drain electrode of the 4th MOS transistor is connected to the inverse output terminal Von of output difference sub-signal, the grid of the 4th MOS transistor is connected to the positive input IP of the first input differential signal, and the source class of the 4th MOS transistor is connected to the source class of the 5th MOS transistor and the leakage level of the second MOS transistor; The drain electrode of the 5th MOS transistor is connected to the forward output end vo p of output difference sub-signal, the grid of the 5th MOS transistor is connected to the reverse input end IN of the first input differential signal, and the source class of the 5th MOS transistor is connected to the source class of the 4th MOS transistor and the leakage level of the second MOS transistor; Described 4th MOS transistor and the 5th MOS transistor form the first input difference to pipe;
The drain electrode of the 6th MOS transistor is connected to the inverse output terminal Von of output difference sub-signal, the grid of the 6th MOS transistor is connected to the positive input QP of the second input differential signal, and the source class of the 6th MOS transistor is connected to the source class of the 7th MOS transistor and the leakage level of the 3rd MOS transistor; The drain electrode of the 7th MOS transistor is connected to the forward output end vo p of output difference sub-signal, the grid of the 7th MOS transistor is connected to the reverse input end QN of the second input differential signal, and the source class of the 7th MOS transistor is connected to the source class of the 6th MOS transistor and the leakage level of the 3rd MOS transistor; Described 6th MOS transistor and the 7th MOS transistor form the second input difference to pipe;
The drain electrode of the 8th MOS transistor is connected to the other end of the 5th resistance relative to Von, and the grid of the 8th MOS transistor meets control voltage Vb2, and the source class of the 8th MOS transistor is connected to the other end of the 6th resistance relative to Vop; 8th MOS transistor plays the effect of switch at this;
The drain electrode of the 9th MOS transistor is connected to the other end of the 3rd resistance relative to Von, and the grid of the 9th MOS transistor meets control voltage Vb1, and the source class of the 9th MOS transistor is connected to the other end of the 4th resistance relative to Vop; 9th MOS transistor plays the effect of switch at this;
One end of first resistance is connected to power vd D, and the other end is connected to the inverse output terminal Von of output difference sub-signal;
One end of second resistance is connected to power vd D, and the other end is connected to the forward output end vo p of output difference sub-signal;
One end of 3rd resistance is connected to the inverse output terminal Von of output difference sub-signal, and the other end is connected to the drain electrode of the 9th MOS transistor;
One end of 4th resistance is connected to the forward output end vo p of output difference sub-signal, and the other end is connected to the source class of the 9th MOS transistor;
One end of 5th resistance is connected to the inverse output terminal Von of output difference sub-signal, and the other end is connected to the drain electrode of the 8th MOS transistor;
One end of 6th resistance is connected to the forward output end vo p of output difference sub-signal, and the other end is connected to the source class of the 8th MOS transistor;
Described 8th MOS transistor, the 9th MOS transistor, the first resistance, the second resistance, the 3rd resistance, the 4th resistance, the 5th resistance and the 6th resistance are as the output loading of analog adder, by regulable control voltage Vb1 and Vb2, change the conducting resistance of the 8th MOS transistor and the 9th MOS transistor, thus regulating the output impedance of whole analog adder, the gain being finally reflected as analog adder at difference output end (Vop and Von) changes;
The present invention is compared with traditional prior art, and the advantage had and effect are: enormously simplify circuit structure, reduces chip area and power consumption.
Accompanying drawing explanation
Fig. 1 is the analog adder circuit theory diagrams of variable gain of the present invention;
Embodiment
Below in conjunction with accompanying drawing, the present invention is elaborated.
See Fig. 1, a kind of analog adder of variable gain comprises the first bias current sources Idc1, the first MOS transistor M1, the second MOS transistor M2, the 3rd MOS transistor M3, the 4th MOS transistor M4, the 5th MOS transistor M5, the 6th MOS transistor M6, the 7th MOS transistor M7, the 8th MOS transistor M8, the 9th MOS transistor M9, the first resistance R1, the second resistance R2, the 3rd resistance R3, the 4th resistance R4, the 5th resistance R5 and the 6th resistance R6.
Wherein first bias current sources Idc1 one end is connected to voltage source V DD, and the other end is connected to the grid of the drain electrode of the first MOS transistor M1, the grid of the first MOS transistor M1, the grid of the second MOS transistor M2 and the 3rd MOS transistor M3;
The drain electrode of the first MOS transistor M1 is connected to the grid of self, and is connected to the grid of the second MOS transistor M2 and the grid of the 3rd MOS transistor M3, and the source class of the first MOS transistor M1 is connected to ground;
The drain electrode of the second MOS transistor M2 is connected to the source class of the 4th MOS transistor M4 and the source class of the 5th MOS transistor M5, the grid of the second MOS transistor M2 is connected to the grid of the grid of the first MOS transistor M1, the drain electrode of the first MOS transistor M1 and the 3rd MOS transistor M3, the source class ground connection of the second MOS transistor M2, the effect of the second MOS transistor M2 is tail current source;
The drain electrode of the 3rd MOS transistor M3 is connected to the source class of the 6th MOS transistor M6 and the source class of the 7th MOS transistor M7, the grid of the 3rd MOS transistor M3 is connected to the grid of the second MOS transistor M2, the grid of the first MOS transistor M1 and drain electrode, the source class ground connection of the 3rd MOS transistor M3, the effect of the 3rd MOS transistor M3 is tail current source;
The drain electrode of the 4th MOS transistor M4 is connected to the inverse output terminal Von of output difference sub-signal, the grid of the 4th MOS transistor M4 is connected to the positive input IP of the first input differential signal, and the source class of the 4th MOS transistor M4 is connected to the source class of the 5th MOS transistor M5 and the leakage level of the second MOS transistor M2; The drain electrode of the 5th MOS transistor M5 is connected to the forward output end vo p of output difference sub-signal, the grid of the 5th MOS transistor M5 is connected to the reverse input end IN of the first input differential signal, and the source class of the 5th MOS transistor M5 is connected to the source class of the 4th MOS transistor M4 and the leakage level of the second MOS transistor M2; Described 4th MOS transistor M4 and the 5th MOS transistor M5 forms the first input difference to pipe;
The drain electrode of the 6th MOS transistor M6 is connected to the inverse output terminal Von of output difference sub-signal, the grid of the 6th MOS transistor M6 is connected to the positive input QP of the second input differential signal, and the source class of the 6th MOS transistor M6 is connected to the source class of the 7th MOS transistor M7 and the leakage level of the 3rd MOS transistor M3; The drain electrode of the 7th MOS transistor M7 is connected to the forward output end vo p of output difference sub-signal, the grid of the 7th MOS transistor M7 is connected to the reverse input end QN of the second input differential signal, and the source class of the 7th MOS transistor M7 is connected to the source class of the 6th MOS transistor M6 and the leakage level of the 3rd MOS transistor M3; Described 6th MOS transistor M6 and the 7th MOS transistor M7 forms the second input difference to pipe;
The drain electrode of the 8th MOS transistor M8 is connected to the other end of the 5th resistance R5 relative to Von, and the grid of the 8th MOS transistor M8 meets control voltage Vb2, and the source class of the 8th MOS transistor M8 is connected to the other end of the 6th resistance R6 relative to Vop; 8th MOS transistor M8 plays the effect of switch at this;
The drain electrode of the 9th MOS transistor M9 is connected to the other end of the 3rd resistance R3 relative to Von, and the grid of the 9th MOS transistor M9 meets control voltage Vb1, and the source class of the 9th MOS transistor M9 is connected to the other end of the 4th resistance R4 relative to Vop; 9th MOS transistor M9 plays the effect of switch at this;
One end of first resistance R1 is connected to power vd D, and the other end is connected to the inverse output terminal Von of output difference sub-signal;
One end of second resistance R2 is connected to power vd D, and the other end is connected to the forward output end vo p of output difference sub-signal;
One end of 3rd resistance R3 is connected to the inverse output terminal Von of output difference sub-signal, and the other end is connected to the drain electrode of the 9th MOS transistor M9;
One end of 4th resistance R4 is connected to the forward output end vo p of output difference sub-signal, and the other end is connected to the source class of the 9th MOS transistor M9;
One end of 5th resistance R5 is connected to the inverse output terminal Von of output difference sub-signal, and the other end is connected to the drain electrode of the 8th MOS transistor M8;
One end of 6th resistance R6 is connected to the forward output end vo p of output difference sub-signal, and the other end is connected to the source class of the 8th MOS transistor M8;
Described 8th MOS transistor M8, the 9th MOS transistor M9, the first resistance R1, the second resistance R2, the 3rd resistance R3, the 4th resistance R4, the 5th resistance R5 and the 6th resistance R6 are as the output loading of analog adder, by regulable control voltage Vb1 and Vb2, change the conducting resistance of the 8th MOS transistor M8 and the 9th MOS transistor M9, thus regulating the output impedance of whole analog adder, the gain being finally reflected as analog adder at difference output end (Vop and Von) changes;
The input of the first input differential signal is IP and IN, the input of the second input differential signal is QP and QN, two differential signals exist respectively, 4th MOS transistor M4 and the 5th MOS transistor M5 forms the first input difference to pipe, 6th MOS transistor M6 and the 7th MOS transistor M7 forms the second input difference and is converted to difference current on pipe, two-pass DINSAR electric current synthesizes a road difference current and is converted to differential voltage again simultaneously on the first resistance R1 and the second resistance R2, is exported by difference output end Vop and Von;
By regulable control voltage Vb1 and Vb2, the conducting resistance of the 8th MOS transistor M8 and the 9th MOS transistor M9 can be changed; When the 8th MOS transistor M8 and the 9th MOS transistor M9 conducting, increase the conducting resistance that control voltage Vb1 and Vb2 can increase the 8th MOS transistor M8 and the 9th MOS transistor M9, and then increase the output impedance of whole analog adder, improve the gain of analog adder; When the 8th MOS transistor M8 and the 9th MOS transistor M9 conducting, reduce the conducting resistance that control voltage Vb1 and Vb2 can reduce the 8th MOS transistor M8 and the 9th MOS transistor M9, and then reduce the output impedance of whole analog adder, reduce the gain of analog adder;
And when regulable control voltage Vb1 and Vb2 makes the output impedance of analog adder change, the DC point of whole analog adder circuit is stablized constant, and input and output common-mode point is fixed, and enormously simplify the design of front stage circuits and late-class circuit.
So by regulable control voltage Vb1 and Vb2, cooperatively interact, the addition function of the first input differential signal and the first input differential signal can be realized, change the gain of analog adder simultaneously.
More than show and describe general principle of the present invention and principal character and advantage of the present invention.The technical staff of the industry should understand; the present invention is not restricted to the described embodiments; what describe in above-described embodiment and specification just illustrates principle of the present invention; without departing from the spirit and scope of the present invention; the present invention also has various changes and modifications, and these changes and improvements all fall in the claimed scope of the invention.Application claims protection range is defined by appending claims and equivalent thereof.
Claims (1)
1. an analog adder for variable gain, is characterized in that: comprise the first bias current sources, the first MOS transistor, the second MOS transistor, the 3rd MOS transistor, the 4th MOS transistor, the 5th MOS transistor, the 6th MOS transistor, the 7th MOS transistor, the 8th MOS transistor, the 9th MOS transistor, the first resistance, the second resistance, the 3rd resistance, the 4th resistance, the 5th resistance and the 6th resistance;
Described first bias current sources one end is connected to voltage source V DD, and the other end is connected to the grid of the drain electrode of the first MOS transistor, the grid of the first MOS transistor, the grid of the second MOS transistor and the 3rd MOS transistor respectively;
The drain electrode of described first MOS transistor is connected to the grid of the grid of self, the grid of the second MOS transistor and the 3rd MOS transistor respectively, and the source class of the first MOS transistor is connected to ground;
The drain electrode of described second MOS transistor is connected to the source class of the 4th MOS transistor and the source class of the 5th MOS transistor, the grid of the second MOS transistor is connected to the grid of the 3rd MOS transistor, the source class ground connection of the second MOS transistor, the effect of the second MOS transistor is tail current source;
The drain electrode of described 3rd MOS transistor is connected to the source class of the 6th MOS transistor and the source class of the 7th MOS transistor, the source class ground connection of the 3rd MOS transistor, and the effect of the 3rd MOS transistor is tail current source;
The drain electrode of described 4th MOS transistor is connected to the inverse output terminal Von of output difference sub-signal, the grid of the 4th MOS transistor is connected to the positive input IP of the first input differential signal, and the source class of the 4th MOS transistor is also connected to the source class of the 5th MOS transistor;
The drain electrode of described 5th MOS transistor is connected to the forward output end vo p of output difference sub-signal, and the grid of the 5th MOS transistor is connected to the reverse input end IN of the first input differential signal; Described 4th MOS transistor and the 5th MOS transistor form the first input difference to pipe;
The drain electrode of described 6th MOS transistor is connected to the inverse output terminal Von of output difference sub-signal, and the grid of the 6th MOS transistor is connected to the positive input QP of the second input differential signal, and the source class of the 6th MOS transistor is connected to the source class of the 7th MOS transistor;
The drain electrode of described 7th MOS transistor is connected to the forward output end vo p of output difference sub-signal, and the grid of the 7th MOS transistor is connected to the reverse input end QN of the second input differential signal; Described 6th MOS transistor and the 7th MOS transistor form the second input difference to pipe;
The drain electrode of described 8th MOS transistor is connected to the other end of the 5th resistance relative to Von, and the grid of the 8th MOS transistor meets control voltage Vb2, and the source class of the 8th MOS transistor is connected to the other end of the 6th resistance relative to Vop; 8th MOS transistor plays the effect of switch at this;
The drain electrode of described 9th MOS transistor is connected to the other end of the 3rd resistance relative to Von, and the grid of the 9th MOS transistor meets control voltage Vb1, and the source class of the 9th MOS transistor is connected to the other end of the 4th resistance relative to Vop; 9th MOS transistor plays the effect of switch at this;
One end of first resistance is connected to power vd D, and the other end is connected to the inverse output terminal Von of output difference sub-signal;
One end of second resistance is connected to power vd D, and the other end is connected to the forward output end vo p of output difference sub-signal;
One end of 3rd resistance is connected to the inverse output terminal Von of output difference sub-signal, and the other end is connected to the drain electrode of the 9th MOS transistor;
One end of 4th resistance is connected to the forward output end vo p of output difference sub-signal, and the other end is connected to the source class of the 9th MOS transistor;
One end of 5th resistance is connected to the inverse output terminal Von of output difference sub-signal, and the other end is connected to the drain electrode of the 8th MOS transistor;
One end of 6th resistance is connected to the forward output end vo p of output difference sub-signal, and the other end is connected to the source class of the 8th MOS transistor.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310298979.0A CN104300961A (en) | 2013-07-16 | 2013-07-16 | Variable-gain analog adder |
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| CN201310298979.0A CN104300961A (en) | 2013-07-16 | 2013-07-16 | Variable-gain analog adder |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106788397A (en) * | 2017-02-16 | 2017-05-31 | 苏州英诺迅科技股份有限公司 | A kind of signal adds and subtracts circuit |
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| CN1551489A (en) * | 2003-03-19 | 2004-12-01 | 三洋电机株式会社 | Variable impedance circuit, amplifier, multiplier, high-frequency circuit using same |
| CN1905404A (en) * | 2005-07-25 | 2007-01-31 | 夏普株式会社 | Low noise block converter |
| US7978785B2 (en) * | 2006-08-02 | 2011-07-12 | Edgewater Computer Systems, Inc. | Quadrature frequency doubler with adjustable phase offset |
| CN103368514A (en) * | 2012-03-29 | 2013-10-23 | 北京普源精电科技有限公司 | Variable gain amplifier-equipped measuring apparatus |
| CN203423670U (en) * | 2013-07-16 | 2014-02-05 | 陕西北斗恒通信息科技有限公司 | Variable-gain analog adder |
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2013
- 2013-07-16 CN CN201310298979.0A patent/CN104300961A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1551489A (en) * | 2003-03-19 | 2004-12-01 | 三洋电机株式会社 | Variable impedance circuit, amplifier, multiplier, high-frequency circuit using same |
| CN1905404A (en) * | 2005-07-25 | 2007-01-31 | 夏普株式会社 | Low noise block converter |
| US7978785B2 (en) * | 2006-08-02 | 2011-07-12 | Edgewater Computer Systems, Inc. | Quadrature frequency doubler with adjustable phase offset |
| CN103368514A (en) * | 2012-03-29 | 2013-10-23 | 北京普源精电科技有限公司 | Variable gain amplifier-equipped measuring apparatus |
| CN203423670U (en) * | 2013-07-16 | 2014-02-05 | 陕西北斗恒通信息科技有限公司 | Variable-gain analog adder |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106788397A (en) * | 2017-02-16 | 2017-05-31 | 苏州英诺迅科技股份有限公司 | A kind of signal adds and subtracts circuit |
| CN106788397B (en) * | 2017-02-16 | 2023-09-19 | 苏州英诺迅科技股份有限公司 | Signal adding and subtracting circuit |
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Application publication date: 20150121 |