CN101902215B - Four-input terminal comparator - Google Patents

Abstract

The invention discloses a comparator with four input terminals, which has four input terminals and only needs one reference source when it is applied in a scheme similar to multi-section batteries, which saves chip area and cost and improves circuit performance. The technical solution is: the comparator has a first MOS transistor, a second MOS transistor, a third MOS transistor and a fourth MOS transistor, wherein the gates of the first MOS transistor and the second MOS transistor are connected to the first input voltage and the second MOS transistor respectively. The input voltage, the sources of the first MOS transistor and the second MOS transistor are respectively connected to the third input voltage and the fourth input voltage. The third MOS transistor and the fourth MOS transistor form a current mirror structure, the third MOS transistor forms a diode connection mode, the drain of the third MOS transistor is connected to the drain of the first MOS transistor, and the drain of the fourth MOS transistor is connected to the first MOS transistor. The drain of the two MOS transistors is the output of the comparator.

Description

Four Input Comparator

technical field

The present invention relates to a comparator, and more particularly to a comparator having four inputs and suitable for use in a monolithic integrated circuit chip.

Background technique

In the field of analog integrated circuits, comparators are widely used. The comparator compares two voltages and outputs high and low level signals for subsequent circuit processing.

The traditional comparator is shown in Figure 1. The comparator is composed of the first stage and the second stage. The first stage is composed of the input pair of transistors M1 and M2, the load pair of transistors M3 and M4, and the current source _Ib1 . The second stage It is composed of MOS transistor M5 and current source _Ib . The comparison voltages are respectively connected to the gates of M1 and M2. As seen from FIG. 1, the first input voltage V _in is input to the gate of M1, and the second input voltage V _ip is input to the gate of M2.

The input comparison voltages V _in and V _ip of a traditional comparator are both relative to the same potential (V _gnd ), and this comparator compares two voltage differences between V _in -V _gnd and V _ig -V _gnd .

When V _in -V _gnd =V _ip -V _gnd , that is, when V _in =V _ip , the output voltage V _out of the comparator is reversed. If the power supply potential V _DD and the ground potential V _gnd of the comparator are not considered, the input voltage of the traditional comparator has two V _in and V _ip , so the traditional voltage comparator can be called a dual-input voltage comparator, and can also be expressed as as shown in picture 2.

In practical application, one of the input terminals of the comparator shown in FIG. 2 is connected to the reference voltage V _ref , and the other terminal is connected to the voltage to be detected.

Since the two input terminals of the traditional comparator are relative to the same potential, when the relative potential of the voltage to be detected changes, the corresponding reference voltage V _ref also needs to be changed.

For example, in the multi-cell lithium-ion battery application scheme, it is necessary to detect the voltage of multiple cells. The implementation method of using a traditional comparator is to provide a reference voltage between each cell, and then divide the voltage of the multiple cells with the corresponding compared with the reference voltage. For example, as shown in FIG. 3 , since there are four batteries, four reference voltages are required. In Figure 3, VC1~VC4 represent the positive input terminals of the four batteries, Vd1~Vd4 respectively represent the divided voltages of the four batteries, V _ref1 ~V _ref4 represent the reference voltage corresponding to each battery, and satisfy the relationship:

V _ref4 -V _gnd =V _ref3 -V _c4 =V _ref2 -V _c3 =V _ref1 -V _c2

This implementation has certain limitations:

(1) Each battery needs a reference voltage. As the number of batteries increases, the reference source circuit also increases, and the area and cost of the corresponding chip will increase accordingly.

(2) The mismatch of the reference source circuit (Mismatch) between each battery will introduce additional errors, which will affect the overall accuracy.

Contents of the invention

The purpose of the present invention is to solve the above problems, providing a four-input comparator with four input terminals, which only needs one reference source when applied in a similar multi-cell battery solution, which saves chip area and cost, and improves circuit performance.

The technical solution of the present invention is: the present invention discloses a four-input comparator, comprising:

The first MOS transistor and the second MOS transistor, wherein the gate of the first MOS transistor is connected to the first input voltage, the gate of the second MOS transistor is connected to the second input voltage, and the source of the first MOS transistor is connected to the third input voltage, The source of the second MOS transistor is connected to the fourth input voltage;

The third MOS transistor and the fourth MOS transistor, wherein the gate and drain of the third MOS transistor are short-circuited, the source of the third MOS transistor is connected to the power supply voltage, and the drain of the third MOS transistor is connected to the drain of the first MOS transistor , the gate of the fourth MOS transistor is connected to the gate of the third MOS transistor, the source of the fourth MOS transistor is connected to the power supply voltage, the drain of the fourth MOS transistor is connected to the drain of the second MOS transistor and is a four-input comparison output of the device.

According to an embodiment of the four-input comparator of the present invention, the size of the first MOS transistor and the second MOS transistor are the same, and the size of the third MOS transistor and the fourth MOS transistor are the same.

According to an embodiment of the four-input comparator of the present invention, the four-input comparator further includes:

The gate of the fifth MOS transistor is connected to the drain of the fourth MOS transistor, the source is connected to the power supply voltage, the drain is connected to a current source which is the output of the four-input comparator, and the other end of the current source is grounded.

According to an embodiment of the four-input comparator of the present invention, the source of the first MOS transistor is connected to the first resistor, and the source of the second MOS transistor is connected to the second resistor.

According to an embodiment of the four-input comparator of the present invention, the source of the first MOS transistor is grounded.

The present invention also discloses a four-input comparator, comprising:

The first MOS transistor and the second MOS transistor, wherein the gate of the first MOS transistor is connected to the first input voltage, the gate of the second MOS transistor is connected to the second input voltage, and the source of the first MOS transistor is connected to the third input voltage, The source of the second MOS transistor is connected to the fourth input voltage;

The third MOS transistor and the fourth MOS transistor, wherein the drain and gate of the third MOS transistor are short-circuited, the source of the third MOS transistor is grounded, the drain of the third MOS transistor is connected to the drain of the first MOS transistor, and the drain of the third MOS transistor is connected to the drain of the first MOS transistor. The gates of the four MOS transistors are connected to the gate of the third MOS transistor, the source of the fourth MOS transistor is grounded, and the drain of the fourth MOS transistor is connected to the drain of the second MOS transistor and is the output of the four-input comparator.

According to an embodiment of the four-input comparator of the present invention, the size of the first MOS transistor and the second MOS transistor are the same, and the size of the third MOS transistor and the fourth MOS transistor are the same.

According to an embodiment of the four-input comparator of the present invention, the four-input comparator further includes:

The gate of the fifth MOS transistor is connected to the drain of the fourth MOS transistor, the source is grounded, the drain is connected to a current source which is the output of the four-input comparator, and the other end of the current source is connected to the power supply voltage.

According to an embodiment of the four-input comparator of the present invention, the source of the first MOS transistor is connected to the first resistor, and the source of the second MOS transistor is connected to the second resistor.

According to an embodiment of the four-input comparator of the present invention, the gate of the second MOS transistor is connected to a reference voltage.

The present invention also discloses a four-input comparator, comprising:

The first triode and the second triode, wherein the base of the first triode is connected to the first input voltage, the base of the second triode is connected to the second input voltage, and the emitter of the first triode is connected to the third input voltage, the emitter of the second transistor is connected to the fourth input voltage;

The third triode and the fourth triode, wherein the base and collector of the third triode are short-circuited, the emitter of the third triode is connected to the power supply voltage, and the collector of the third triode is connected to the first The collector of the triode, the base of the fourth triode are connected to the base of the third triode, the emitter of the fourth triode is connected to the power supply voltage, the collector of the fourth triode is connected to the second three The collector of the pole tube is connected and is the output of the four-input comparator.

According to an embodiment of the four-input comparator of the present invention, the first transistor and the second transistor have the same size, and the third transistor and the fourth transistor have the same size.

According to an embodiment of the four-input comparator of the present invention, the four-input comparator further includes:

The base of the fifth transistor is connected to the collector of the fourth transistor, the emitter is connected to the power supply voltage, the collector is connected to a current source which is the output of the four-input comparator, and the other end of the current source is grounded.

According to an embodiment of the four-input comparator of the present invention, the emitter of the first transistor is connected to the first resistor, and the emitter of the second transistor is connected to the second resistor.

The present invention additionally discloses a four-input comparator, comprising:

The first triode and the second triode, wherein the base of the first triode is connected to the first input voltage, the base of the second triode is connected to the second input voltage, and the emitter of the first triode is connected to the third input voltage, the emitter of the second transistor is connected to the fourth input voltage;

The third triode and the fourth triode, wherein the collector and base of the third triode are short-circuited, the collector of the third triode is connected to the collector of the first triode, and the third triode The emitter of the fourth triode is grounded, the base of the fourth triode is connected to the base of the third triode, the emitter of the fourth triode is grounded, the collector of the fourth triode is connected to the collector of the second triode The electrodes are connected and are the output of a four-input comparator.

According to an embodiment of the four-input comparator of the present invention, the first transistor and the second transistor have the same size, and the third transistor and the fourth transistor have the same size.

According to an embodiment of the four-input comparator of the present invention, the four-input comparator further includes:

The base of the fifth transistor is connected to the collector of the fourth transistor, the emitter is grounded, the collector is connected to a current source and is the output of the four-input comparator, and the other end of the current source is connected to the power supply voltage.

According to an embodiment of the four-input comparator of the present invention, the emitter of the first transistor is connected to the first resistor, and the emitter of the second transistor is connected to the second resistor.

Compared with the prior art, the present invention has the following beneficial effects: the comparator of the present invention has a first MOS transistor, a second MOS transistor, a third MOS transistor and a fourth MOS transistor, wherein the gates of the first MOS transistor and the second MOS transistor The poles are respectively connected to the first input voltage and the second input voltage, and the sources of the first MOS transistor and the second MOS transistor are respectively connected to the third input voltage and the fourth input voltage. The third MOS transistor and the fourth MOS transistor form a current mirror structure, the third MOS transistor forms a diode connection mode, the drain of the third MOS transistor is connected to the drain of the first MOS transistor, and the drain of the fourth MOS transistor is connected to the first MOS transistor. The drain of the two MOS transistors is the output of the comparator. Compared with the prior art, in the above multi-cell battery solution, the present invention can directly compare the battery voltage of each string with the same reference voltage under low voltage, so only one reference voltage source circuit is needed, saving multiple reference sources , thereby saving the cost of the chip and improving the performance of the circuit.

Description of drawings

Figure 1 is a schematic diagram of the internal circuit of a conventional comparator.

FIG. 2 is a schematic diagram of a conventional two-input comparator.

FIG. 3 is a schematic diagram of a multi-cell battery voltage detection method implemented by using a traditional comparator.

FIG. 4 is a circuit diagram of a first embodiment of the four-input comparator of the present invention.

FIG. 5 is a circuit diagram of a second embodiment of the four-input comparator of the present invention.

FIG. 6 is a schematic diagram of a four-input comparator of the present invention.

FIG. 7 is a circuit diagram of a third embodiment of the four-input comparator of the present invention.

Fig. 8 is a schematic diagram of a multi-cell battery voltage detection method implemented by the present invention.

FIG. 9 is a schematic diagram of each level change during the inversion process of the comparator in FIG. 7 .

FIG. 10 is a circuit diagram of a fourth embodiment of the four-input comparator of the present invention.

FIG. 11 is a circuit diagram of a fifth embodiment of the four-input comparator of the present invention.

FIG. 12 is a circuit diagram of a sixth embodiment of the four-input comparator of the present invention.

FIG. 13 is a circuit diagram of a seventh embodiment of the four-input comparator of the present invention.

FIG. 14 is a circuit diagram of an eighth embodiment of the four-input comparator of the present invention.

FIG. 15 is a circuit diagram of a ninth embodiment of the four-input comparator of the present invention.

Fig. 16 is a circuit diagram of a tenth embodiment of the four-input comparator of the present invention.

Detailed ways

The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

A first embodiment of a four-input comparator

FIG. 4 shows the circuit of a first embodiment of the four-input comparator of the present invention. Referring to FIG. 4 , the four-input comparator in this embodiment includes: a first MOS transistor M1 , a second MOS transistor M2 , a third MOS transistor M3 and a fourth MOS transistor M4 .

The gate of the first MOS transistor M1 is connected to the first input voltage V _in , the gate of the second MOS transistor M2 is connected to the second input voltage V _ip , the source of the first MOS transistor M1 is connected to the third input voltage V1 , and the second MOS transistor M2 The source of the transistor M2 is connected to the fourth input voltage V2.

The connection mode of the third MOS transistor M3 and the fourth MOS transistor M4 constitutes a current mirror. Specifically, the gate and drain of the third MOS transistor M3 are short-circuited (marked in FIG. 4 as using N1 to connect the gate and drain of M3 to form a diode connection), and the source of the third MOS transistor M3 The pole is connected to the power supply voltage VDD, and the drain of the third MOS transistor M3 is connected to the drain of the first MOS transistor M1. The gate of the fourth MOS transistor M4 is connected to the gate of the third MOS transistor M3, the source of the fourth MOS transistor M4 is connected to the power supply voltage VDD, the drain of the fourth MOS transistor M4 is connected to the drain of the second MOS transistor M2, Moreover, the output of the drain of the fourth MOS transistor M4 is the output of the comparator (marked as the output of the comparator derived from N2 in FIG. 4 ).

For the four-input comparator, the above circuit can already constitute a basic four-input comparator. In order to better realize its effect, a fifth MOS transistor M5 and a current source _Ib can also be added on the basis of the above circuit, and the gate of the fifth MOS transistor M5 is connected to the drain of the fourth MOS transistor M4 (in FIG. 4 is connected to N2), and the source of the fifth MOS transistor M5 is connected to the power supply voltage VDD. The drain of the fifth MOS transistor M5 is connected to the current source I _b , and the drain is drawn out as the output of the comparator (the output of the comparator is marked as V _out in FIG. 4 ), and the other end of the current source I _b is grounded.

In a preferred implementation manner, the first MOS transistor M1 and the second MOS transistor M2 have the same size, and the third MOS transistor M3 and the fourth MOS transistor M4 have the same size.

The form of expression of this four-input terminal comparator is shown in Figure 6, and it has input voltage V1 and V2 besides input voltage V _in and V _ip , and this is the two input that the present invention increases compared to traditional comparator end. This four-input comparator compares two voltage differences between V _in -V1 and V _ip -V2. When V _in -V1=V _ip -V2, the output voltage V _out of the comparator is reversed.

Second embodiment of the four-input comparator

FIG. 5 shows the circuit of a second embodiment of the four-input comparator of the present invention. Referring to FIG. 5 , the four-input comparator in this embodiment includes: a first MOS transistor M1 , a second MOS transistor M2 , a third MOS transistor M3 , a fourth MOS transistor M4 and two resistors R1 and R2 .

The gate of the first MOS transistor M1 is connected to the first input voltage V _in , the gate of the second MOS transistor M2 is connected to the second input voltage V _ip , the source of the first MOS transistor M1 is connected to the third input voltage V1 through the resistor R1, The source of the second MOS transistor M2 is connected to the fourth input voltage V2 through the resistor R2.

The connection mode of the third MOS transistor M3 and the fourth MOS transistor M4 constitutes a current mirror. Specifically, the gate and drain of the third MOS transistor M3 are short-circuited (marked in FIG. 5 as using N1 to connect the gate and drain of M3 to form a diode connection), and the source of the third MOS transistor M3 The pole is connected to the power supply voltage VDD, and the drain of the third MOS transistor M3 is connected to the drain of the first MOS transistor M1. The gate of the fourth MOS transistor M4 is connected to the gate of the third MOS transistor M3, the source of the fourth MOS transistor M4 is connected to the power supply voltage VDD, the drain of the fourth MOS transistor M4 is connected to the drain of the second MOS transistor M2, Moreover, the output of the drain of the fourth MOS transistor M4 is the output of the comparator (marked as the output of the comparator derived from N2 in FIG. 5 ).

For the four-input comparator, the above circuit can already constitute a basic four-input comparator. In order to better realize its effect, a fifth MOS transistor M5 and a current source _Ib can also be added on the basis of the above circuit, and the gate of the fifth MOS transistor M5 is connected to the drain of the fourth MOS transistor M4 (in FIG. 5 is connected to N2), and the source of the fifth MOS transistor M5 is connected to the power supply voltage VDD. The drain of the fifth MOS transistor M5 is connected to the current source I _b , and the drain is drawn out as the output of the comparator (the output of the comparator is marked as V _out in FIG. 5 ), and the other end of the current source I _b is grounded.

In a preferred implementation manner, the first MOS transistor M1 and the second MOS transistor M2 have the same size, and the third MOS transistor M3 and the fourth MOS transistor M4 have the same size.

In a preferred embodiment, the resistance values of the resistors R1 and R2 are the same.

The form of expression of this four-input terminal comparator is shown in Figure 6, and it has input voltage V1 and V2 besides input voltage V _in and V _ip , and this is the two input that the present invention increases compared to traditional comparator end. This four-input comparator compares two voltage differences between V _in -V1 and V _ip -V2. When V _in -V1=V _ip -V2, the output voltage V _out of the comparator is reversed.

A third embodiment of a four-input comparator

FIG. 7 shows the circuit of the third embodiment of the four-input comparator of the present invention. Referring to FIG. 7 , the four-input comparator in this embodiment includes: a first MOS transistor M1 , a second MOS transistor M2 , a third MOS transistor M3 and a fourth MOS transistor M4 .

The gate of the first MOS transistor M1 is connected to the first input voltage V _in , the gate of the second MOS transistor M2 is connected to the second input voltage V _ip , the source of the first MOS transistor M1 is grounded (V _gnd ), and the second MOS transistor M2 The source of M2 is connected to the fourth input voltage V2.

The connection mode of the third MOS transistor M3 and the fourth MOS transistor M4 constitutes a current mirror. Specifically, the gate and drain of the third MOS transistor M3 are short-circuited (marked in FIG. 7 as using N1 to connect the gate and drain of M3 to form a diode connection), and the source of the third MOS transistor M3 The pole is connected to the power supply voltage VDD, and the drain of the third MOS transistor M3 is connected to the drain of the first MOS transistor M1. The gate of the fourth MOS transistor M4 is connected to the gate of the third MOS transistor M3, the source of the fourth MOS transistor M4 is connected to the power supply voltage VDD, the drain of the fourth MOS transistor M4 is connected to the drain of the second MOS transistor M2, Moreover, the output of the drain of the fourth MOS transistor M4 is the output of the comparator (marked as the output of the comparator derived from N2 in FIG. 7 ).

For the four-input comparator, the above circuit can already constitute a basic four-input comparator. In order to better realize its effect, a fifth MOS transistor M5 and a current source _Ib can also be added on the basis of the above circuit, and the gate of the fifth MOS transistor M5 is connected to the drain of the fourth MOS transistor M4 (in FIG. 7 shows that it is connected to N2), and the source of the fifth MOS transistor M5 is connected to the power supply voltage VDD. The drain of the fifth MOS transistor M5 is connected to the current source I _b , and the drain is drawn out as the output of the comparator (the output of the comparator is marked as V _out in FIG. 7 ), and the other end of the current source I _b is grounded.

In a preferred implementation manner, the first MOS transistor M1 and the second MOS transistor M2 have the same size, and the third MOS transistor M3 and the fourth MOS transistor M4 have the same size.

Compared with the first embodiment in FIG. 4 , the only difference of this embodiment is that the source of the first MOS transistor M1 is grounded instead of the third input voltage V1 as shown in FIG. 4 . In practical applications, the gate of the first MOS transistor M1 may be connected to the reference voltage V _ref .

Therefore, the equation of V _in -V1=V _ip -V2 in the first embodiment can be simplified as V _ref =V _ip -V2, so as long as a stable V2 voltage is provided, the high voltage V _ip and the low voltage V _ref for direct comparison, as shown in Figure 7.

In the circuit shown in Figure 7, when V _ip -V ₂ >V _ref -V _gnd , the current flowing through the first MOS transistor M1 is smaller than the current flowing through the second MOS transistor M2, and the fourth MOS transistor M4 mirrors The current of the third MOS transistor M3, so the current of the fourth MOS transistor M4 is smaller than the current of the second MOS transistor M2, the voltage of the point N2 is pulled down, the fifth MOS transistor M5 is strongly turned on, and V _out outputs a high level VDD.

When V _ip -V ₂ =V _ref -V _gnd , the current flowing through the first MOS transistor M1 is equal to the current flowing through the second MOS transistor M2, and the fourth MOS transistor M4 mirrors the current of the third MOS transistor M3, so the first MOS transistor M3 The current of the fourth MOS transistor M4 is equal to the current of the second MOS transistor M2, the voltage at point N2 is in an intermediate state, the current of the fifth MOS transistor M5 is equal to I _b , and V _out starts to change from a high level VDD to a low level V _gnd .

When V _ip -V ₂ <V _ref -V _gnd , the current flowing through the first MOS transistor M1 is greater than the current flowing through the second MOS transistor M2, and the fourth MOS transistor M4 mirrors the current of the third MOS transistor M3, so the first The current of the fourth MOS transistor M4 is greater than the current of the second MOS transistor M2, the voltage of the point N2 is pulled up to VDD, the fifth MOS transistor M5 is turned off, and V _out outputs a low level V _gnd .

The changes of each level during the inversion process of the comparator are shown in Fig. 9 .

A further extension of this embodiment can realize the detection of the voltage of multiple batteries. In Figure 8, VC1~VC4 represent the positive input terminals of the four batteries, Vd1~Vd4 respectively represent the divided voltages of the four batteries, V _ref represents the reference voltage, and the comparator flips when the following relationship is satisfied:

V _ref -V _gnd =V _d4 -V _gnd =V _d3 -V _c4 =V _d2 -V _c3 =V _d1 -V _c2

Compared with the implementation method of the traditional comparator, the present invention can directly compare the battery voltage of each string with the same reference voltage under low voltage, so only one reference voltage source circuit is needed, saving multiple reference sources, thereby saving chips cost and improves circuit performance.

A fourth embodiment of a four-input comparator

FIG. 10 shows the circuit of the fourth embodiment of the four-input comparator of the present invention. Referring to FIG. 10 , the four-input comparator in this embodiment includes: a first MOS transistor M1 , a second MOS transistor M2 , a third MOS transistor M3 , a fourth MOS transistor M4 , and resistors R1 and R2 .

The gate of the first MOS transistor M1 is connected to the first input voltage V _in (in practical applications, the gate of the first MOS transistor M1 can be connected to the reference voltage V _ref ), and the gate of the second MOS transistor M2 is connected to the second input voltage V _ip , the source of the first MOS transistor M1 is grounded (V _gnd ) through the resistor R1, and the source of the second MOS transistor M2 is connected to the fourth input voltage V2 through the resistor R2.

The connection mode of the third MOS transistor M3 and the fourth MOS transistor M4 constitutes a current mirror. Specifically, the gate and drain of the third MOS transistor M3 are short-circuited (marked in FIG. 10 as connecting the gate and drain of M3 with N1 to form a diode connection), and the source of the third MOS transistor M3 The pole is connected to the power supply voltage VDD, and the drain of the third MOS transistor M3 is connected to the drain of the first MOS transistor M1. The gate of the fourth MOS transistor M4 is connected to the gate of the third MOS transistor M3, the source of the fourth MOS transistor M4 is connected to the power supply voltage VDD, the drain of the fourth MOS transistor M4 is connected to the drain of the second MOS transistor M2, Moreover, the output of the drain of the fourth MOS transistor M4 is the output of the comparator (marked as the output of the comparator derived from N2 in FIG. 10 ).

For the four-input comparator, the above circuit can already constitute a basic four-input comparator. In order to better realize its effect, a fifth MOS transistor M5 and a current source _Ib can also be added on the basis of the above circuit, and the gate of the fifth MOS transistor M5 is connected to the drain of the fourth MOS transistor M4 (in FIG. 10 is connected to N2), and the source of the fifth MOS transistor M5 is connected to the power supply voltage VDD. The drain of the fifth MOS transistor M5 is connected to the current source I _b , and the drain is taken out as the output of the comparator (the output of the comparator is marked as V _out in FIG. 10 ), and the other end of the current source I _b is grounded.

In a preferred implementation manner, the first MOS transistor M1 and the second MOS transistor M2 have the same size, and the third MOS transistor M3 and the fourth MOS transistor M4 have the same size.

In a preferred embodiment, the resistance values of the resistors R1 and R2 are the same.

Fifth Embodiment of Four-Input Comparator

FIG. 11 shows the circuit of the fifth embodiment of the four-input comparator of the present invention. Please refer to FIG. 11. Compared with the four-input comparator of the previous embodiment, the four-input comparator of this embodiment has an input pair of transistors (that is, the first MOS transistor M1 and the second MOS transistor M2) that are PMOS transistors, and The load pair transistors (that is, the third MOS transistor M3 and the fourth MOS transistor M4 ) are NMOS transistors.

The four-input comparator in this embodiment includes: a first MOS transistor M1 , a second MOS transistor M2 , a third MOS transistor M3 , a fourth MOS transistor M4 , and resistors R1 and R2 .

The gate of the first MOS transistor M1 is connected to the first input voltage V _in , the gate of the second MOS transistor M2 is connected to the second input voltage V _ip , the source of the first MOS transistor M1 is connected to the third input voltage V1 through the resistor R1, The source of the second MOS transistor M2 is connected to the fourth input voltage V2 through the resistor R2.

The connection mode of the third MOS transistor M3 and the fourth MOS transistor M4 constitutes a current mirror. Specifically, the gate and drain of the third MOS transistor M3 are short-circuited (marked in FIG. 11 as connecting the gate and drain of M3 with N1 to form a diode connection), and the source of the third MOS transistor M3 The electrode is grounded (V _gnd ), and the drain of the third MOS transistor M3 is connected to the drain of the first MOS transistor M1. The gate of the fourth MOS transistor M4 is connected to the gate of the third MOS transistor M3, the source of the fourth MOS transistor M4 is grounded (V _gnd ), and the drain of the fourth MOS transistor M4 is connected to the drain of the second MOS transistor M2 , and the output of the drain of the fourth MOS transistor M4 is the output of the comparator (marked as the output of the comparator drawn from N2 in FIG. 11 ).

For the four-input comparator, the above circuit can already constitute a basic four-input comparator. In order to better realize its effect, a fifth MOS transistor M5 and a current source _Ib can also be added on the basis of the above circuit, and the gate of the fifth MOS transistor M5 is connected to the drain of the fourth MOS transistor M4 (in FIG. 11 is connected to N2), and the source of the fifth MOS transistor M5 is grounded. The drain of the fifth MOS transistor M5 is connected to the current source I _b , and the drain is drawn out as the output of the comparator (the output of the comparator is marked as V _out in FIG. 11 ), and the other end of the current source I _b is connected to the power supply voltage VDD.

In a preferred implementation manner, the first MOS transistor M1 and the second MOS transistor M2 have the same size, and the third MOS transistor M3 and the fourth MOS transistor M4 have the same size.

In a preferred embodiment, the resistance values of the resistors R1 and R2 are the same.

Sixth Embodiment of Four-Input Comparator

FIG. 12 shows a sixth embodiment of the four-input comparator of the present invention. Please refer to FIG. 12, the four-input terminal comparator of this embodiment is the same as the fifth embodiment, its input pair of transistors (that is, the first MOS transistor M1 and the second MOS transistor M2) are PMOS transistors, and the load pair of transistors (also That is, the third MOS transistor M3 and the fourth MOS transistor M4) are NMOS transistors.

The four-input comparator in this embodiment includes: a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, and a fourth MOS transistor M4.

The gate of the first MOS transistor M1 is connected to the first input voltage V _in , the gate of the second MOS transistor M2 is connected to the second input voltage V _ip (in practical applications, the second input voltage V _ip is set as the reference voltage V _ref ), The source of the first MOS transistor M1 is connected to the third input voltage V1, and the source of the second MOS transistor M2 is connected to the fourth input voltage V2.

The connection mode of the third MOS transistor M3 and the fourth MOS transistor M4 constitutes a current mirror. Specifically, the gate and drain of the third MOS transistor M3 are short-circuited (marked in FIG. 12 as using N1 to connect the gate and drain of M3 to form a diode connection), and the source of the third MOS transistor M3 The electrode is grounded (V _gnd ), and the drain of the third MOS transistor M3 is connected to the drain of the first MOS transistor M1. The gate of the fourth MOS transistor M4 is connected to the gate of the third MOS transistor M3, the source of the fourth MOS transistor M4 is grounded (V _gnd ), and the drain of the fourth MOS transistor M4 is connected to the drain of the second MOS transistor M2 , and the output of the drain of the fourth MOS transistor M4 is the output of the comparator (marked as the output of the comparator drawn from N2 in FIG. 12 ).

For the four-input comparator, the above circuit can already constitute a basic four-input comparator. In order to better realize its effect, a fifth MOS transistor M5 and a current source _Ib can also be added on the basis of the above circuit, and the gate of the fifth MOS transistor M5 is connected to the drain of the fourth MOS transistor M4 (in FIG. 12 is connected to N2), and the source of the fifth MOS transistor M5 is grounded. The drain of the fifth MOS transistor M5 is connected to the current source I _b , and the drain is drawn out as the output of the comparator (the output of the comparator is marked as V _out in FIG. 12 ), and the other end of the current source I _b is connected to the power supply VDD.

In a preferred implementation manner, the first MOS transistor M1 and the second MOS transistor M2 have the same size, and the third MOS transistor M3 and the fourth MOS transistor M4 have the same size.

Seventh Embodiment of Four-Input Comparator

Fig. 13 shows a seventh embodiment of the four-input comparator of the present invention. Please refer to FIG. 13 , the difference between this embodiment and the previous embodiments is that the original MOS transistor is replaced with a BJT transistor (transistor).

The four-input comparator in this embodiment includes: a first transistor Q1 , a second transistor Q2 , a third transistor Q3 and a fourth transistor Q4 .

The base of the first transistor Q1 is connected to the first input voltage V _in , the base of the second transistor Q2 is connected to the second input voltage V _ip , the emitter of the first transistor Q1 is connected to the third input voltage V1 , The emitter of the second transistor Q2 is connected to the fourth input voltage V2.

The connection mode of the third transistor Q3 and the fourth transistor Q4 constitutes a current mirror. Specifically, the base and collector of the third triode Q3 are short-circuited (marked in FIG. 13 as using N1 to connect the base and collector of Q3 to form a diode connection), and the third triode Q3 The emitter of the third transistor Q3 is connected to the power supply voltage VDD, and the collector of the third transistor Q3 is connected to the collector of the first transistor Q1. The base of the fourth transistor Q4 is connected to the base of the third transistor Q3, the emitter of the fourth transistor Q4 is connected to the power supply voltage VDD, and the collector of the fourth transistor Q4 is connected to the second transistor The collector of Q2, and the output of the collector of the fourth transistor Q4 is the output of the comparator (marked as the output of the comparator drawn out by N2 in FIG. 13 ).

For the four-input comparator, the above circuit can already constitute a basic four-input comparator. In order to better realize its effect, a fifth transistor Q5 and a current source I _b can be added on the basis of the above circuit, and the base of the fifth transistor Q5 is connected to the collector of the fourth transistor Q4 (shown as being connected to N2 in FIG. 13 ), the emitter of the fifth transistor Q5 is connected to the power supply voltage VDD. The collector of the fifth transistor Q5 is connected to the current source I _b , and the collector is drawn out as the output of the comparator (the output of the comparator is marked as V _out in FIG. 13 ), and the other end of the current source I _b is grounded.

In a preferred implementation manner, the first triode Q1 and the second triode Q2 have the same size, and the third triode Q3 and the fourth triode Q4 have the same size.

Eighth embodiment of a four-input comparator

FIG. 14 shows an eighth embodiment of the four-input comparator of the present invention. Please refer to FIG. 14 , same as the embodiment in FIG. 13 , this embodiment replaces the original MOS transistor with a BJT transistor (transistor).

The four-input comparator in this embodiment includes: a first transistor Q1 , a second transistor Q2 , a third transistor Q3 , a fourth transistor Q4 , and resistors R1 and R2 .

The base of the first transistor Q1 is connected to the first input voltage V _in , the base of the second transistor Q2 is connected to the second input voltage V _ip , and the emitter of the first transistor Q1 is connected to the third input through the resistor R1 Voltage V1, the emitter of the second transistor Q2 is connected to the fourth input voltage V2 through the resistor R2.

The connection mode of the third transistor Q3 and the fourth transistor Q4 constitutes a current mirror. Specifically, the base and collector of the third triode Q3 are short-circuited (marked in FIG. 14 as connecting the base and collector of Q3 with N1 to form a diode connection), and the third triode Q3 The emitter of the third transistor Q3 is connected to the power supply voltage VDD, and the collector of the third transistor Q3 is connected to the collector of the first transistor Q1. The base of the fourth transistor Q4 is connected to the base of the third transistor Q3, the emitter of the fourth transistor Q4 is connected to the power supply voltage VDD, and the collector of the fourth transistor Q4 is connected to the second transistor The collector of Q2, and the output of the collector of the fourth transistor Q4 is the output of the comparator (marked as the output of the comparator drawn by N2 in FIG. 14 ).

For the four-input comparator, the above circuit can already constitute a basic four-input comparator. In order to better realize its effect, a fifth transistor Q5 and a current source I _b can be added on the basis of the above circuit, and the base of the fifth transistor Q5 is connected to the collector of the fourth transistor Q4 (shown as being connected to N2 in FIG. 14 ), the emitter of the fifth transistor Q5 is connected to the power supply voltage VDD. The collector of the fifth transistor Q5 is connected to the current source I _b , and the collector is drawn out as the output of the comparator (the output of the comparator is marked as V _out in FIG. 14 ), and the other end of the current source I _b is grounded.

In a preferred implementation manner, the first triode Q1 and the second triode Q2 have the same size, and the third triode Q3 and the fourth triode Q4 have the same size.

In a preferred embodiment, the resistance values of the resistors R1 and R2 are the same.

Ninth Embodiment of Four-Input Comparator

FIG. 15 shows a ninth embodiment of the four-input comparator of the present invention. Referring to FIG. 15 , the four-input comparator in this embodiment includes: a first transistor Q1 , a second transistor Q2 , a third transistor Q3 and a fourth transistor Q4 .

The base of the first transistor Q1 is connected to the first input voltage V _in , and the base of the second transistor Q2 is connected to the second input voltage V _ip (the second input voltage can be the reference voltage V _ref in practical applications) , the emitter of the first transistor Q1 is connected to the third input voltage V1, and the emitter of the second transistor Q2 is connected to the fourth input voltage V2.

The connection mode of the third transistor Q3 and the fourth transistor Q4 constitutes a current mirror. Specifically, the base and collector of the third triode Q3 are short-circuited (marked in FIG. 15 as connecting the base and collector of Q3 with N1 to form a diode connection), and the third triode Q3 The emitter of the transistor is grounded (V _gnd ), and the collector of the third transistor Q3 is connected to the collector of the first transistor Q1. The base of the fourth transistor Q4 is connected to the base of the third transistor Q3, the emitter of the fourth transistor Q4 is grounded, and the collector of the fourth transistor Q4 is connected to the collector of the second transistor Q2. electrode, and the output of the collector of the fourth transistor Q4 is the output of the comparator (marked as the output of the comparator drawn from N2 in FIG. 15 ).

For the four-input comparator, the above circuit can already constitute a basic four-input comparator. In order to better realize its effect, a fifth transistor Q5 and a current source I _b can be added on the basis of the above circuit, and the base of the fifth transistor Q5 is connected to the collector of the fourth transistor Q4 (shown as connection N2 in FIG. 15 ), the emitter of the fifth transistor Q5 is grounded. The collector of the fifth triode Q5 is connected to the current source I _b , and the collector is drawn out as the output of the comparator (the output of the comparator is marked as V _out in FIG. 15 ), and the other end of the current source I _b is connected to the power supply voltage VDD .

In a preferred implementation manner, the first triode Q1 and the second triode Q2 have the same size, and the third triode Q3 and the fourth triode Q4 have the same size.

Tenth Embodiment of Four-Input Comparator

Fig. 16 shows a tenth embodiment of the four-input comparator of the present invention. Referring to FIG. 16 , the four-input comparator in this embodiment includes: a first transistor Q1 , a second transistor Q2 , a third transistor Q3 , a fourth transistor Q4 , and resistors R1 and R2 .

The base of the first transistor Q1 is connected to the first input voltage V _in , and the base of the second transistor Q2 is connected to the second input voltage V _ip (in practical applications, the second input voltage V _ip can be set as the reference voltage V _ref ), the emitter of the first transistor Q1 is connected to the third input voltage V1 through the resistor R1, and the emitter of the second transistor Q2 is connected to the fourth input voltage V2 through the resistor R2.

The connection mode of the third transistor Q3 and the fourth transistor Q4 constitutes a current mirror. Specifically, the base and collector of the third triode Q3 are short-circuited (marked in FIG. 16 as using N1 to connect the base and collector of Q3 to form a diode connection), and the third triode Q3 The emitter of the transistor is grounded (V _gnd ), and the collector of the third transistor Q3 is connected to the collector of the first transistor Q1. The base of the fourth transistor Q4 is connected to the base of the third transistor Q3, the emitter of the fourth transistor Q4 is grounded, and the collector of the fourth transistor Q4 is connected to the collector of the second transistor Q2. electrode, and the output of the collector of the fourth transistor Q4 is the output of the comparator (marked as the output of the comparator drawn from N2 in FIG. 16 ).

For the four-input comparator, the above circuit can already constitute a basic four-input comparator. In order to better realize its effect, a fifth transistor Q5 and a current source I _b can be added on the basis of the above circuit, and the base of the fifth transistor Q5 is connected to the collector of the fourth transistor Q4 (shown as connection N2 in FIG. 16 ), the emitter of the fifth transistor Q5 is grounded. The collector of the fifth triode Q5 is connected to the current source I _b , and the collector is drawn out as the output of the comparator (the output of the comparator is marked as V _out in FIG. 16 ), and the other end of the current source I _b is connected to the power supply voltage VDD .

In a preferred implementation manner, the first triode Q1 and the second triode Q2 have the same size, and the third triode Q3 and the fourth triode Q4 have the same size.

In a preferred embodiment, the resistance values of the resistors R1 and R2 are the same.

From the above embodiments, it can be seen that the two input terminals of the four-input terminal comparator of the present invention are relative to different potentials. When the relative potential of the voltage to be detected changes, the corresponding reference voltage V _ref does not need to be changed. In similar applications such as the multi-cell lithium-ion battery application scheme described in the background technology, compared with the implementation method of the traditional comparator, the present invention can directly compare the battery voltage of each string with the same reference voltage under low voltage , so only one reference voltage source circuit is needed, saving multiple reference sources, thereby saving chip cost and improving circuit performance.

The above-mentioned embodiments are provided for those of ordinary skill in the art to implement or use the present invention. Those of ordinary skill in the art can make various modifications or changes to the above-mentioned embodiments without departing from the inventive idea of the present invention. Therefore, the present invention The scope of protection of the invention is not limited by the above-mentioned embodiments, but should be the maximum scope consistent with the innovative features mentioned in the claims.

Claims (14)

1. A four-input comparator comprising: a first MOS transistor and a second MOS transistor, wherein the gate of the first MOS transistor is connected to the first input voltage, and the gate of the second MOS transistor is connected to the second input voltage; The third MOS transistor and the fourth MOS transistor, wherein the gate and drain of the third MOS transistor are short-circuited, the source of the third MOS transistor is connected to the power supply voltage, and the drain of the third MOS transistor is connected to the drain of the first MOS transistor , the gate of the fourth MOS transistor is connected to the gate of the third MOS transistor, the source of the fourth MOS transistor is connected to the power supply voltage, the drain of the fourth MOS transistor is connected to the drain of the second MOS transistor and is a four-input comparison the output of the device; The source of the first MOS transistor is connected to the first resistor, the source of the second MOS transistor is connected to the second resistor, the other end of the first resistor is connected to the third input voltage, and the other end of the second resistor is connected to the fourth input voltage. 2. The four-input comparator according to claim 1, wherein the size of the first MOS transistor and the second MOS transistor are the same, and the size of the third MOS transistor and the fourth MOS transistor are the same. 3. The four-input comparator according to claim 1, wherein the four-input comparator further comprises: The gate of the fifth MOS transistor is connected to the drain of the fourth MOS transistor, the source is connected to the power supply voltage, the drain is connected to a current source which is the output of the four-input comparator, and the other end of the current source is grounded. 4. The four-input comparator according to claim 1, wherein the third input voltage is a ground voltage. 5. A four-input comparator comprising: a first MOS transistor and a second MOS transistor, wherein the gate of the first MOS transistor is connected to the first input voltage, and the gate of the second MOS transistor is connected to the second input voltage; The third MOS transistor and the fourth MOS transistor, wherein the drain and gate of the third MOS transistor are short-circuited, the source of the third MOS transistor is grounded, the drain of the third MOS transistor is connected to the drain of the first MOS transistor, and the drain of the third MOS transistor is connected to the drain of the first MOS transistor. The gate of the four MOS transistors is connected to the gate of the third MOS transistor, the source of the fourth MOS transistor is grounded, and the drain of the fourth MOS transistor is connected to the drain of the second MOS transistor and is the output of the four-input comparator; The source of the first MOS transistor is connected to the first resistor, the source of the second MOS transistor is connected to the second resistor, the other end of the first resistor is connected to the third input voltage, and the other end of the second resistor is connected to the fourth input voltage. 6. The four-input comparator according to claim 5, wherein the size of the first MOS transistor and the second MOS transistor are the same, and the size of the third MOS transistor and the fourth MOS transistor are the same. 7. The four-input comparator according to claim 5, wherein the four-input comparator further comprises: The gate of the fifth MOS transistor is connected to the drain of the fourth MOS transistor, the source is grounded, the drain is connected to a current source which is the output of the four-input comparator, and the other end of the current source is connected to the power supply voltage. 8. The four-input comparator according to claim 5, wherein the gate of the second MOS transistor is connected to a reference voltage. 9. A four-input comparator comprising: a first triode and a second triode, wherein the base of the first triode is connected to the first input voltage, and the base of the second triode is connected to the second input voltage; The third triode and the fourth triode, wherein the base and collector of the third triode are short-circuited, the emitter of the third triode is connected to the power supply voltage, and the collector of the third triode is connected to the first The collector of the triode, the base of the fourth triode are connected to the base of the third triode, the emitter of the fourth triode is connected to the power supply voltage, the collector of the fourth triode is connected to the second three The collector of the pole tube is connected and is the output of the four-input comparator; The emitter of the first triode is connected to the first resistor, the emitter of the second triode is connected to the second resistor, the other end of the first resistor is connected to the third input voltage, and the other end of the second resistor is connected to the fourth input Voltage. 10. The four-input comparator according to claim 9, wherein the first triode and the second triode have the same size, and the third triode and the fourth triode have the same size. 11. The four-input comparator according to claim 9, wherein the four-input comparator further comprises: The base of the fifth transistor is connected to the collector of the fourth transistor, the emitter is connected to the power supply voltage, the collector is connected to a current source which is the output of the four-input comparator, and the other end of the current source is grounded. 12. A four-input comparator comprising: a first triode and a second triode, wherein the base of the first triode is connected to the first input voltage, and the base of the second triode is connected to the second input voltage; The third triode and the fourth triode, wherein the collector and base of the third triode are short-circuited, the collector of the third triode is connected to the collector of the first triode, and the third triode The emitter of the fourth triode is grounded, the base of the fourth triode is connected to the base of the third triode, the emitter of the fourth triode is grounded, the collector of the fourth triode is connected to the collector of the second triode The electrodes are connected and are the output of a four-input comparator; The emitter of the first triode is connected to the first resistor, the emitter of the second triode is connected to the second resistor, the other end of the first resistor is connected to the third input voltage, and the other end of the second resistor is connected to the fourth input Voltage. 13. The four-input comparator according to claim 12, wherein the first triode and the second triode have the same size, and the third triode and the fourth triode have the same size. 14. The four-input comparator according to claim 12, wherein the four-input comparator further comprises: The base of the fifth transistor is connected to the collector of the fourth transistor, the emitter is grounded, the collector is connected to a current source and is the output of the four-input comparator, and the other end of the current source is connected to the power supply voltage.

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