CN110971221B - Time delay circuit - Google Patents
Time delay circuit Download PDFInfo
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- CN110971221B CN110971221B CN201811147683.8A CN201811147683A CN110971221B CN 110971221 B CN110971221 B CN 110971221B CN 201811147683 A CN201811147683 A CN 201811147683A CN 110971221 B CN110971221 B CN 110971221B
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- 239000003990 capacitor Substances 0.000 claims abstract description 46
- 239000004065 semiconductor Substances 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims 9
- 230000007423 decrease Effects 0.000 description 4
- 230000007306 turnover Effects 0.000 description 3
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/28—Modifications for introducing a time delay before switching
- H03K17/284—Modifications for introducing a time delay before switching in field effect transistor switches
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/14—Modifications for compensating variations of physical values, e.g. of temperature
- H03K17/145—Modifications for compensating variations of physical values, e.g. of temperature in field-effect transistor switches
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
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Abstract
The present invention provides a delay circuit comprising: the delay circuit comprises a first switch unit, a first capacitor, a second switch unit, a second capacitor and a current compensation unit, wherein the first switch unit and the second switch unit are connected between a first voltage and a second voltage, and the current compensation unit is connected with the first capacitor and/or the second capacitor in series and/or in parallel between the first voltage and the second voltage, wherein the current compensation unit comprises at least one NMOS tube and is used for compensating charge and discharge current for the delay circuit, so that the delay variation of the delay circuit is reduced when the power supply voltage is changed. The delay circuit provided by the invention is provided with the current compensation unit, the charge and discharge current of the capacitor is slightly larger than that of the traditional delay circuit, and the current flowing through the current compensation unit is hardly changed when the power supply voltage is changed, so that the delay variation of the circuit is very small when the power supply voltage is changed, and the delay is more convergent and stable.
Description
Technical Field
The invention relates to the field of integrated circuits, in particular to a delay circuit.
Background
The delay circuit has wide application in integrated circuits, and the stable delay circuit is beneficial to deburring of digital circuits, starting of analog circuits and the like.
According to t=c U/I, the delay of the delay circuit as a function of the supply voltage appears in two ways: the first is the change of the flip voltage, and the second is the change of the charge-discharge current. For the traditional delay circuit, as the power supply voltage is reduced, the turnover voltage U is reduced, the charge and discharge current I is reduced, and the change rate of delay is reduced under the combined action of the turnover voltage U and the charge and discharge current I, but the change rate of delay is still larger because the change proportion of the turnover voltage U and the charge and discharge current I is inconsistent.
Therefore, in order to solve the above-mentioned problems, it is necessary to propose a novel delay circuit to improve the above-mentioned problems.
Disclosure of Invention
In the summary, a series of concepts in a simplified form are introduced, which will be further described in detail in the detailed description. The summary of the invention is not intended to define the key features and essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
In order to solve the problems existing at present, an aspect of the present invention provides a delay circuit, including: the delay circuit comprises a first switch unit, a first capacitor, a second switch unit, a second capacitor and a current compensation unit, wherein the first switch unit and the second switch unit are connected between a first voltage and a second voltage, and the current compensation unit is connected with the first capacitor and/or the second capacitor in series and/or in parallel between the first voltage and the second voltage, wherein the current compensation unit comprises at least one NMOS tube and is used for compensating charge and discharge current for the delay circuit, so that the delay variation of the delay circuit is reduced when the power supply voltage is changed.
In one embodiment, the first switch unit includes a first PMOS transistor, a first NMOS transistor, and a first current limiting resistor, where gates of the first PMOS transistor and the first NMOS transistor are both connected to an input signal, a source of the first PMOS transistor is connected to the first voltage, a source of the first NMOS transistor is connected to the second voltage, a drain of the first PMOS transistor is connected to one end of the first current limiting resistor, and a drain of the first NMOS transistor is connected to the other end of the first current limiting resistor; one end of the first capacitor is connected with a first node between the drain electrode of the first NMOS tube and the first current limiting resistor, and the other end of the first capacitor is connected with the second voltage; the second switch unit comprises a second PMOS tube, a second NMOS tube and a second current limiting resistor, wherein grid electrodes of the second PMOS tube and the second NMOS tube are connected to the first node, a source electrode of the second PMOS tube is connected with the first voltage, a source electrode of the second NMOS tube is connected with the second voltage, a drain electrode of the second PMOS tube is connected with one end of the second current limiting resistor, and a drain electrode of the second NMOS tube is connected with the other end of the second current limiting resistor; one end of the second capacitor is connected with a second node between the drain electrode of the second PMOS tube and the second current limiting resistor, the other end of the second capacitor is connected with the first voltage, and the second node is connected with an output signal.
In one embodiment, the current compensation unit includes a third NMOS transistor and a fourth NMOS transistor, where a drain of the third NMOS transistor is connected to the first voltage, a source is connected to the first node, and a gate is connected to an inverted signal of the input signal; and the source electrode of the fourth NMOS tube is connected with the second voltage, the drain electrode of the fourth NMOS tube is connected with the second node, and the grid electrode of the fourth NMOS tube is connected with the inverted signal of the input signal.
In one embodiment, the delay circuit further includes a first inverter and a second inverter, where the first switch unit includes a first PMOS tube, a first NMOS tube, and a first current limiting resistor, where a source of the first PMOS tube is connected to the first voltage, a source of the first NMOS tube is connected to the second voltage, a drain of the first PMOS tube is connected to one end of the first current limiting resistor, and a drain of the first NMOS tube is connected to the other end of the first current limiting resistor; the input end of the first inverter is connected with an input signal, and the grid electrodes of the first PMOS tube and the first NMOS tube are both connected with the output end of the first inverter; one end of the first capacitor is connected with a first node between the drain electrode of the first NMOS tube and the first current limiting resistor, and the other end of the first capacitor is connected with the second voltage; the second switch unit comprises a second PMOS tube, a second NMOS tube and a second current limiting resistor, wherein grid electrodes of the second PMOS tube and the second NMOS tube are connected to the first node, a source electrode of the second PMOS tube is connected with the first voltage, a source electrode of the second NMOS tube is connected with the second voltage, a drain electrode of the second PMOS tube is connected with one end of the second current limiting resistor, and a drain electrode of the second NMOS tube is connected with the other end of the second current limiting resistor; one end of the second capacitor is connected with a second node between the drain electrode of the second PMOS tube and the second current limiting resistor, and the other end of the second capacitor is connected with the first voltage; the input end of the second inverter is connected with the second node, and the output end of the second inverter is connected with an output signal.
In one embodiment, the current compensation unit includes a third NMOS transistor and a fourth NMOS transistor, where a drain of the third NMOS transistor is connected to the first voltage, a source is connected to the first node, and a gate is connected to the input signal; and the source electrode of the fourth NMOS tube is connected with the second voltage, the drain electrode of the fourth NMOS tube is connected with the second node, and the grid electrode of the fourth NMOS tube is connected with the input signal.
In one embodiment, the first switching unit further includes a third current limiting resistor, the second switching unit further includes a fourth current limiting resistor, the current compensation unit further includes a fifth NMOS transistor and a sixth NMOS transistor, wherein the third current limiting resistor is connected between a drain of the first NMOS transistor and the first node; the fourth current limiting resistor is connected between the drain electrode of the second PMOS tube and the second node; the drain electrode of the fifth NMOS tube is connected with the first node, the source electrode of the fifth NMOS tube is connected with the second voltage, and the grid electrode of the fifth NMOS tube is connected with the input signal; and the drain electrode of the sixth NMOS tube is connected with the first voltage, the source electrode of the sixth NMOS tube is connected with the second node, and the grid electrode of the sixth NMOS tube is connected with the input signal.
In one embodiment, the first switching unit further includes a third current limiting resistor, the second switching unit further includes a fourth current limiting resistor, the current compensation unit further includes a fifth NMOS transistor and a sixth NMOS transistor, wherein the third current limiting resistor is connected between a drain of the first NMOS transistor and the first node; the fourth current limiting resistor is connected between the drain electrode of the second PMOS tube and the second node; the drain electrode of the fifth NMOS tube is connected with the first node, the source electrode of the fifth NMOS tube is connected with the second voltage, and the grid electrode of the fifth NMOS tube is connected with an inverted signal of the input signal; and the drain electrode of the sixth NMOS tube is connected with the first voltage, the source electrode of the sixth NMOS tube is connected with the second node, and the grid electrode of the sixth NMOS tube is connected with the inverted signal of the input signal.
In one embodiment, the first voltage is greater than the second voltage.
In one embodiment, the first voltage is a power supply voltage and the second voltage is a ground voltage.
According to another aspect of the present invention there is provided a semiconductor device comprising a delay circuit as described above.
According to a further aspect of the invention there is provided an electronic device comprising a semiconductor device comprising a delay circuit as described in any one of the above.
The delay circuit provided by the invention is provided with the current compensation unit, the charge and discharge current of the capacitor is slightly larger than that of the traditional delay circuit, and the current flowing through the current compensation unit is hardly changed when the power supply voltage is changed, so that the delay variation of the circuit is very small when the power supply voltage is changed, and the delay is more convergent and stable.
Drawings
The following drawings are included to provide an understanding of the invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and their description to explain the principles of the invention.
In the accompanying drawings:
fig. 1 shows a circuit schematic of a conventional delay circuit;
FIG. 2 shows a schematic circuit diagram of a delay circuit according to one embodiment of the invention; and
fig. 3 shows a circuit schematic of a delay circuit according to another embodiment of the invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the invention may be practiced without one or more of these details. In other instances, well-known features have not been described in detail in order to avoid obscuring the invention.
It should be understood that the present invention may be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size of layers and regions, as well as the relative sizes, may be exaggerated for clarity. Like numbers refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on" …, "" adjacent to "…," "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected to or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on" …, "" directly adjacent to "…," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatially relative terms, such as "under …," "under …," "below," "under …," "above …," "above," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "under …" and "under …" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
In the following description, for the purpose of providing a thorough understanding of the present invention, detailed structures and steps are presented in order to illustrate the technical solution presented by the present invention. Preferred embodiments of the present invention are described in detail below, however, the present invention may have other embodiments in addition to these detailed descriptions.
For a better understanding of the present invention, a conventional delay circuit structure is briefly described below in conjunction with fig. 1.
A circuit schematic of a conventional delay circuit is shown in fig. 1. As shown in fig. 1, the delay circuit 100 includes a first inverter S11, a first switching unit SW11, a first capacitor C10, a second switching unit SW12, a second capacitor C11, and a second inverter S12. The first switch unit SW11 includes a PMOS transistor M11, an NMOS transistor M12 and a first current limiting resistor R11, and the second switch unit SW12 includes a PMOS transistor M13, an NMOS transistor M14 and a second current limiting resistor R12.
According to the delay circuit 100 of fig. 1, when the input signal VIN changes from low level to high level, the signal changes from high level to low level after passing through the first inverter S11, the PMOS transistor M11 of the first switch unit SW11 is turned on to charge the capacitor C10, the level at point a is pulled up, the NMOS transistor M14 of the second switch unit SW12 is turned on, the capacitor C11 is discharged, the level at point B is pulled down, and finally the output signal is high level after passing through the second inverter S12.
In the delay circuit, as the power supply voltage VDD decreases, the flip voltage decreases, and the charge-discharge current decreases, so that the rate of change of delay decreases under the combined action of the flip voltage VDD and the charge-discharge current, but the change ratio of delay is inconsistent, so that the change range of delay is still larger.
In order to solve the above problems, the present invention provides a delay circuit comprising: the delay circuit comprises a first switch unit, a first capacitor, a second switch unit, a second capacitor and a current compensation unit, wherein the first switch unit and the second switch unit are connected between a first voltage and a second voltage, and the current compensation unit is connected with the first capacitor and/or the second capacitor in series and/or in parallel between the first voltage and the second voltage, wherein the current compensation unit comprises at least one NMOS tube and is used for compensating charge and discharge current for the delay circuit, so that the delay variation of the delay circuit is reduced when the power supply voltage is changed. The delay circuit provided by the invention is provided with the current compensation unit, the charge and discharge current of the capacitor is slightly larger than that of the traditional delay circuit, and the current flowing through the current compensation unit is hardly changed when the power supply voltage is changed, so that the delay variation of the circuit is very small when the power supply voltage is changed, and the delay is more convergent and stable.
Specific embodiments of the present invention are described in detail below.
Fig. 2 shows a circuit schematic of a delay circuit according to an embodiment of the invention. Illustratively, the delay circuit 10 shown in fig. 2 includes a first switching unit SW1, a first capacitor C0, a second switching unit SW2, a second capacitor C1, and a current compensation unit.
The first switch unit SW1 includes a first PMOS transistor M1, a first NMOS transistor M2, and a first current limiting resistor R1, where gates of the first PMOS transistor M1 and the first NMOS transistor M2 are both connected to an input signal (VIN in fig. 2), a source of the first PMOS transistor M1 is connected to a first voltage (VDD in fig. 2), a source of the first NMOS transistor M2 is connected to a second voltage (VSS in fig. 2), a drain of the first PMOS transistor M1 is connected to one end of the first current limiting resistor R1, and a drain of the first NMOS transistor M2 is connected to the other end of the first current limiting resistor R1.
Wherein the first voltage VDD is greater than the second voltage VSS. Preferably, the first voltage VDD is a power supply voltage and the second voltage VSS is a ground voltage. For example, the first voltage VDD may be 3.6V and the second voltage VSS may be 0V.
One end of the first capacitor C0 is connected to a first node (a shown in fig. 2) between the drain of the first NMOS transistor M2 and the first current limiting resistor R1, and the other end is connected to the second voltage VSS.
The second switch unit SW2 includes a second PMOS transistor M3, a second NMOS transistor M4, and a second current limiting resistor R2, gates of the second PMOS transistor M3 and the second NMOS transistor M4 are all connected to the first node a, a source of the second PMOS transistor M3 is connected to the first voltage VDD, a source of the second NMOS transistor M4 is connected to the second voltage VSS, a drain of the second PMOS transistor M3 is connected to one end of the second current limiting resistor R2, and a drain of the second NMOS transistor M4 is connected to the other end of the second current limiting resistor R2.
One end of the second capacitor C1 is connected to a second node (B in fig. 2) between the drain of the second PMOS transistor M3 and the second current limiting resistor R2, and the other end is connected to the first voltage VDD, and the second node B is connected to an output signal (OUT in fig. 2).
The current compensation unit includes at least one NMOS transistor for compensating the charge and discharge current for the delay circuit 10, so that the delay variation of the delay circuit 10 becomes smaller when the power supply voltage is changed. Since two MOS transistors are turned on at both the rising edge and the falling edge of the input signal, the current compensation unit of this embodiment preferably includes two MOS transistors, i.e., the third NMOS transistor M5 and the fourth NMOS transistor M6.
The drain electrode of the third NMOS tube M5 is connected with the first voltage VDD, the source electrode is connected with the first node A, and the grid electrode is connected with an inverted signal of the input signal end VIN; the source of the fourth NMOS transistor M6 is connected to the second voltage VSS, the drain is connected to the second node B, and the gate is connected to the inverted signal of the input signal VIN.
Illustratively, the delay circuit 10 may further include a first inverter S1 and a second inverter S2. The first inverter S1 is connected between the input signal VIN and the gates of the first PMOS transistor M1 and the first NMOS transistor M2. Specifically, the input end of the first inverter S1 is connected to the input signal VIN, and the gates of the first PMOS transistor M1 and the first NMOS transistor M2 are both connected to the output end of the first inverter S1, and at this time, the gates of the third NMOS transistor M5 and the fourth NMOS transistor M6 should be connected to the input signal VIN. Wherein the second inverter S2 is connected between the second node B and the output signal OUT. Specifically, the input terminal of the second inverter S2 is connected to the second node B, and the output terminal is connected to the output signal OUT.
According to the embodiment, when the input signal VIN changes from low level to high level, the current flowing through the first PMOS transistor M1 and the third NMOS transistor M5 charges the capacitor C0, the charging current is increased compared with the conventional delay circuit, and the charging speed is increased; and the capacitor C1 discharges through two paths of the second NMOS tube M4 and the fourth NMOS tube M6, the discharge current is increased compared with the traditional delay circuit, and the discharge speed is accelerated. In addition, when the power supply voltage changes, the current flowing through the current compensation unit is hardly changed, so when the power supply voltage changes, compared with the traditional delay circuit, the delay circuit disclosed by the invention is added with two relatively stable charge and discharge current paths for compensation, so that the change amount of delay is very small, and the delay is more convergent and more stable.
Fig. 3 shows a circuit schematic of a delay circuit according to another embodiment of the invention. Compared to the embodiment of fig. 2, there are only a few more elements than the delay circuit of fig. 3. For brevity, elements identical to those of the fig. 2 embodiment will not be repeated in this embodiment, and only elements different from those of the fig. 2 embodiment will be described.
Illustratively, the first switching unit SW1 of the delay circuit of fig. 3 further includes a third current limiting resistor R3, the second switching unit SW2 further includes a fourth current limiting resistor R4, and the current compensation unit further includes a fifth NMOS transistor M7 and a sixth NMOS transistor M8.
The third current limiting resistor R3 is connected between the drain of the first NMOS transistor M2 and the first node a, and the fourth current limiting resistor R4 is connected between the drain of the second PMOS transistor M3 and the second node B.
The drain of the fifth NMOS transistor M7 is connected to the first node a, the source is connected to the second voltage VSS, and the gate is connected to the inverted signal of the input signal VIN. The source of the sixth NMOS transistor M8 is connected to the second node B, the drain is connected to the first voltage VDD, and the gate is connected to the inverted signal of the input signal VIN.
Of course, the embodiment of fig. 3 may also not include the first inverter S1 and the second inverter S2, where the gate of the first PMOS transistor M1 and the gate of the first NMOS transistor M2 are directly connected to the input signal VIN, and the second node B is directly connected to the output signal OUT. At this time, the gates of the fifth NMOS transistor M7 and the sixth NMOS transistor M8 should be connected to the input signal VIN.
According to the embodiment, both the rising edge and the falling edge of the input signal are added with two charge and discharge current paths for compensation, so that the delay variation of the circuit is smaller when the power supply voltage is changed, and the delay is more convergent and stable.
It should be noted that the current compensation units of the delay circuits in the above two embodiments include two NMOS transistors and four NMOS transistors, respectively, but it should be noted that this is merely exemplary and is not intended to limit the present invention thereto. According to the invention, the current compensation unit can comprise any number of NMOS tubes, so long as the effect of compensating the charge and discharge currents of the capacitor can be achieved.
According to another embodiment of the present invention, a semiconductor device is provided, which includes a delay circuit as described in any one of the above two embodiments, and the specific structure of the delay circuit is referred to the above embodiments and will not be described herein. The semiconductor device may also include any other structures known to those skilled in the art, and will not be described in detail herein.
According to still another embodiment of the present invention, an electronic device is provided, which includes a semiconductor device, where the semiconductor device includes a delay circuit as described in any one of the above two embodiments, and the specific structure of the delay circuit is referred to the above embodiments and will not be described herein. The electronic device may also include any other structures known to those skilled in the art, and will not be described in detail herein.
The present invention has been illustrated by the above-described embodiments, but it should be understood that the above-described embodiments are for purposes of illustration and description only and are not intended to limit the invention to the embodiments described. In addition, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications are possible in light of the teachings of the invention, which variations and modifications are within the scope of the invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (11)
1. A delay circuit, comprising: the delay circuit comprises a first switch unit, a first capacitor, a second switch unit, a second capacitor and a current compensation unit, wherein the first switch unit and the second switch unit are connected between a first voltage and a second voltage, the current compensation unit is connected with the first capacitor and/or the second capacitor in series and/or in parallel between the first voltage and the second voltage, the first switch unit and the second switch unit comprise MOS tubes, the substrate of each MOS tube is connected with the first voltage or the second voltage, and the current compensation unit comprises at least one NMOS tube for compensating charge and discharge current for the delay circuit, so that the delay variation of the delay circuit is reduced when the power supply voltage is changed.
2. The delay circuit of claim 1, wherein,
the first switch unit comprises a first PMOS tube, a first NMOS tube and a first current limiting resistor, wherein grid electrodes of the first PMOS tube and the first NMOS tube are connected with input signals, a source electrode and a substrate of the first PMOS tube are connected with the first voltage, a source electrode and a substrate of the first NMOS tube are connected with the second voltage, a drain electrode of the first PMOS tube is connected with one end of the first current limiting resistor, and a drain electrode of the first NMOS tube is connected with the other end of the first current limiting resistor;
one end of the first capacitor is connected with a first node between the drain electrode of the first NMOS tube and the first current limiting resistor, and the other end of the first capacitor is connected with the second voltage;
the second switch unit comprises a second PMOS tube, a second NMOS tube and a second current limiting resistor, wherein grid electrodes of the second PMOS tube and the second NMOS tube are connected to the first node, a source electrode and a substrate of the second PMOS tube are connected with the first voltage, a source electrode and a substrate of the second NMOS tube are connected with the second voltage, a drain electrode of the second PMOS tube is connected with one end of the second current limiting resistor, and a drain electrode of the second NMOS tube is connected with the other end of the second current limiting resistor;
one end of the second capacitor is connected with a second node between the drain electrode of the second PMOS tube and the second current limiting resistor, the other end of the second capacitor is connected with the first voltage, and the second node is connected with an output signal.
3. The delay circuit of claim 2, wherein the current compensation unit comprises a third NMOS transistor and a fourth NMOS transistor, wherein,
the drain electrode of the third NMOS tube is connected with the first voltage, the source electrode of the third NMOS tube is connected with the first node, and the grid electrode of the third NMOS tube is connected with an inverted signal of the input signal;
and the source electrode of the fourth NMOS tube is connected with the second voltage, the drain electrode of the fourth NMOS tube is connected with the second node, and the grid electrode of the fourth NMOS tube is connected with the inverted signal of the input signal.
4. The delay circuit of claim 1, further comprising a first inverter and a second inverter, wherein,
the first switch unit comprises a first PMOS tube, a first NMOS tube and a first current limiting resistor, wherein a source electrode and a substrate of the first PMOS tube are connected with the first voltage, the source electrode and the substrate of the first NMOS tube are connected with the second voltage, a drain electrode of the first PMOS tube is connected with one end of the first current limiting resistor, and a drain electrode of the first NMOS tube is connected with the other end of the first current limiting resistor;
the input end of the first inverter is connected with an input signal, and the grid electrodes of the first PMOS tube and the first NMOS tube are both connected with the output end of the first inverter;
one end of the first capacitor is connected with a first node between the drain electrode of the first NMOS tube and the first current limiting resistor, and the other end of the first capacitor is connected with the second voltage;
the second switch unit comprises a second PMOS tube, a second NMOS tube and a second current limiting resistor, wherein grid electrodes of the second PMOS tube and the second NMOS tube are connected to the first node, a source electrode and a substrate of the second PMOS tube are connected with the first voltage, a source electrode and a substrate of the second NMOS tube are connected with the second voltage, a drain electrode of the second PMOS tube is connected with one end of the second current limiting resistor, and a drain electrode of the second NMOS tube is connected with the other end of the second current limiting resistor;
one end of the second capacitor is connected with a second node between the drain electrode of the second PMOS tube and the second current limiting resistor, and the other end of the second capacitor is connected with the first voltage;
the input end of the second inverter is connected with the second node, and the output end of the second inverter is connected with an output signal.
5. The delay circuit of claim 4, wherein the current compensation unit comprises a third NMOS transistor and a fourth NMOS transistor, wherein,
the drain electrode of the third NMOS tube is connected with the first voltage, the source electrode of the third NMOS tube is connected with the first node, and the grid electrode of the third NMOS tube is connected with the input signal;
and the source electrode of the fourth NMOS tube is connected with the second voltage, the drain electrode of the fourth NMOS tube is connected with the second node, and the grid electrode of the fourth NMOS tube is connected with the input signal.
6. The delay circuit of claim 3 wherein said first switching element further comprises a third current limiting resistor, said second switching element further comprises a fourth current limiting resistor, said current compensation element further comprises a fifth NMOS tube and a sixth NMOS tube, wherein,
the third current limiting resistor is connected between the drain electrode of the first NMOS tube and the first node;
the fourth current limiting resistor is connected between the drain electrode of the second PMOS tube and the second node;
the drain electrode of the fifth NMOS tube is connected with the first node, the source electrode of the fifth NMOS tube is connected with the second voltage, and the grid electrode of the fifth NMOS tube is connected with the input signal;
and the drain electrode of the sixth NMOS tube is connected with the first voltage, the source electrode of the sixth NMOS tube is connected with the second node, and the grid electrode of the sixth NMOS tube is connected with the input signal.
7. The delay circuit of claim 5, wherein the first switching unit further comprises a third current limiting resistor, the second switching unit further comprises a fourth current limiting resistor, the current compensation unit further comprises a fifth NMOS tube and a sixth NMOS tube, wherein,
the third current limiting resistor is connected between the drain electrode of the first NMOS tube and the first node;
the fourth current limiting resistor is connected between the drain electrode of the second PMOS tube and the second node;
the drain electrode of the fifth NMOS tube is connected with the first node, the source electrode of the fifth NMOS tube is connected with the second voltage, and the grid electrode of the fifth NMOS tube is connected with an inverted signal of the input signal;
and the drain electrode of the sixth NMOS tube is connected with the first voltage, the source electrode of the sixth NMOS tube is connected with the second node, and the grid electrode of the sixth NMOS tube is connected with the inverted signal of the input signal.
8. The delay circuit of any of claims 2-7, wherein the first voltage is greater than the second voltage.
9. The delay circuit of claim 8, wherein the first voltage is a supply voltage and the second voltage is a ground voltage.
10. A semiconductor device, characterized in that the semiconductor device comprises a delay circuit as claimed in any of claims 1-9.
11. An electronic device comprising a semiconductor device comprising a delay circuit as claimed in any one of claims 1-9.
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| CN201811147683.8A CN110971221B (en) | 2018-09-29 | 2018-09-29 | Time delay circuit |
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| CN201811147683.8A CN110971221B (en) | 2018-09-29 | 2018-09-29 | Time delay circuit |
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| JP2005229744A (en) * | 2004-02-13 | 2005-08-25 | Ricoh Co Ltd | Slope building out circuit, switching regulator, and electronic equipment |
| CN102130668A (en) * | 2010-01-20 | 2011-07-20 | 上海华虹Nec电子有限公司 | Time-delay circuit |
| CN103973224A (en) * | 2014-05-20 | 2014-08-06 | 上海华力微电子有限公司 | Single-capacitor oscillator |
| WO2017054479A1 (en) * | 2015-09-30 | 2017-04-06 | 中兴通讯股份有限公司 | Slope compensation circuit and method |
| CN107769545A (en) * | 2017-11-09 | 2018-03-06 | 上海华力微电子有限公司 | A kind of charge pump circuit for being used for capacitor electric leakage compensation in PLL |
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| JP2005229744A (en) * | 2004-02-13 | 2005-08-25 | Ricoh Co Ltd | Slope building out circuit, switching regulator, and electronic equipment |
| CN102130668A (en) * | 2010-01-20 | 2011-07-20 | 上海华虹Nec电子有限公司 | Time-delay circuit |
| CN103973224A (en) * | 2014-05-20 | 2014-08-06 | 上海华力微电子有限公司 | Single-capacitor oscillator |
| WO2017054479A1 (en) * | 2015-09-30 | 2017-04-06 | 中兴通讯股份有限公司 | Slope compensation circuit and method |
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