CN104282709B - Nonvolatile memory devices - Google Patents

Abstract

The nonvolatile memory device of the embodiment includes: a first wiring extending in a first direction; a second wiring extending in a second direction perpendicular to the first direction and electrically connected to the first wiring; 3. The wirings each extend in a third direction intersecting the first direction and perpendicular to the second direction. The plurality of third wirings are arranged side by side along the second direction on both sides of the second wiring. The device further includes: a first storage layer disposed between one of the plurality of third wirings facing each other across the second wiring and the second wiring; a second storage layer disposed between the above-mentioned Between the other of the two third wirings and the above-mentioned second wiring. The second wiring has a block portion between a first portion connected to the first memory layer and a second portion connected to the second memory layer.

Description

non-volatile storage device

related application

This application takes U.S. Provisional Patent Application No. 61/844, No. 234 (filing date: July 9, 2013) as the basic application, and enjoys the right of priority. This application incorporates the entire content of the basic application by referring to this basic application.

technical field

Embodiments relate to non-volatile memory devices.

Background technique

In order to realize a next-generation nonvolatile memory device, the development of a memory cell array having a three-dimensional structure is further advanced. For example, there is a structure in which a plurality of bit lines extending in a direction perpendicular to a base semiconductor substrate are provided, and a plurality of memory cells are arranged along each extending direction. In the memory cell array having such a structure, a cell structure is adopted in which a memory layer is provided on the sidewall of the bit line. In order to increase the memory capacity, a structure in which two memory cells face each other across a bit line is generally adopted.

In this case, when one of the two memory cells facing each other across the bit line is selected, its operation may affect the storage state of the other memory cell. Such a phenomenon becomes a cause of a malfunction called "crosstalk" and reduces the reliability of the memory device.

Contents of the invention

Embodiments of the present invention suppress crosstalk in non-volatile memory devices.

The nonvolatile memory device of the embodiment includes: a first wiring extending in a first direction; a second wiring extending in a second direction perpendicular to the first direction and electrically connected to the first wiring; 3. The wirings each extend in a third direction intersecting the first direction and perpendicular to the second direction. The plurality of third wirings are arranged side by side along the second direction on both sides of the second wiring. The above device further includes: a first storage layer provided between one of the two third wirings facing each other across the second wiring and the second storage layer; a second storage layer provided on the above-mentioned Between the other of the two third wirings and the above-mentioned second wiring. The second wiring has a block portion between a first portion connected to the first memory layer and a second portion connected to the second memory layer.

Description of drawings

FIG. 1 is an example of a perspective view schematically showing a memory cell array of a nonvolatile memory device according to a first embodiment.

FIG. 2 is an example of a perspective view schematically showing the structure of the memory cell array of the first embodiment viewed from above.

FIG. 3 is an example of a block diagram showing the nonvolatile memory device of the first embodiment.

FIG. 4 is an example of a cross-sectional view schematically showing the memory cell array of the first embodiment.

5A and 5B are schematic diagrams showing a memory cell array of a comparative example.

6A and 6B are examples of schematic diagrams showing the memory cell array of the first embodiment.

7 to 11C are examples of schematic diagrams showing the manufacturing process of the memory cell array of the first embodiment.

FIG. 12 is an example of a schematic diagram showing a memory cell array according to a modified example of the first embodiment.

13A to 13C are examples of schematic diagrams showing memory cell arrays in other modified examples of the first embodiment.

FIG. 14 is an example of a cross-sectional view schematically showing a memory cell array of the second embodiment.

15 is an example of a cross-sectional view schematically showing a memory cell array of a nonvolatile memory device according to a third embodiment.

detailed description

Hereinafter, an embodiment will be described with reference to the drawings. The same part in the drawings is attached with the same number, and the detailed description thereof is appropriately omitted, and a different part will be described. In addition, the drawings are schematic or conceptual diagrams, and the relationship between the thickness and width of each part, the size ratio between parts, and the like are not necessarily the same as the actual ones. In addition, even when the same portion is shown, it may be shown with different dimensions and ratios depending on the drawings.

In the following description, the arrangement of each component will be described with reference to the three axial directions perpendicular to each other shown in the drawings, that is, the X direction, the Y direction, and the Z direction. In addition, the Z direction may be described as upward, and the opposite direction may be described as downward.

[first embodiment]

The nonvolatile memory device 100 of the first embodiment includes a memory cell array 1 having a three-dimensional structure. The memory cell array 1 includes, for example, a plurality of variable resistance memory cells MC.

Hereinafter, a nonvolatile memory device 100 according to a first embodiment will be described with reference to FIGS. 1 to 4 .

FIG. 1 is an example of a perspective view schematically showing a memory cell array 1 . The memory cell array 1 includes: a first wiring extending in a first direction; a second wiring extending in a second direction perpendicular to the first direction and electrically connected to the first wiring; A plurality of third wirings respectively extending in third directions perpendicular to each other.

In this example, the first direction is the X direction, the second direction is the Z direction, and the third direction is the Y direction. The extending directions of the respective wirings are perpendicular to each other, but are not limited to being perpendicular in a strict sense. For example, deviations from orthogonality due to manufacturing techniques and the like are tolerated, as long as they are in a substantially orthogonal state. In addition, the third direction is not limited to the Y direction perpendicular to the X direction, and may be a direction intersecting the X direction within the X-Y plane.

The first wiring is, for example, the global bit line 10 and extends in the X direction. In addition, the memory cell array 1 has a plurality of global bit lines 10 . The plurality of global bit lines 10 are parallel to each other and arranged side by side in the Y direction.

The second wiring is, for example, a local bit line 20 and extends in the Z direction. The local bit line 20 is electrically connected to the global bit line 10 via a selection element 50 such as a thin film transistor (Thin Film Transistor: TFT). One global bit line 10 is electrically connected to a plurality of local bit lines 20 .

The third wiring is, for example, the word line 30 and extends in the Y direction. The memory cell array 1 includes a plurality of word lines 30 . The word lines 30 are disposed on both sides of the local bit lines 20 . The plurality of word lines 30 are parallel to each other on each side, and are arranged side by side in the Z direction.

Between the local bit line 20 and the word line 30, a storage layer 40 is provided. The storage layer 40 includes, for example, a resistance change material that reversibly migrates between a first state and a second state having lower resistance than the first state.

The resistance change material is, for example, made from hafnium (Hf), zirconium (Zr), nickel (Ni), tantalum (Ta), tungsten (W), cobalt (Co), aluminum (Al), iron (Fe), manganese (Mn ), an oxide of at least one element selected from the group consisting of chromium (Cr) and niobium (Nb) as the main component. For example, the resistance change material is a thin film of a material including _{HfO 2} , Al ₂ O ₃ , TiO ₂ , NiO, WO ₃ , Ta ₂ O ₅ , or the like. The impedance variable material can reversibly change its impedance value by passing a predetermined current or applying a predetermined voltage.

In addition, ionic resistance change materials can also be used. For example, single crystal or polycrystal Si, Ge, SiGe, GaAs, InP, GaP, GaInAsP, GaN, SiC, HfSi, HfO, AlO or these laminates can be used as the resistance change material. film etc. At this time, as electrodes of the variable resistance material, for example, Ag, Au, Ti, Ni, Co, Al, Fe, Cr, Cu, Electrodes of W, Hf, Ta, Pt, Ru, Zr or Ir and their nitrides or carbides. In addition, the electrodes may be made of polysilicon with the above-mentioned materials added thereto. In addition, a barrier layer of TaSiN may be inserted on the opposite side of the electrode of the variable resistance material.

Furthermore, the memory cell array 1 includes a selection element 50 between the global bit line 10 and the local bit line 20 . The selection element 50 performs on-off control of the electrical conduction between the global bit line 10 and the local bit line 20 , for example. The selection element 50 is a thin film transistor having, for example, a conductive portion 51 extending in the Z direction, a gate electrode 53 facing a side surface of the conductive portion 51 , and a gate insulating film 55 provided between the conductive portion 51 and the gate electrode 53 . That is, the selection element 50 exemplified here is a transistor having a channel through which current flows in the Z direction.

In addition, in FIG. 1 , the insulating films between the global bit lines 10 and the local bit lines 20 in the Y direction are not shown for ease of viewing the drawing.

FIG. 2 is an example of a perspective view schematically showing the structure of the memory cell array 1 viewed from above. FIG. 2 shows an example of the arrangement of word lines 30 with respect to local bit lines 20 .

As shown in FIG. 2 , a plurality of global bit lines 10 are arranged in parallel in the Y direction. On one global bit line 10, a plurality of local bit lines 20 are arranged side by side in the X direction. In addition, the local bit lines 20 may also be arranged side by side in the Y direction. That is, the local bit lines 20 form a matrix configuration on a plurality of global bit lines 10 .

The word line 30 shown in FIG. 2 includes: an extension portion 30d extending in the Y direction between adjacent local bit lines 20 in the X direction; and a common portion 30f electrically converging the plurality of extension portions 30d. In the X direction, the extending portions 30d of every other word line 30 are electrically converged by the common portion 30f. That is, in one layer of word lines 30 stacked in the Z direction, two word lines 30 a and 30 b electrically converging a plurality of extension portions 30 d are provided. A word line 30a is provided on one side in the X direction of each local bit line 20, and a word line 30b is provided on the other side.

In this specification, word lines 30 a and 30 b are collectively referred to as word lines 30 . In addition, among other constituent elements, the case where the same element is distinguished by another symbol and the case where the same element is collectively referred to by one symbol.

Two word lines 30 a and 30 b among the plurality of word lines 30 face each other across the local bit line 20 . Between the word line 30a and the local bit line 20, a first storage layer 40a is provided. In addition, a second memory layer 40b is provided between the word line 30b and the local bit line 20 .

Memory cells MC are respectively formed at portions where local bit lines 20 and word lines 30 intersect. That is, each memory cell MC includes either the first memory layer 40a or the second memory layer 40b.

Furthermore, as shown in FIG. 2 , the gate electrode 53 of the selection element 50 extends in the Y direction in the lower layer of the word line 30 . In addition, the gate electrode 53 extends along the Y direction between the plurality of conductive parts 51 connected to the local bit line 20 .

FIG. 3 is an example of a block diagram showing the nonvolatile memory device 100 of the first embodiment. The nonvolatile memory device 100 includes, for example, a row decoder 15 and a sense amplifier 17 that drive the memory cell array 1 . Sense amplifier 17 can discriminate and temporarily store data read from memory cell MC. Furthermore, the nonvolatile memory device 100 includes a control circuit 13 and an interface circuit 19 . The control circuit 13 records information in the memory cell array 1 via the row decoder 15 and the sense amplifier 17 and reads information from the memory cell array 1 in accordance with instructions received from the outside via the interface circuit 19 .

For example, the control circuit 13 selects one of the plurality of global bit lines 10 via the sense amplifier 17 . In addition, the control circuit 13 selects one of the plurality of local bit lines 20 provided on the selected global bit line 10 via the row decoder 15 . Specifically, a gate bias voltage is applied to the gate electrode 53 of the selection element 50 provided between the selected global bit line 10 and the local bit line 20 to be selected, and the two are electrically conducted.

Also, the control circuit 13 selects one of the plurality of memory cells MC disposed between the selected local bit line 20 and the word line 30 by specifying one of the plurality of word lines 30 . Specifically, the word line 30a or 30b of the hierarchy in which the memory cell MC is provided is designated.

For example, when reading information recorded in a memory cell MC, the control circuit 13 applies a voltage to a designated word line 30 , and the sense amplifier 17 detects a current flowing to a selected global bit line 10 . Then, based on the output from the sense amplifier 17 , the information to be recorded in the memory cell MC is identified and output via the interface circuit 19 . In addition, when writing (setting) information to the memory cell MC or deleting (resetting) the information recorded in the memory cell MC, a predetermined voltage is applied to the designated word line 30 to change the impedance of the MC from the first state to Transition to the second state or vice versa.

FIG. 4 is an example of a cross-sectional view schematically showing the memory cell array 1 of the first embodiment. FIG. 4 shows a section along line A-A shown in FIG. 2 .

As shown in FIG. 4 , a selection element 50 is provided on the global bit line 10 . The selection element 50 has: a conductive portion 51 ; a gate electrode 53 facing a side thereof; and a gate insulating film 55 provided between the conductive portion 51 and the gate electrode 53 .

The conductive portion 51 has a channel portion 57 and source and drain portions 58 and 59 provided above and below it. The channel portion 57 faces the gate electrode 53 with the gate insulating film 55 interposed therebetween. The source-drain portion 58 is connected to the global bit line 10 . On the other hand, the source-drain portion 59 is connected to the local bit line 20 .

Between the global bit line 10 and the gate electrode 53, an insulating layer 61 is provided. In addition, on the gate electrode 53, an insulating layer 63 is provided. For the insulating layers 61 and 63, silicon oxide films can be used, for example.

On the selection element 50, a local bit line 20 and a plurality of word lines 30 are provided. A plurality of word lines 30 are stacked in the Z direction with insulating layers 33 interposed therebetween. In addition, in the X direction, word lines 30 a and word lines 30 b are arranged alternately between adjacent local bit lines 20 .

A first storage layer 40a is provided between the local bit line 20 and the word line 30a. In addition, a second memory layer 40b is provided between the local bit line 20 and the word line 30b.

As shown in FIG. 4, the local bit line 20 has a first portion 21 connected to the first memory layer 40a and a second portion 23 connected to the second memory layer 40b, and has a block portion 25 therebetween.

5A and 5B are schematic diagrams of a memory cell array 2 of a comparative example. FIG. 5A is a partial cross-sectional view of the memory cell array 2, and FIG. 5B is an energy band diagram in the cross-section.

As shown in FIG. 5A , the block portion 25 is not provided in the memory cell array 2 . A memory cell MC1 including a first memory layer 40a is provided between the local bit line 20 and the word line 30a. A memory cell MC2 including a second memory layer 40b is provided between the local bit line 20 and the word line 30b.

As shown in FIG. 5A , the control circuit 13 applies different voltages to the opposite word lines 30 a and 30 b across the local bit line 20 . When memory cell MC2 is reset, for example, the potential of local bit line 20 is set to 3V, the potential of word line 30a is set to 2V, and the potential of word line 30b is set to 1V. That is, a potential difference of 1V is applied to the memory cell MC1, and a potential difference of 2V is applied to the memory cell MC2.

The thickness of the storage layer 40 is, for example, several nm, and a strong electric field on the order of 106 V/cm is generated inside the storage layer 40 . Accordingly, the reset current IR flows to MC2, and the second memory layer 40b transitions from, for example, the second state (low impedance) to the first state (high impedance). On the other hand, the voltage applied to MC1 is half that of MC2, and the current flowing to the first storage layer 40a is smaller than the reset current IR. Therefore, the impedance state of the first storage layer 40a does not transition.

5B shows an energy band diagram when the potential difference applied between the local bit line 20 and the word line 30a is set to 1V, and the potential difference applied between the local bit line 20 and the word line 30b is set to 2V. The horizontal line Ec in the figure represents the energy level of the conduction band in the local bit line 20, word lines 30a and 30b.

For example, when the reset current IR flows from the local bit line 20 to the word line 30b, electrons eA and eB, which are current carriers, move from the word line 30b to the local bit line 20 through the second memory layer 40b. Most of the electrons eA flowing from the word line 30b into the local bit line 20 are scattered in the local bit line 20 and lose kinetic energy.

However, when the width of the local bit line 20 in the X direction is, for example, 40 nm, some electrons may pass through the local bit line 20 and flow into the memory cell MC1 without being scattered. These electrons e _B may undesirably migrate to the impedance state of the first storage layer 40a, thereby changing the storage content of the memory cell MC1. Such a phenomenon occurs more accurately when the width of the local bit line 20 is narrower. A bad mode known as crosstalk between memory cells degrades the reliability of the nonvolatile memory device.

In this embodiment, block portion 25 is provided inside local bit line 20 to suppress movement of carriers (electrons or holes) between memory cell MC1 and memory cell MC2 . Thus, the reliability of the nonvolatile memory device 100 can be improved.

6A and 6B are examples of schematic diagrams showing the memory cell array 1 of the first embodiment. 6A is a partial sectional view of the memory cell array 1, showing a specific example of the block portion 25 provided on the local bit line 20. As shown in FIG. FIG. 6B is an energy band diagram illustrating the effect of the block portion 25 shown in FIG. 6A .

As shown in FIG. 6A , the block unit 25 of this example includes an interface 43 connecting the first part 21 and the second part 23 . That is, the block part 25 is provided in the vicinity of the interface 43, which is a so-called seam. The interface 43 includes a local bend E _B of an energy band or a carrier trap E _T (trapping center) that traps carriers, or the like.

As shown in FIG. 6B , electrons e _B with high energy flow into the local bit line 20 from the word line 30 b through the second memory layer 40 b by the voltage applied between the local bit line 20 and the word line 30 b. Before the electrons e _B pass through the local bit line 20 and reach the first storage layer 40a, the movement in the X direction is restricted due to the energy band bending E _B , or are captured by the carrier trap _ET formed at the interface 43 . The density of the carrier traps _ET contained in the interface 43 is higher than, for example, the scattering centers of the first portion 21 and the second portion 23, and effectively suppresses electrons e _B flowing into the first storage layer 40a. Thus, malfunction of the memory cell MC1 can be prevented.

For example, the first portion 21 and the second portion 23 include a semiconductor material such as polysilicon. The interface 43 connecting the first portion 21 and the second portion 23 becomes a discontinuous surface of the semiconductor crystal, and includes a high-density carrier trap _ET .

Next, a manufacturing process of the memory cell array 1 will be described with reference to FIGS. 7 to 11B.

7 to 11B are examples of schematic diagrams showing the manufacturing process of the memory cell array of the first embodiment. 7, 8B, 9A-10B and 11B are partial cross-sectional views of the wafer. 8A and 11A are plan views showing the top surface of the wafer.

First, a wafer in which selection elements 50 are formed on global bit lines 10 is prepared. For example, on a silicon substrate on which peripheral circuits such as the control circuit 13, the row decoder 15, and the sense amplifier 17 are formed, the global bit line 10 is formed via an interlayer insulating film. A select element 50 is then formed on the global bit line 10 .

Next, as shown in FIG. 7 , a laminated body 60 is formed on the selection element 50 . The laminated body 60 includes a plurality of insulating layers 33 and a plurality of conductive layers 31 . The insulating layer 33 is, for example, a silicon oxide film formed by a CVD (Chemical Vapor Deposition: Chemical Vapor Deposition) method. The conductive layer 31 is, for example, a polysilicon film formed by CVD. The insulating layer 33 and the conductive layer 31 are alternately laminated in the Z direction.

Next, as shown in FIGS. 8A and 8B , the laminated body 60 is selectively etched to form slits 65 . The laminated body 60 is etched using, for example, RIE (Reactive Ion Etching: Reactive Ion Etching). An etching mask (not shown) is provided on the laminated body 60 .

As in FIG. 8A , the slit 65 is formed to extend in the Y direction. In addition, the slit 65 is formed to a depth from the top surface of the laminated body 60 to the selection element 50 . The source drain portion 59 of the conductive portion 51 is exposed on the bottom surface of the slit 65 .

Next, as shown in FIG. 9A , the memory layer 40 is formed on the inner surface of the slit 65 . The memory layer 40 includes a variable resistance material, and is formed, for example, by an ALD (Atomic Layer Deposition: Atomic Layer Deposition) method. The thickness of the storage layer 40 is, for example, several nm.

Next, as shown in FIG. 9B , the memory layer 40 formed on the bottom surface of the slit 65 is selectively removed to expose the source and drain portions 59 . For example, by using the anisotropic etching conditions of RIE, the storage layer 40 formed on the sidewall of the slit 65 can be left, and the storage layer 40 formed on the bottom surface can be selectively removed.

Next, as shown in FIG. 10A , a conductive layer 67 is formed on the inner surface of the slit 65 . The conductive layer 67 is, for example, a metal film or a polysilicon film. For the formation of the conductive layer 67 , it is preferable to employ a film-forming method with good isotropy, such as ALD method or CVD method. The conductive layer 67 is deposited laterally (X direction and −X direction) on the memory layer 40 formed on the sidewall of the slit 65 . If the film growth is isotropic, the conductive layer 67 can be uniformly formed on the side walls of the slit 65 with a uniform thickness.

As shown in FIG. 10B , by continuously accumulating conductive layers 67 , the gaps in the slits 65 are filled. The conductive layers 67 deposited on both side walls of the slit 65 are connected at the center of the slit 65 to form a joint surface (seam) extending in the Z direction or a discontinuous surface of the crystal. In this discontinuous surface, movement of electrons in the X direction is restricted due to bending of the energy band. In addition, the joint and/or the discontinuous surface may contain high-density crystal defects. This crystal defect functions as a trapping center for carriers.

Next, as shown in FIGS. 11A and 11B , the conductive layer 67 is selectively etched to separate a plurality of local bit lines 20 .

As shown in FIG. 11A , the conductive layer 67 extending in the Y direction is separated by the insulator 38 to form a plurality of local bit lines. Specifically, in the portion where the insulator 38 is formed, the conductive layer 67 is formed at a depth from the top surface thereof to the insulating layer 63 . The insulating layer 63 is provided so as to be buried between adjacent selection elements 50 in the Y direction.

That is, as shown in FIG. 11B , the conductive layer 67 is removed except for the portion connected to the source-drain portion 59 of the selection element 50 . Next, in order to form the insulator 38, a silicon oxide film, for example, is buried in the gap where the conductive layer 67 is removed.

In the memory cell array 1 formed through the above-described manufacturing process, the interface 43 is formed inside the local bit line 20 . As shown in FIGS. 11A and 11B , the interface 43 extends in the Y direction and the Z direction, and separates the local bit line 20 into a first part 21 and a second part 23 .

On the other hand, the local bit line 20 includes a part of the conductive layer 67 deposited on the source-drain portion 59 in the portion connected to the source-drain portion 59 . Therefore, the interface 43 does not extend to the end 20 e of the local bit line 20 on the side of the global bit line 10 . Here, in order to suppress crosstalk between memory cells MC3 and MC4 formed closest to global bit line 10 , end 43 e of interface 43 is preferably located below word line 30 e formed closest to global bit line 10 . This can be achieved by forming the insulating layer 33 e formed on the selection element 50 thicker than the conductive layer 67 deposited on the source-drain portion 59 .

Referring to FIG. 4 , this condition is in other words, it is preferable to make the distance (W _B ) between the end 25e of the block portion 25 on the global bit line 10 side and the end 20e of the local bit line 20 be greater than that of the plurality of word lines 30 closest to the global bit line. The distance (W _L2 ) between word line 30e of line 10 and end 20e of local bit line 20 is narrow.

In addition, as shown in FIG. 11C , the film thickness of the lowermost insulating film 30eb may be thicker than that of the other insulating films 33e. That is, as the width of the slit 65 becomes narrower, the interval W _B becomes larger. However, if the film thickness of the entire insulating film 30e is increased, the height of the slit 65 becomes too high. Therefore, by increasing the film thickness of the lowermost insulating film 30eb, the interval W _L2 is increased (W _L1 <W _L2 ). Therefore, even if the width of the slit 65 is narrow, the relationship of interval W _B < interval W _L2 can be maintained.

It can also be said that in the above structure, the distance between the bottom surface of the word line 30e and the end 20e of the local bit line 20 is wider than the distance between two adjacent word lines 30 in the Z direction among the word lines 30 stacked in the Z direction.

FIG. 12 is an example of a cross-sectional view schematically showing a memory cell array 3 according to a modified example of the first embodiment.

In the memory cell array 3 , the block portion 25 includes a block layer 45 provided between the first portion 21 and the second portion 23 . Specifically, the first part 21 and the second part 23 contain the first metal. The block layer 45 includes a second metal having a smaller work function than the first metal. The first metal is, for example, tantalum nitride (TaN), and the second metal is, for example, tungsten (W).

Accordingly, potential barriers are formed between the first portion 21 and the block layer 45 and between the second portion 23 and the block layer 45 . For example, electrons e _B injected from the word line 30b to the local bit line 20 through the second storage layer 40b can be prevented from flowing into the first storage layer 40a. In addition, electrons flowing from the word line 30a to the local bit line 20 through the first memory layer 40a can be prevented from being injected into the second memory layer 40a.

In addition, as another example, the first portion 21 and the second portion 23 may include a first semiconductor, and the block layer 45 may include a second semiconductor having a wider band gap than the first semiconductor. For example, the first semiconductor may be silicon, and the second semiconductor may be gallium arsenide (GaAs) or gallium nitride (GaN). That is, the discontinuity of the energy band between the first semiconductor and the second semiconductor acts as a potential barrier, thereby obtaining an effect of inhibiting the movement of carriers in the X direction within the local bit line 20 .

13A to 13C are examples of schematic diagrams showing memory cell array 4 according to other modified examples of the first embodiment. FIG. 13A is a partial cross-sectional view showing the memory cell array 4. As shown in FIG. 13B and 13C show the impurity profile of the local bit line 20 .

In the memory cell array 4, the local bit line 20 includes a semiconductor. The impurity concentration of the block portion 25 is lower than that of the first portion 21 . In addition, the impurity concentration of the bulk portion 25 is lower than the impurity concentration of the second portion 23 . Therefore, between the bulk portion 25 and the first portion 21 and between the bulk portion 25 and the second portion, a potential barrier is formed due to the concentration difference. The block portion 25 suppresses movement of carriers in the X direction within the local bit line 20 .

As shown in FIG. 13B , the impurity distribution in the local bit line 20 is formed such that it decreases continuously toward the center from the side of the first memory layer 40 a and the side of the second memory layer 40 b . That is, when the conductive layer 67 is deposited (see FIGS. 10A and 10B ), the doping amount of impurities increases in the first half and decreases in the second half.

In addition, as shown in FIG. 13C , the impurity distribution in the local bit line 20 may also be formed in a manner of decreasing in steps in the block portion 25 . The local bit line 20 comprises, for example, polysilicon. Impurities doped with the local bit line 20 are, for example, arsenic (As), phosphorus (P) or boron (B).

[Second embodiment]

FIG. 14 is an example of a cross-sectional view schematically showing the memory cell array 5 of the second embodiment.

As shown in FIG. 14, in the memory cell array 5, the local bit line 20 has a gap 47 between the first portion 21 connected to the first memory layer 40a and the second portion 23 connected to the second memory layer 40b. For example, in the process shown in FIG. 10A , the deposition is stopped before the conductive layers 67 deposited on both side walls of the slit 65 are connected in the X direction. Therefore, a gap can remain between the first part 21 and the second part 23 .

The gap 47 extends in the Z direction in the local bit line 20 . The gap 47 prevents carriers flowing from one of the word lines 30a and 30b to the local bit line 20 through the storage layer 40 from moving to the other of the word lines 30a and 30b. Accordingly, crosstalk between memory cells facing each other across the local bit line 20 can be suppressed.

In addition, the interval W _B between the end 47e of the gap 47 on the global bit line 10 side and the end 20e of the local bit line on the global bit line 10 side is preferably larger than the word line 30e closest to the global bit line 10 among the plurality of word lines 30 and The interval WL of the end _20e of the local bit line 20 is narrow. Accordingly, crosstalk between memory cells MC3 and MC4 formed at positions closest to global bit line 10 can be suppressed.

In addition, the film thickness of the lowermost insulating film 30eb may be thicker than the film thickness of the other insulating films 33e. That is, as the width of the slit 65 becomes narrower, the interval W _B becomes larger. However, if the film thickness of the entire insulating film 30e is increased, the height of the slit 65 becomes too high. Therefore, by increasing the film thickness of the lowermost insulating film 30eb, the interval W _L2 is increased (W _L1 <W _L2 ). Therefore, even if the width of the slit 65 is narrow, the relationship of interval W _B < interval W _L2 can be maintained.

It can also be said that in the above structure, the distance between the bottom surface of the word line 30e and the end 20e of the local bit line 20 is wider than the distance between two adjacent word lines 30 in the Z direction among the word lines 30 stacked in the Z direction.

[third embodiment]

FIG. 15 is an example of a cross-sectional view schematically showing the memory cell array 6 of the nonvolatile memory device 200 of the third embodiment.

The nonvolatile memory device 200 has a so-called vertical cross-point structure, and the local bit line 20 is directly connected to the global bit line 10 . Between the local bit line 20 and the word line 30 a rectifying element, such as a diode, is arranged.

As shown in FIG. 15 , in the memory cell array 6 , the global bit line 10 is directly connected to the local bit line 20 . A plurality of word lines 30 are arranged side by side on both sides of the local bit line 20 . In addition, in this example, the word line 30 arranged between adjacent local bit lines 20 in the X direction faces any one of the local bit lines 20 via the memory layer 40 . The storage layer 40 includes a variable resistance layer 42 provided on the side of the word line 30 and a rectifying layer 71 connected to the local bit line 20 .

The word line 30a and the word line 30b shown in FIG. 15 face each other across the local bit line 20 in the X direction. A first storage layer 40a is provided between the local bit line 20 and the word line 30a. In addition, a second memory layer 40b is provided between the local bit line 20 and the word line 30b.

The first memory layer 40a has a first rectifying layer 71a at a portion connected to the local bit line 20 . In addition, the second memory layer 40b has a second rectifying layer 71b at a portion connected to the local bit line 20 .

The first rectifying layer 71 a interposes a first diode between the first storage layer 40 a and the local bit line 20 . The second rectifying layer 71 b interposes a second diode between the second storage layer 40 b and the local bit line 20 .

For example, when the local bit line 20 contains metal, the rectifying layer 71 contains a semiconductor. Therefore, a Schottky diode can be interposed between the local bit line 20 and the storage layer 40 . In addition, when the local bit line 20 includes a semiconductor, the rectifying layer 71 includes a semiconductor whose conductivity type is different from that of the local bit line 20 . Therefore, a PN junction diode can be inserted between the local bit line 20 and the storage layer 40 .

In this embodiment, the local bit line 20 also has a first portion 21 connected to the first storage layer 40a and a second portion 23 connected to the second storage layer 40b, with a block portion 25 therebetween. The block portion 25 prevents carriers flowing from one of the word lines 30a and 30b to the local bit line 20 through the memory layer 40 from moving to the other. Accordingly, crosstalk between memory cells facing each other across the local bit line 20 can be suppressed. The block portion 25 has the same structure as that of the first embodiment. In addition, a gap 47 may be provided between the first part 21 and the second part 23 .

While several embodiments of the invention have been described, these embodiments are illustrative only and do not limit the scope of the invention. These new embodiments can be implemented in various forms, and various omissions, substitutions, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are also included in the invention described in the scope of claims and their equivalents.

Claims (19)

1. A non-volatile memory device, characterized in that it possesses: a first wiring extending in a first direction; a second wiring extending in a second direction perpendicular to the first direction and electrically connected to the first wiring; A plurality of third wirings each extending in a third direction intersecting the first direction and perpendicular to the second direction, and arranged side by side along the second direction on both sides of the second wiring; The first storage layer is provided between one of the two third wirings facing each other across the second wiring and the second wiring among the plurality of third wirings; The second storage layer is provided between the other of the two third wirings and the second wiring, The second wiring has a block portion between a first portion connected to the first memory layer and a second portion connected to the second memory layer. 2. The non-volatile memory device according to claim 1, wherein: The block part includes an interface connecting the first part and the second part. 3. The non-volatile memory device of claim 2, wherein: the above-mentioned part 1 and the above-mentioned part 2 comprise semiconductor materials, The above-mentioned interface is a discontinuous surface of the semiconductor crystal. 4. The non-volatile memory device of claim 2, wherein: The block portion includes carrier traps at the interface. 5. The non-volatile memory device of claim 1, wherein: The above-mentioned first part and the above-mentioned second part contain the first metal, The bulk portion includes a second metal having a work function smaller than that of the first metal. 6. The non-volatile memory device according to claim 5, wherein: The above-mentioned first metal is tantalum nitride (TaN), The above-mentioned second metal is tungsten (W). 7. The non-volatile memory device of claim 1, wherein: The second wiring includes a semiconductor, The impurity concentration of the block portion is lower than that of the first portion and the second portion. 8. The non-volatile memory device of claim 7, wherein: The second wiring includes polysilicon. 9. The non-volatile memory device of claim 1, wherein: the first part and the second part include the first semiconductor, The bulk portion includes a second semiconductor having a wider bandgap than the first semiconductor. 10. The non-volatile memory device of claim 1, wherein: The first storage layer and the second storage layer include a resistance variable material that reversibly transitions between a first state and a second state having lower impedance than the first state. 11. The non-volatile memory device of claim 1, wherein: further comprising a plurality of second wirings arranged side by side in the above-mentioned first direction, One of the two third wirings has: a plurality of first extensions extending along the third direction between the second wirings arranged side by side in the first direction; and a first extension that electrically converges the plurality of first extensions. 1 shared part, The other of the two third wirings has: a plurality of second extensions extending along the third direction between the plurality of second wirings; a second common portion electrically converging the plurality of second extensions, One of the plurality of first extensions and one of the plurality of second extensions are provided on both sides of each of the second wirings, One of the plurality of first extensions and one of the plurality of second extensions face each other across the second wiring. 12. The non-volatile memory device of claim 1, wherein: further comprising a plurality of third wirings stacked in the above-mentioned second direction, The block portion extends in the second wiring along the second direction, The distance between the end of the block part on the side of the first wiring and the end of the second wiring on the side of the first wiring is greater than the distance between the third wiring closest to the first wiring and the third wiring closest to the first wiring among the third wirings stacked in the second direction. The distance between the ends of the second wiring is narrow. 13. The non-volatile memory device of claim 12, wherein: Among the third wirings stacked in the second direction, the distance between the bottom surface of the third wiring closest to the first wiring and the end of the second wiring is larger than that of the second wiring among the third wirings stacked in the second direction. The distance between two third wirings adjacent in the direction is wide. 14. The non-volatile memory device of claim 1, wherein: The first storage layer has a first rectifying layer at a portion connected to the second wiring, The second memory layer has a second rectifying layer at a portion connected to the second wiring. 15. The non-volatile memory device of claim 14, wherein: The first rectifying layer interposes a first diode between the first storage layer and the second wiring, In the second rectifying layer, a second diode is interposed between the second memory layer and the second wiring. 16. A non-volatile storage device, characterized in that it has: a first wiring extending in a first direction; a second wiring extending in a second direction perpendicular to the first direction and electrically connected to the first wiring; A plurality of third wirings each extending in a third direction intersecting the first direction and perpendicular to the second direction, and arranged side by side along the second direction on both sides of the second wiring; The first storage layer is provided between one of the two third wirings facing each other across the second wiring and the second wiring among the plurality of third wirings; The second storage layer is provided between the other of the two third wirings and the second wiring, and the second wiring is between the first part connected to the first storage layer and the second storage layer connected to the second storage layer. There is a gap between the 2 parts. 17. The non-volatile memory device of claim 16, wherein: The first storage layer and the second storage layer include a resistance variable material that reversibly transitions between a first state and a second state having lower impedance than the first state. 18. The non-volatile memory device of claim 16, wherein: further comprising a plurality of third wirings stacked in the above-mentioned second direction, The gap extends in the second wiring along the second direction, The distance between the end of the gap on the side of the first wiring and the end of the second wiring on the side of the first wiring is greater than the distance between the third wiring closest to the first wiring and the end of the third wiring stacked in the second direction. The distance between the ends of the second wiring is narrow. 19. The non-volatile memory device of claim 18, wherein: Among the third wirings stacked in the second direction, the distance between the bottom surface of the third wiring closest to the first wiring and the end of the second wiring is larger than that of the third wiring stacked in the second direction. The interval between two adjacent third wirings in the two directions is wide.