CN104268253B - A kind of part triplication redundancy method counted based on look-up table configuration bit - Google Patents

Abstract

A partial three-mode redundancy method based on lookup table configuration bit statistics of the present invention includes step S1: mapping the circuit to be redundant into a k-input lookup table format, reading information on the circuit to be redundant, and establishing a circuit topology database ; Step S2: Perform statistics on the circuit topology information, and record the irrelevant configuration bit information of each node in the circuit to be redundant; Step S3: Obtain the single event effect sensitivity information of the lookup table according to the number of irrelevant configuration bits; S4: Extract the single event upset-sensitive lookup table from the single event effect sensitivity information of the lookup table, and perform three-mode redundancy processing on the single event upset-sensitive lookup table, and obtain and perform redundancy in each redundancy according to the redundancy result. A voter is inserted between the redundant module and the non-redundant module to construct a partial triple-mode redundant circuit with the ability to resist single event effects. The invention can greatly improve the reliability of the system, and can save about half of the hardware overhead of the full three-mode redundant circuit.

Description

A Partial Triple-Mode Redundancy Method Based on Lookup Table Configuration Bit Statistics

technical field

The invention relates to the technical field of digital system fault tolerance, in particular to a method for reducing hardware overhead in the triple-mode redundancy technology of programmable devices.

technical background

Programmable device (FPGA) has the characteristics of short development cycle, low cost, and high flexibility, so it is widely used in electronic system design. The FPGA chip based on static random access memory (SRAM) configuration depends entirely on internal configuration data. , according to the existing literature and in-orbit flight data, SRAM-type FPGA devices are mainly susceptible to Single Event Upset (SEU) in the space radiation environment, so the design of SRAM-based FPGA systems should focus on SEU protection.

FIG. 1a is a schematic diagram of a circuit to be redundant, and FIG. 1b is a schematic diagram of a full triple-mode redundant circuit. The circuit to be redundant as shown in Figure 1a includes modules M1, M2, M3, the circuit to be redundant is a digital circuit of binary logic, and the result output by the circuit modules to be redundant M1, M2, M3 is logic "0" ” or logic “1”. The module M1 receives multiple logic signals input from the outside, the module M1 outputs multiple first logic signals, the module M2 receives multiple first logic signals, and the multiple second logic signals output by the module M2 are transmitted to the module M3, and the module M3 The output is a plurality of third logic signals of the circuit to be redundant. The circuit after full triple-mode redundancy of the redundant circuit to be redundant is shown in Figure 1b, that is, the entire redundant circuit in Figure 1a is copied twice to form a parallel structure of three branches composed of three modules M1, M2, and M3. Wherein each module M3 respectively outputs a plurality of third logic signals, the same total number of voters V is set according to the total number of third logic signals output by the three modules M3, and the voters V respectively receive the total number of third logic signals output by the three modules M3 , each voter V votes on the third logic signal output by the three modules M3 according to the principle of "minority obeys the majority", and judges that the third logic signal is all the same logic value, and judges that the third logic signal is two The same logic value, so when a redundant module is overturned, the voter V can still output the correct result.

Triple-mode redundancy is currently the most commonly used fault-tolerant technology, and it is widely used in space systems due to its reliability. This method replicates the original circuit three times, and when an error occurs in one of the circuits, the correct result can be output by comparison. When the two modules fail at the same time, the voting device will not be able to judge the correct result. Therefore, the triple-mode redundancy technology for SRAM FPGA is generally used in conjunction with the timing refresh technology, which can effectively ensure the safe and stable operation of the system.

However, the three-mode redundant technology has the problem of excessive circuit overhead. The complete three-mode redundant circuit will cause the circuit overhead to reach 200% or more before redundancy, and the specific application should minimize the power and volume constraints hardware overhead. In view of the sensitivity of different parts of the circuit to the single event effect, selectively performing part of the triple-mode redundancy on the circuit components can appropriately reduce the overhead. Part of the triple-mode redundancy technology is at the expense of circuit reliability, and the hardware overhead is saved accordingly. ground will result in reduced reliability. How to make trade-offs to the circuit is a problem to be considered in some triple-mode redundant designs.

Those skilled in the art have proposed the concept of sensitive gates to save circuit overhead by only redundant sensitive gates. This method first sets an input probability for the original input of the circuit based on empirical values, and then calculates the input of each gate according to the circuit topology. Probabilities, combined with the control value properties of the gates, define each gate as either sev-sensitive or sing-insensitive. The single event event-sensitive gate is redundantly inserted into the voter and then combined with the single event event-insensitive gate to form the original circuit function, and then mapped to a look-up table structure by the FPGA synthesis tool.

Since the sensitivity of the prior art is calculated according to the gate-level circuit structure and input probability, the effect of fault tolerance and overhead saving will be greatly reduced after it is mapped to the FPGA structure based on the look-up table.

Contents of the invention

(1) Solved technical problems

In order to solve the problems in the prior art, the purpose of the present invention is to find a partial triple-mode redundancy method that can directly operate on the look-up table circuit model and does not depend on the circuit input, which has very far-reaching significance.

(2) Technical solution

The present invention provides a kind of partial three-mode redundancy method based on lookup table configuration bit statistics, comprising the following steps:

Step S1: mapping the circuit to be redundant into a k-input lookup table format, reading information on the circuit to be redundant, and establishing a circuit topology database, the lookup table being a lookup table in the FPGA;

Step S2: Counting the circuit topology information in the circuit topology database, and recording the irrelevant configuration bit information of each node in the redundant circuit in the circuit topology database;

Step S3: Obtain the single event effect sensitivity information of the lookup table according to the number of irrelevant configuration bits;

Step S4: Extract the single event upset-sensitive lookup table from the single event effect sensitivity information of the lookup table, and perform three-mode redundancy processing on the single event upset-sensitive lookup table, and obtain and use the redundant results in each A voter is inserted between the redundant module and the non-redundant module to construct a partial three-mode redundant circuit with the ability to resist single event effects.

(3) Beneficial effects

After adopting the above technical solutions, the present invention has the following advantages compared with the prior art: 1) Since the present invention performs triple-mode redundancy on the single event reversal-sensitive lookup table in the circuit, it can effectively improve the ability of the circuit to resist single event effects, Extend the mean time between failures of the circuit. 2) compared with the full three-mode redundancy fault-tolerant method of the present invention, the present invention selects the look-up table that needs to carry out triple-mode redundancy by calculating the irrelevant configuration bits of the look-up table. To a certain extent, the reliability of the SRAM FPGA circuit can be guaranteed, which can greatly save the circuit cost. 3) The window method adopted in the present invention can obtain most of the irrelevant configuration bits of the look-up table in a relatively short period of time, and the resulting set is a subset of the irrelevant configuration bits set of the entire circuit, that is, the exact lower part of the irrelevant configuration bits of the entire circuit. boundary.

Description of drawings

Figure 1a and Figure 1b are schematic diagrams of the circuit to be redundant and the full three-mode redundant circuit;

Fig. 2 is the flow chart of the present invention based on the partial three-mode redundancy method of look-up table configuration bit statistics;

Fig. 3 realizes a kind of partial three-mode redundant circuit structural diagram for the inventive method;

Fig. 4 is to be redundant circuit look-up table level circuit structural diagram;

Fig. 5 is the circuit structure diagram of the look-up table level after the partial redundancy of the embodiment used by the present invention;

Fig. 6 is the working flow diagram of the used lookup table irrelevant configuration bit calculation method of the present invention;

Fig. 7 is a flow chart of the window division method used in the present invention;

Fig. 8 is a schematic diagram of the window division method used in the present invention;

Fig. 9 is the flow chart of the irrelevant configuration bit search method used in the present invention;

Fig. 10 is a flow chart of the single event event simulation method provided by the present invention.

detailed description

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be described in further detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

The partial triple-mode redundancy method of the present invention defines a single event reversal-sensitive lookup table and a single event reversal-insensitive lookup table according to the number of irrelevant configuration bits of the lookup table, and only redundant single event reversal-sensitive lookup tables are used. The partially triple-redundant system includes a triple-redundant part and a non-triple-redundant part, wherein: the triple-redundant part duplicates the single-event flip-sensitive look-up table in the circuit and inserts a majority at the output The voter is formed; the non-three-mode redundant part is composed of single event flip-insensitive lookup table in the circuit; the connection between the three-mode redundant part and the non-three-mode redundant part maintains the topology of the original circuit, and the designed part three The modular redundant circuit can keep the function of the original circuit unchanged.

Figure 2 shows the flow chart of the present invention's partial triple-mode redundancy method based on look-up table configuration bit statistics, using this method to carry out the operation of the partial triple-mode redundancy embodiment of the FPGA circuit includes the following steps: Step S1: use the U.S. The tool RASP provided by the University of California, Los Angeles maps the circuit to be redundant into a k-input lookup table format, reads the information of the circuit to be redundant, and establishes a circuit topology database. The lookup table is a resource in the FPGA. For implementing combinational logic and sequential logic. Step S2: Count the circuit topology information in the circuit topology database, and record the irrelevant configuration bit information of each node in the redundant circuit in the circuit topology database; divide the nodes according to the circuit topology, and obtain the node window, Then judge whether to calculate the irrelevant configuration bit according to the node window information. If the number of leaf nodes in the window is less than the maximum value Lmax of the leaf node, calculate the number of irrelevant configuration bits of the node and record it; if the number of leaf nodes in the window is not When it is less than the maximum value Lmax, the number of irrelevant configuration bits of the node is recorded as 0. The calculation method for the number of node-independent configuration bits is as follows: use the exhaustive method to generate a test set for the window, apply the exhaustive test set to the leaf nodes of the window and flip each configuration bit of the node one by one, and observe whether the output of the root node of the window changes; if Flip a configuration bit and traverse the entire exhaustive test set, and the output of the root node of the window does not change, then the configuration bit is an irrelevant configuration bit of the node. Step S3: Obtain the single event effect sensitivity information of the lookup table according to the recorded number of irrelevant configuration bits. This method first sets a threshold value H of the irrelevant configuration bits of the lookup table. When the number of irrelevant configuration bits of a certain lookup table is higher than When the lookup table has nothing to do with the configuration bit threshold H, it can be judged that the lookup table is a single event flip-insensitive lookup table. When the number of irrelevant configuration bits of a certain lookup table is not higher than the lookup table. The lookup table is a single event upset-sensitive lookup table. The setting of the threshold needs to be comprehensively considered according to the specific application. The higher the reliability requirements of the redundant circuit, the greater the threshold H should be. P represents the probability of failure of the redundant circuit after being hit by a single event event, and Nc represents For the number of configuration bits in the lookup table, the method adopts the formula H=10*(P-0.9)*Nc to calculate the irrelevant configuration bit threshold of the lookup table. When three-mode redundancy is performed on the circuit to be redundant, only the single event flip-sensitive lookup table is redundantly processed. Step S4: Partial triple-mode redundant circuit construction, extract single event upset-sensitive lookup table from the single event effect sensitivity information of the lookup table, and perform triple-mode redundancy processing on the single event upset-sensitive lookup table, to obtain And according to the redundancy result, a voter is inserted between each redundant module and non-redundant module, and a partial triple-mode redundant circuit with anti-single event effect capability is constructed.

As shown in Figure 3, use a kind of part three-mode redundant circuit that the inventive method realizes; Suppose existing results show that in the three modules in the redundant circuit, only module M1 is easily affected by the single event effect and breaks down, and Module M2 and module M3 are not sensitive to single event effects, so only module M1 can be selectively redundant.

In view of the above setting, Fig. 3 shows part of the three-mode redundant circuit of the present invention, including three modules M1, one module M2, one module M3 and one voter V, and the three modules M1 are the first module M1 and the second module M1 , the third module M1, wherein: the input terminals of the first module M1, the second module M1, and the third module M1 receive external input logic signals, because the first module M1, the second module M1, and the third module M1 are Three-mode redundant signal, so the externally input multiple logic signals are fanned out into two copies and respectively input to the first module M1, the second module M1, and the third module M1 to generate and output redundant signals; the input terminal of the voter V is connected to the second module The output terminals of the first module M1, the second module M1, and the third module M1 are connected, and the voting device V votes on the redundant signals output by the first module M1, the second module M1, and the third module M1. The principle of "majority" always outputs the same value among the three. When only one module M1 circuit is overturned and the output is wrong, the voter V can still output the correct result through voting; the input terminal of the module M2 and the output of the voter V Since the module M2 is a single event reversal-insensitive lookup table, the module M2 is not easy to be overturned by the single event event and make an error; the input terminal of the module M3 is connected to the output terminal of the module M2, which is the same as the module M2, and the module M3 is not easy to be overturned by the single event event. If the event is overturned and an error occurs, the final result of the circuit will be output. As can be seen from the above structure, compared with the full three-mode redundant circuit, the part of the three-mode redundant circuit realized by the method of the present invention can save unnecessary expenses, according to the specific circuit to be redundant module Different, the number and position of the voters inserted are different, which will result in different circuit overhead saved.

Provide the application example of the present invention in concrete circuit below: present embodiment adopts 8 to select 1 multiplexer circuit cm152a, and this circuit is selected from the benchmark test circuit set (MCNC'91) that South Carolina Microelectronics Center provides, this The test circuit set contains multiple benchmark test circuits, and the 8-to-1 multiplexer circuit cm152a is one of the smaller test circuits.

Figure 4 shows the circuit structure diagram of the lookup table level of the circuit to be redundant. The circuit to be redundant is the circuit after cm152a is mapped to a 4-input lookup table structure using the RASP tool. The circuit to be redundant is composed of [15], [16], [ 9], [10], [2], p1 these six look-up tables form a three-level structure. The circuit to be redundant has 11 input signals including: 8 input signals pa, pb, pc, pd, pe, pf, pg, ph of the multiplexer, coded input signals pi, pj, pk, the to-be The redundant circuit has an output signal p1, and the circuit selects one of the eight input signals to be selected as the output signal by encoding the encoded values of the input signals pi, pj, and pk.

The first-level look-up table of the redundant circuit is [15], [16], [9], [10], and the look-up table [15] has 4 input terminals, which respectively receive the input signals pb and pf to be selected from the outside and coded input signals pj, pk; 1 output terminal, outputting the first intermediate signal. The look-up table [16] has 4 input terminals, which respectively receive the input signals pd, ph to be selected and the encoded input signals pj, pk from the outside; 1 output terminal, which outputs the second intermediate signal. The look-up table [9] has 4 input terminals, which respectively receive external input signals pa, pe and coded input signals pj, pk to be selected; 1 output terminal, which outputs the third intermediate signal. The look-up table [10] has 4 input terminals, which respectively receive external input signals pc, pg to be selected and coded input signals pj, pk; 1 output terminal, which outputs the fourth intermediate signal. The second-level look-up table of the redundant circuit is [2], and the look-up table [2] has three input terminals, which respectively receive the coded input signal pi from the outside and the first and the first of the look-up tables [15] and [16]. Two intermediate signals; one output terminal, which outputs the fifth intermediate signal.

The third-level look-up table of the redundant circuit is p1, and the look-up table p1 has four input terminals, which respectively receive the coded input signal pi from the outside and the fifth and the fifth of the look-up tables [2], [9], [10] 3. The fourth intermediate signal: 1 output terminal, which outputs the output signal p1 of the redundant circuit to the outside.

The circuit to be redundant is composed of k-input look-up tables, and the k inputs of each look-up table accept the output signal or the original input signal of the previous level look-up table, when one input terminal of one look-up table A is connected with another look-up table B When the output terminals are connected, B is said to be A's input lookup table.

As shown in Figure 5, the 8-choice 1 multiplexer circuit cm152a selective triple-mode redundant structure implemented by the method of the present invention, the selective triple-mode redundant structure circuit includes a non-redundant circuit part 51 and a triple-mode redundant circuit Part 52, wherein the triple-mode redundant circuit part 52 includes three redundant look-up tables [10](1), [10](2), [10](3) and a voter V. Use the method judgment result of the present invention as an example below to be that the look-up table [10] is a single-event reversal-sensitive look-up table, and all the other 5 are single-event reversal-insensitive look-up tables, then the method of the present invention will look-up table [10] The two copies are [10](2), [10](3), and at the same time, the input signals pc, pg, pj, and pk of the lookup table [10] also fan out two copies as the lookup table [10](2) , [10] (3) input signal, then form three look-up tables [10] (1), [10] (2), [10] (3) with the same function, each of them has an output terminal, outputting respectively The fourth intermediate signal (1), the fourth intermediate signal (2), and the fourth intermediate signal (3), these three output signals are voted by the voting device V and then used as input signals of the look-up table p1.

Still taking the above-mentioned 8-to-1 multiplexer circuit cm152a as an example, as shown in Figure 4, if the method of the present invention is used to determine the results, the look-up tables [2], [9], and [10] are all single-event reversal-sensitive look-up tables , the output ends of [2], [9], [10] are all connected with the input end of the lookup table p1, so according to the method of the present invention, the lookup tables [2], [9], [10] should be three-mode respectively Redundancy and voters are respectively inserted at the output ends of the lookup tables [2], [9], [10], and the output results of the three voters are used as input signals of the lookup table p1. In this way, after the three look-up tables [2], [9], and [10] are redundant, the circuit needs to add three additional look-up tables as voters. Considering that the output terminals of the lookup tables [2], [9], [10] are all connected to the input terminals of the lookup table p1, that is, the lookup tables [2], [9], [10] are all input lookup tables of the lookup table p1 table, if the lookup table p1 is also redundant and a voter is inserted at the output of the lookup table p1, the resources consumed by the circuit are the same as the way of inserting three voters, and the reliability of the circuit is better guaranteed. Therefore, when building The relationship between the circuit structure and the single event event sensitivity of the lookup table should be fully considered when designing part of the triple-mode redundant circuit. The strategy of the part three-mode redundant circuit building method used in the present invention is: also need to consider the specific structure of the redundant circuit when carrying out part three-mode redundant processing to described redundant circuit, when redundant single event flip-insensitive When the hardware overhead brought by the lookup table is the same as the hardware overhead brought by the insertion voter, the redundant single event flip-insensitive lookup table should be selected, and the three-mode redundancy of the single event flip-insensitive lookup table Remain. Whether a single event reversal-insensitive lookup table should be redundant can be judged as follows: when a single event reversal-insensitive lookup table has two or more input lookup tables, it is a single event reversal-sensitive lookup table When , the single event upset-insensitive lookup table should also perform triple redundancy.

As shown in Figure 6, it is the working flowchart of the irrelevant configuration bit calculation of the used lookup table of the present invention, and the calculation steps of the irrelevant configuration bit of the lookup table described in step S2 include as follows:

Step S221: Select a node according to the circuit node number.

Step S222: divide a window for the node according to the circuit topology, and the specific window division method will be described in FIG. 7 of the specification of the present invention.

Step S223: Determine whether the node window is divided successfully, if the node can divide the window, record the input of the window as a leaf node, and record the output as a root node, establish a database to record the window information of the node and enter step S224; if the node can not divide the window Enter step S226 successfully.

Step S224: Determine whether the number of leaf nodes in the window of the node is less than the preset maximum number of leaf nodes Lmax. Since this method uses full simulation in the window to find irrelevant configuration bits, the workload increases exponentially with the increase in the number of leaf nodes increase, when the number of leaf nodes is greater than the maximum value Lmax of the number of leaf nodes, enter step S226; when the number of leaf nodes is not greater than the maximum value Lmax of the number of leaf nodes, enter step S225. In this embodiment, the maximum value of the number of leaf nodes is Lmax=20.

Step S225: Carry out full simulation of the input space for the node with the window established to obtain the irrelevant configuration bit of the lookup table where the node is located. The specific method for obtaining the irrelevant configuration bit will be described in FIG. 8 of the present invention.

Step S226: For a node whose window cannot be established or the number of leaf nodes in the window is greater than the maximum number of leaf nodes Lmax, directly record the number of node-independent configuration bits as 0.

Step S227: establishing a database to record irrelevant configuration bit information of circuit nodes;

Step S228: Traverse the entire circuit to collect statistics on all node-independent configuration bit information, and return to step S221 until the statistics of all node-independent configuration bit information in the entire circuit are traversed, and this process ends.

As shown in Figure 7, it is a flow chart of the window division method used in the present invention, and the steps are as follows:

Step S21: Select a certain node i in the circuit.

Step S22: Determine whether the fan-out number of the selected node is greater than the preset maximum tolerable fan-out number Omax, if the fan-out number of the node exceeds the maximum tolerable fan-out number Omax, do not divide the window and enter step S23, If the fan-out number of the node does not exceed the maximum value Omax of the tolerable fan-out number, go to step S27.

The test set selected in this embodiment is the MCNC'91 test set. In the benchmark test circuits in the test set, several large circuits include a small number of multi-fanout nodes, and the fanout number of individual nodes is even as high as Dozens, considering that the possibility of fault propagation increases when the fan-out number of nodes increases, and too much fan-out often leads to a huge window, which cannot be operated in the later steps of this method, so if this step finds nodes If the fanout is greater than the maximum value Omax of the tolerable fanout number, the node will not be divided into windows, and it will be marked as node window division failure. In this embodiment, the maximum value of the tolerable fan-out number is Omax=50.

Step S23: Record the input sets of N levels before node i, and include them in the direct input set S_I1, record the outputs of M levels after node i, and include them in the direct fan-out output set S_O1.

Step S24: Record the last M+N level output sets of all nodes in the input set S_I1, and include them in the indirect fan-out set S_O2, record the first M+N level input sets of all nodes in the input set S_O1, and include them in the indirect input set S_I2.

Step S25: Calculate the intersection of the indirect fan-out set S_O2 and the indirect input set S_I2, which is recorded as the window-related node set S=S_O2^S_I2.

Step S26: Calculate the number of leaf nodes and the number of root nodes of the node i to be requested according to the fan-in and fan-out information of the set S, and return the window division success information. Among them, the leaf nodes are the fan-in nodes of all nodes in the window and do not belong to the set S, and the root node is the node that belongs to the set S and at least one of its fan-outs does not belong to the set S.

It should be noted in this step that the original input node in the set S should be recorded as a leaf node, and the original output node should be recorded as a root node. For details, refer to the function division of the pi node in this process embodiment.

Step S27: mark node i as failing in window division, and end the window division work of node i.

Below still introduce the specific operation of the window division method that this method adopts by 8 selecting 1 multiplexer cm152a benchmark circuit, for the sake of simplicity, this embodiment only describes the division method of the first-level window, i.e. the situation of M=N=1:

This embodiment divides the window for the 8-choice 1 multiplexer cm152a reference circuit node [2]. For the convenience of observation and understanding, the 8-choice 1 multiplexer cm152a4-input lookup table level circuit shown in Figure 4 is expressed as a directed The form of Directed acyclic graph (DAG), as shown in Figure 8, in which the input signals are still pa, pb, pc, pd, pe, pf, pg, ph and pi, pj, pk, as directed The leaf node of the acyclic graph; the output signal is still p1, as the root node of the directed acyclic graph, the first-level intermediate state lookup table [9], [10], [15], [16] in Figure 4 constitutes The first stage of the directed acyclic graph, the second stage intermediate state lookup table [2] constitutes the second stage of the directed acyclic graph, the third stage output lookup table p1 constitutes the second stage of the directed acyclic graph, in The leaf nodes, root nodes and intermediate state nodes in the directed acyclic graph are all represented by circles with node labels, the connection lines represent the connection state of each node, and the direction of the arrow is the data transmission direction of the circuit. Module 81 adopts this method to establish a window for node [2]. If the input end of a certain node a is the output end of another node b, then it is said that node b is the input node of node a, and node a is the output end of node b. output node. The input terminal of module 81 node [2] has input signal pi and nodes [15], [16], that is, the input nodes of node [2] are pi, [15], [16], and the output terminal is the input terminal of node p1 , that is, the output node of node [2] is p1, similarly, node [15] has 4 input nodes for input signals pb, pf, pj, pk and one output node for node [2], node [16] has 4 There are four input nodes as input signals pd, ph, pj, pk and one output node as node [2], node [9] has 4 input nodes as input signals pa, pe, pj, pk and one output node as node [2] ], node [10] has 4 input nodes as input signal pc, pg, pj, pk and an output node as node [2], input signal pi has no input node, and has 2 output nodes as node [2], p1 , the output signal p1 has 4 input nodes for the input signal pi and nodes [2], [9], [10], and no output nodes. Adopt method of the present invention to be node [2] the concrete implementation step of window division is as follows:

For node [2], look forward to the first-level input node to obtain the set S_I1={pi, [15], [16]}, and look up the first-level output node backward to obtain the set S_O1={p1};

Each node in the set S_I1 is searched backward for two levels of output to obtain the indirect output set SI_O2={pi, [2], p1, [15], [16]}, and the node p1 in the set S_O1 is searched forward for two Level input gets indirect input set SI_I2={p1, [2], pi, [15], [16], [9], pa, pe, pj, pk, [10], pc, pg}, take set SI_O2 and The intersection of SI_I2 obtains the window related node set S={pi, [2], p1, [15], [16]} of node [2], i.e. the module 811 in Fig. 7;

According to the set S, it can be obtained that the window leaves of node [2] include nodes pb, pf, pj, pk, pd, ph, [9], [10]. In addition, the node pi in the set S is the original input of the circuit, and also The window leaf node of node [2]; there is only one output node p1 in the set S, which is the root node of the window. In summary, the window of the node [2] contains 9 leaf nodes {pi, pb, pf, pj, pk, pd, ph, [9], [10]} related to 1 root node p1 and 3 windows node {[15], [16], [2]}.

As shown in Figure 9, it is a flow chart of the irrelevant configuration bit search method in the used window of the present invention, and the step of finding the irrelevant configuration bit in the window that has been divided in step S27 is as follows:

Step S231: If entering this process for the first time, select the first configuration bit b _k of the node, k=0, otherwise k=k+1, select the next configuration bit b _k of the node.

Step S232: Generate test vectors, record and output R(x)|b _k ;

Use an exhaustive method to generate a test set for the window, select one of the test vectors x and obtain the output R(x)|b _k of the root node of the window through logic simulation, where R(x) is the input vector x applied to the leaf node of the window Root node output value.

Step S233: Flip the configuration bit b _k →b _k , apply the test vector generated in the previous step, and obtain the output R′(x)|(b _k →b _k ). Flip the configuration bit b _k selected in step S21 and apply the test vector x in step S232 to the window, and output the obtained window root node Where R′(x) is the output value of the root node when the input vector x is applied to the leaf node of the window after the configuration bit b _k is flipped, means that the single event flip simulation is performed on the configuration bit b _k , that is, if b _k =1 then If b _k ＝0 then

Step S234: Compare the results R(x)|b _k and if any That is, flipping the configuration bit b _k does not change the output of the root node of the window, then b _k is not a sensitive configuration bit, and then enters step S235; if there is

That is, if the output of the root node of the window changes after flipping the configuration bit b _k , then b _k is a sensitive configuration bit, and enters step S237;

Step S235: Judging whether all test sets have been exhausted for the configuration bit b _k , if there are still unapplied test vectors, return to step S232 and continue to apply test vectors for testing, if all test vectors have been applied, proceed to step S236.

Step S236: Mark the configuration bit b _k as a don't care configuration bit.

Step S237: mark the configuration bit b _k as a sensitive configuration bit, ie not an irrelevant configuration bit.

Step S238: Judging whether all configuration bits of the node have been traversed, judging whether the configuration bit number k has reached the maximum value, if it has reached the maximum value, then enter step S29; if the configuration bit number k has not reached the maximum value, then return to step S21 to continue A lookup of the node-independent configuration bits is performed.

Step S239: All configuration bits of the node have been simulated, and a database is established to record irrelevant configuration bit information of the node.

As shown in FIG. 10 , the present invention provides a single event event simulation for the circuit to be redundant and the constructed part of the triple-mode redundant circuit, so as to verify the anti-single event effect capability of the constructed part of the triple-mode redundant circuit. The specific steps of the single event event simulation are as follows:

Step S51: Randomly select a configuration bit L _s b _t of a look-up table of the circuit to be simulated, where L represents the look-up table in the circuit, s represents the number of the look-up table, b represents the configuration bit in the look-up table, and t represents the configuration bit number , that is, the t-th configuration bit in the s-th lookup table is selected.

Step S52: Randomly generate a test vector v, and obtain the corresponding output O(v)|L _s b _t according to the topology information of the circuit to be simulated, where O(v) represents the output value of the circuit when the input vector v is applied to the circuit to be simulated.

Step S53: Flipping the configuration bit L _s b _t selected in step S51 means that a single event event has occurred on the tth configuration bit in the sth lookup table, and applying the test vector v generated in step S52 to the circuit to be simulated Get the corresponding output Among them, O'(v) represents the output value of the circuit when the input vector v is applied to the simulated circuit after flipping the configuration bit L _s b _t . Indicates that the single-event flip simulation is performed on the configuration bit L _s b _t , that is, if L _s b _t = 1, then If L _s b _t = 0 then

Step S54: Compare the outputs in Step S52 and Step S53 The output terminal O of the circuit then enters step S55;

if any Indicates that the injected fault cannot be propagated to the output terminal O of the circuit to be simulated, and enters step S56.

Step S55: Add 1 to the fault number of the circuit to be simulated.

Step S56: Determine whether the number of injected fault points has reached the preset value, if not, go back to step S51 to continue injecting faults; if it has reached the preset value, go to step S57.

Step S57: Count the failure information of the circuit to be simulated, calculate the failure rate of the circuit to be simulated, and the single event event simulation work ends.

The above descriptions are only preferred implementations of the present invention, and it should be pointed out that those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention also intends to include these modifications and variations.

Claims (7)

1. a kind of part triplication redundancy method counted based on look-up table configuration bit, including step are as follows：

Step S1：It will treat that redundant circuit is mapped as k- input look-up table formats, and read the information for treating redundant circuit, set up circuit and open up Structural database is flutterred, the look-up table is the look-up table in FPGA；

Step S2：Circuit topological structure information to circuit topological structure database is counted, and writing circuit topological structure The unrelated configuration bit information of each node in redundant circuit is treated in database；Wherein, the step of the unrelated configuration bit information is obtained It is rapid as follows：Node is divided according to circuit topological structure, node window is obtained, judges whether further according to node window information Unrelated configuration bit is calculated, if the leaf node number of window is met when being less than leaf node maximum, the node is calculated Unrelated configuration bit number and record；If the leaf node number of window is unsatisfactory for being less than maximum, by the nothing of the node Close configuration bit number and be designated as 0；

Step S3：According to unrelated configuration bit number, the single particle effect sensitive information of look-up table is obtained；

Step S4：The look-up table of single-particle inversion-sensitivity is extracted from the single particle effect sensitive information of look-up table, and to list The look-up table of particle upset-sensitivity carries out triplication redundancy processing, obtains and according to redundant results in each redundant module and non-superfluous Voting machine is inserted between complementary modul block, the part triplication redundancy circuit with anti-single particle effect capability is built.

2. triplication redundancy method in part as claimed in claim 1, it is characterised in that the unrelated configuration bit number calculating method of node For：It is window generation exhaustive testing collection with exhaustive method, applies the exhaustive testing collection to window leaf node and overturn one by one Whether each configuration bit of node, watch window root node output changes；If overturning certain configuration bit and traveling through whole exhaustive testing Collection, window root node output is unchanged, then the configuration bit is the unrelated configuration bit of node.

3. triplication redundancy method in part as claimed in claim 1, it is characterised in that the single particle effect for obtaining look-up table is sensitive The step of property information, is as follows：The unrelated configuration bit threshold value of a look-up table is set, when the unrelated configuration bit number of some look-up table is high Then it is the look-up table of single-particle inversion-insensitive when look-up table unrelated configuration bit threshold value；When the unrelated configuration of some look-up table Then it is the look-up table of single-particle inversion-sensitivity when position number is not higher than look-up table unrelated configuration bit threshold value.

4. triplication redundancy method in part as claimed in claim 3, it is characterised in that the unrelated configuration bit threshold value H of look-up table It is expressed as follows：H=10 × (P-0.9) × Nc, wherein P are out of order general to be showed after redundant circuit is hit by single event Rate, Nc is look-up table configuration bit number, it follows that treat that redundant circuit is higher to reliability requirement, the unrelated configuration bit threshold of look-up table Value is bigger.

5. triplication redundancy method in part as claimed in claim 3, it is characterised in that carry out triplication redundancy treating redundant circuit When, redundancy processing only is done to the look-up table of the single-particle inversion-sensitivity.

6. triplication redundancy method in part as claimed in claim 1, it is characterised in that treat redundant circuit and the part three built Mould redundant circuit carries out single event emulation, to verify the energy of constructed part triplication redundancy circuit anti-single particle effect Power.

7. triplication redundancy method in part as claimed in claim 1, it is characterised in that treat that redundant circuit carries out part three to described Also need to consider the concrete structure for treating redundant circuit during the processing of mould redundancy, when the look-up table of one single-particle inversion of redundancy-insensitive When can reduce the insertion of two or more voting machine, triplication redundancy should be carried out to the single-particle inversion-insensitive look-up table.