CN104866390B - Asynchronous static random access memory triplication redundancy controller - Google Patents

Abstract

The invention provides an asynchronous random static memory triple-mode redundant controller, comprising: an address signal processing unit connected to the address signal pins of the microprocessor and the SRAM respectively, used to receive and process the first address signal, and output the second address signal to the SRAM Two address signals; the write signal processing unit is connected to the write signal pins of the microprocessor and the SRAM respectively, and is used to receive and process the first write signal, output the second write signal to the SRAM, and output the write operation address strobe signal; read The signal processing unit is connected to the read signal pins of the microprocessor and the SRAM respectively, and is used to receive and process the first read signal, output the second read signal to the SRAM, and output the read operation address strobe signal; triple-mode redundant error correction The unit is respectively connected to the data signal pins of the microprocessor and the SRAM, and is used to perform triple-mode redundancy comparison, output error status signals and comparison result data, and correct errors for backup data stored in the SRAM. The invention has the advantages of simple structure, strong compatibility, wide application range and high reliability.

Description

Asynchronous Random Static Memory Triple-mode Redundant Controller

technical field

The invention relates to the technical field of anti-radiation and fault tolerance of memory, in particular to an asynchronous random static memory triple-mode redundant controller.

Background technique

Asynchronous static random access memory (Static Random Access Memory, hereinafter referred to as asynchronous SRAM) has the characteristics of high integration, fast read and write speed, low power consumption and complete compatibility with complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, hereinafter referred to as CMOS) process, etc. , is widely used in various electronic devices for data storage. In the field of space applications, asynchronous SRAMs are also widely used in electronic equipment such as on-orbit spacecraft and satellite loads for data storage. Since there are various particles in the space environment, such as protons, electrons, alpha particles, heavy ions, gamma rays and so on. When these particles bombard the asynchronous SRAM, a variety of single event effects (SEE) will occur, including hard damage such as displacement damage and total dose effect, and soft errors such as single event upset (SEU). Asynchronous SRAM is particularly sensitive to the single event upset effect in a long-term high-dose radiation environment. The single event upset effect will cause a mutation between '0' and '1' in the stored content, resulting in errors in the stored data. Once the data is wrong, it will lead to system dysfunction and endanger the reliability, function and life of the spacecraft.

With the gradual miniaturization of the CMOS integrated circuit process and the continuous reduction of the feature size of the device, the critical charge threshold for single event upset is getting lower and lower. On the other hand, the capacity requirements of the system for the SRAM memory are getting higher and higher, and this increase in integration further leads to an increasing probability of a single event upset in the SRAM memory.

In order to resist the single event effect, especially the single event upset effect, the asynchronous SRAM is often reinforced from the device level and the application level. The device level is to strengthen the radiation resistance of the device design and process itself. For example, the radiation-resistant SRAM unit of the Chinese invention patent (patent application number 201410223064.8) discloses a SRAM unit designed for radiation hardening. In addition, radiation resistance can also be used A better SOI (Silicon On Insulator, SOI for short) process is used to produce SRAM memory. However, these methods only improve the anti-radiation ability, and cannot fundamentally eliminate the single-event upset effect caused by radiation. Therefore, it is necessary to strengthen SRAM against radiation from an application point of view. In system applications, it is generally realized by using triple modular redundancy (TMR) or error detection and correction coding (EDAC). Triple-mode redundancy technology is to back up three copies of the same data, and output the correct data through a two-out-of-three majority vote. If one of the backup data is wrong, it can be corrected; EDAC technology is to encode the data and increase the check digit. Then verify the correctness of the data through the decoding algorithm, and according to the complexity of the algorithm, 1-bit or multiple-bit error correction can be completed. These methods often require running time of the system software. For example, a Chinese invention patent for a SRAM-oriented controller and method for anti-SEU error accumulation (patent application number 201310648233.8), a Chinese invention patent space computer anti-single event flip memory error correction and automatic write-back method (patent application number 200510041617.9 ). This will complicate the software design, waste a lot of microprocessor processing time, and increase unreliable factors. For EDAC technology, research and development of dedicated EDAC chips have also been carried out at home and abroad, such as the design and implementation of EDAC modules in S698M SoC chips (Huang Lin, Chen Dihu, Liang Baoyu, etc. China Integrated Circuit, 2008, 112(9): 50- 54.) etc. However, EDAC codec is complex, its error correction capability is weaker than TMR, and its execution speed is also limited. Therefore, the way based on triple redundancy is the best. However, there is currently no effective solution that can implement triple-mode redundant control on the existing asynchronous SRAM memory to achieve data fault-tolerant processing without increasing the burden on the system software and without changing the software structure of the system microprocessor.

FIG. 1 is a schematic diagram of an application scenario of an asynchronous random SRAM in the prior art. Microprocessor (single chip microcomputer, FPGA, etc.) is directly connected to SRAM, including address bus Addr, data bus Data, chip select signal CS (active low), write enable signal WE (active low) and read enable signal OE (active low). These signals are standard interfaces of asynchronous SRAMs. The read and write timings of different types of asynchronous SRAMs are usually uniform, but the difference is that the bit widths of the data bus Data and the address bus Addr may be different.

FIG. 2 and FIG. 3 are schematic diagrams of the timing sequence of the write operation/read operation of the asynchronous random static memory in the above-mentioned prior art, respectively. When the chip select signal CS is low and the read enable signal OE is high, write the data Data into the specified address Addr during the low level period of the write enable signal WE; when the chip select signal CS is low, write enable When the signal WE is high, the data Data in the specified address Addr will be output during the low level period of the read enable signal OE.

Contents of the invention

A brief overview of the invention is given below in order to provide a basic understanding of some aspects of the invention. It should be understood that this summary is not an exhaustive overview of the invention. It is not intended to identify key or critical parts of the invention nor to delineate the scope of the invention. Its purpose is merely to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later.

The invention provides an asynchronous random static memory triple-mode redundant controller capable of realizing SRAM triple-mode redundant backup, majority voting and correcting functions without occupying system software running time and without changing the microprocessor software structure.

The present invention provides an asynchronous random static memory triple-mode redundant controller, comprising:

The address signal processing unit is connected to the address signal pins of the microprocessor and the random static memory respectively, and is used to receive and process the first address signal output by the microprocessor, and output to the random static memory including the write operation address, read a second address signal of an operation address or an error correction operation address;

A write signal processing unit is respectively connected to the write signal pins of the microprocessor and the random static memory, and is connected to the address signal processing unit for receiving and processing the first write signal output by the microprocessor , outputting a second write signal to the random static memory, and outputting a gate signal for gating the address of the write operation to the address signal processing unit;

The read signal processing unit is respectively connected to the read signal pins of the microprocessor and the random static memory, and is connected to the address signal processing unit for receiving and processing the first read signal output by the microprocessor outputting a second read signal to the random static memory, and outputting a gate signal for gating the address of the read operation to the address signal processing unit;

The three-mode redundant error correction unit is respectively connected to the data signal pin of the microprocessor, the error state signal pin and the data signal pin of the random static memory, and is respectively connected with the read signal processing unit and the described read signal processing unit. The write signal processing unit is connected with the address signal processing unit, and is used for performing triple-modular redundancy comparison on the input three copies of backup data, outputting an error status signal and comparison result data to the microprocessor, and performing an operation on the random static memory Stored backup data for error correction.

The three-mode redundant controller of the asynchronous random static memory provided by the present invention is set between the system microprocessor and the asynchronous random static memory as a bridge, and automatically converts the write/read operation of the microprocessor to the asynchronous random static memory into a three-mode redundant controller. Yu and the three out of two majority voting operation sequence, realize the automatic processing of triple-mode redundancy fault tolerance, thereby replacing the processing of triple-mode redundancy in the system software, reducing the burden on the system software, and at the same time without changing the system microprocessor software structure , which reduces the complexity of system software design and ensures reliability at the same time. To sum up, the three-mode redundant controller for asynchronous random static memory of the present invention has the advantages of simple structure, strong compatibility, wide application range, and high reliability.

Description of drawings

The above and other objects, features and advantages of the present invention will be more easily understood with reference to the following description of the embodiments of the present invention in conjunction with the accompanying drawings. The components in the drawings are only to illustrate the principles of the invention. In the drawings, the same or similar technical features or components will be denoted by the same or similar reference numerals.

FIG. 1 is a schematic diagram of an application scenario of an asynchronous random SRAM in the prior art.

FIG. 2 is a schematic diagram of a write operation sequence of an asynchronous random static memory in the prior art.

FIG. 3 is a schematic diagram of a read operation timing sequence of an asynchronous random static memory in the prior art.

FIG. 4 is a schematic diagram of an application scenario of an asynchronous random static memory triple-mode redundant controller of the present invention.

FIG. 5 is a schematic diagram of the pin structure of the three-mode redundant controller of the asynchronous random static memory of the present invention.

Fig. 6 is a schematic diagram of the internal structure of the three-mode redundant controller of the asynchronous random static memory of the present invention.

FIG. 7 is a schematic structural diagram of the write signal delay module of the triple-mode redundant controller of the asynchronous random static memory of the present invention.

FIG. 8 is a timing diagram of a write signal delay module of an asynchronous random SRAM triple-mode redundant controller according to the present invention.

FIG. 9 is a schematic structural diagram of a write sequence module of an asynchronous random static memory triple-mode redundant controller of the present invention.

FIG. 10 is a timing schematic diagram of the write sequence module of the ARAM triple-mode redundant controller of the present invention.

FIG. 11 is a schematic structural diagram of the read signal delay module of the ARAM triple-mode redundant controller of the present invention.

FIG. 12 is a timing diagram of a read signal delay module of an asynchronous random static memory triple-mode redundant controller of the present invention.

FIG. 13 is a schematic structural diagram of a read sequence module of an asynchronous random static memory triple-mode redundant controller of the present invention.

FIG. 14 is a timing schematic diagram of a read timing module of an asynchronous random static memory triple-mode redundant controller of the present invention.

FIG. 15 is a schematic structural diagram of an address calculation module of an asynchronous random static memory triple-mode redundant controller of the present invention.

FIG. 16 is a timing diagram of the address calculation module of the ARAM triple-mode redundant controller of the present invention.

FIG. 17 is a schematic structural diagram of the write address module of the ARAM triple-mode redundant controller of the present invention.

FIG. 18 is a timing diagram of the write address module of the ARAM triple-mode redundant controller of the present invention.

FIG. 19 is a schematic structural diagram of the read address module of the ARAM triple-mode redundant controller of the present invention.

FIG. 20 is a timing diagram of the read address module of the ARAM triple-mode redundant controller of the present invention.

FIG. 21 is a schematic diagram of the principle of dividing the address space of the asynchronous random static memory by the triple-mode redundant controller of the asynchronous random static memory of the present invention.

Fig. 22 is a schematic structural diagram of an error correction address module of an asynchronous random static memory triple-mode redundant controller of the present invention.

Fig. 23 is a schematic diagram of the time sequence when the second backup data of the error correction address module of the asynchronous random static memory triple-mode redundant controller of the present invention is in error.

FIG. 24 is a schematic structural diagram of the majority voting module of the ARAM triple-mode redundant controller of the present invention.

FIG. 25 is a schematic diagram of the time sequence when the majority voting module of the ARAM triple-mode redundant controller of the present invention has no error data.

FIG. 26 is a schematic diagram of the time sequence when the majority voting module of the ARAM triple-mode redundant controller of the present invention has an error data.

FIG. 27 is a schematic diagram of the time sequence when the three data of the majority voting module of the asynchronous random static memory triple-mode redundant controller of the present invention are different.

FIG. 28 is a schematic structural diagram of an error correction sequence module of an asynchronous random static memory triple-mode redundant controller of the present invention.

FIG. 29 is a timing schematic diagram of the error correction timing module of the ARAM triple-mode redundant controller of the present invention.

FIG. 30 is a schematic diagram of the write operation sequence of the three-mode redundant controller of the asynchronous random SRAM according to the present invention.

FIG. 31 is a schematic diagram of the timing sequence of the read operation of the ARAM triple-mode redundant controller of the present invention when there is no error data.

FIG. 32 is a schematic diagram of the timing sequence of the read operation when there is an error data in the ARAM triple-mode redundant controller of the present invention.

FIG. 33 is a schematic diagram of the timing sequence of the read operation when the three data of the three-mode redundant controller of the asynchronous random static memory of the present invention are different.

FIG. 34 is a schematic diagram of the internal signal sequence of the write operation of the triple-mode redundant controller of the asynchronous random static memory of the present invention.

FIG. 35 is a schematic diagram of the internal signal sequence when the read operation of the triple-mode redundancy controller of the asynchronous random static memory of the present invention has no error data.

FIG. 36 is a schematic diagram of the internal signal sequence when there is an error data in the read operation of the triple-mode redundancy controller of the asynchronous random static memory of the present invention.

FIG. 37 is a schematic diagram of the timing sequence of internal signals when the three data in the read operation of the asynchronous random static memory triple-mode redundant controller of the present invention are different.

Fig. 38 is a simulation waveform diagram of the write operation of the triple-mode redundant controller of the asynchronous random static memory of the present invention.

Fig. 39 is a simulation waveform diagram when there is no error data in the read operation of the asynchronous random static memory triple-mode redundant controller of the present invention.

Fig. 40 is a simulation waveform diagram when the first data error occurs in the read operation of the ARAM triple-mode redundant controller of the present invention.

Fig. 41 is a simulation waveform diagram when the second data error occurs in the read operation of the triple-mode redundant controller of the asynchronous random static memory of the present invention.

Fig. 42 is a simulation waveform diagram when the third data error occurs in the read operation of the ARAM triple-mode redundancy controller of the present invention.

Fig. 43 is a simulation waveform diagram when the three data of the read operation of the asynchronous random static memory triple-mode redundant controller of the present invention are different.

Explanation of reference signs:

10 Asynchronous random static memory triple-mode redundant controller

1011 First address signal pin

1012 Second address signal pin

1021 The first data signal pin

1022 Second data signal pin

1031 First write signal pin

1032 Second write signal pin

1041 First read signal pin

1042 Second read signal pin

1051 First error status signal pin

1061 The first chip select signal pin

1062 The second chip select signal pin

121 address calculation module

123 write address module

125 Read address module

127 Error correction address module

129 second and module

141 Write signal delay module

143 Write timing module

145 First and Modules

161 Read signal delay module

163 read timing module

181 majority voting module

183 Error correction timing module

191 First input buffer

193 First tri-state output buffer

195 Second input buffer

197 Second tri-state output buffer

Detailed ways

Embodiments of the present invention will be described below with reference to the drawings. Elements and features described in one drawing or one embodiment of the present invention may be combined with elements and features shown in one or more other drawings or embodiments. It should be noted that representation and description of components and processes that are not related to the present invention and known to those of ordinary skill in the art are omitted from the drawings and descriptions for the purpose of clarity.

FIG. 4 is a schematic diagram of an application scenario of an asynchronous random static memory triple-mode redundant controller of the present invention.

As shown in FIG. 4 , the microprocessor does not directly read and write the asynchronous random static memory, but indirectly reads and writes the asynchronous random static memory through the triple-mode redundant controller of the asynchronous random static memory of the present invention as a bridge. The design of the invention keeps the read-write sequence between the asynchronous random static memory triple-mode redundant controller and the microprocessor consistent with that of the common asynchronous random static memory.

For each write operation of the microprocessor, the asynchronous random static memory triple-mode redundancy controller converts it into write operations of three different addresses, the written data is the same but the address is different, thereby performing data backup The role of three copies; for each read operation of the microprocessor, the three-mode redundant controller of the asynchronous random static memory converts it into three read operations of different addresses, and performs after reading three backup data Two out of three votes output the correct result to the microprocessor, if one data error occurs, the correct result is written back for error correction, and if two data errors occur and the three backup data are all different, then the result is returned to the microprocessor Error status signal.

FIG. 5 is a schematic diagram of the pin structure of the three-mode redundant controller of the asynchronous random static memory of the present invention.

As shown in Figure 5, the asynchronous random static memory triple-mode redundant controller 10 of the present invention is provided with and connects described microprocessor:

a first address signal pin 1011 for inputting a first address signal AddrL[N:0],

The first data signal pin 1021 for inputting the first data signal DataL[M:0],

a first write signal pin 1031 for inputting a first write signal WEL,

a first read signal pin 1041 for inputting a first read signal OEL,

A first error status signal pin 1051 for outputting an error status signal ErrorStatus,

The first chip select signal pin 1061 for inputting the first chip select signal CSL;

and connect the random static memory with:

a second address signal pin 1012 for outputting a second address signal AddrR[N:0],

the second data signal pin 1022 for outputting the second data signal DataR[M:0],

a second write signal pin 1032 for outputting a second write signal WER,

a second read signal pin 1042 for outputting a second read signal OER,

The second chip select signal pin 1062 for outputting the second chip select signal CSR.

Among them, N is the address bit width, and M is the data bit width.

Fig. 6 is a schematic diagram of the internal structure of the three-mode redundant controller of the asynchronous random static memory of the present invention.

As shown in FIG. 6, in this embodiment, the asynchronous random static memory triple-mode redundant controller 10 of the present invention includes:

The address signal processing unit is respectively connected to the address signal pins of the microprocessor and the random static memory, for receiving and processing the first address signal AddrL[N:0] output by the microprocessor, and outputting to the random static memory A second address signal AddrR[N:0] including a write operation address, a read operation address or an error correction operation address;

A write signal processing unit is respectively connected to the write signal pins of the microprocessor and the random static memory, and is connected to the address signal processing unit for receiving and processing the first write signal output by the microprocessor WEL, outputting a second write signal WER to the random static memory, outputting a strobe signal for gating the write operation address to the address signal processing unit;

The read signal processing unit is respectively connected to the read signal pins of the microprocessor and the random static memory, and is connected to the address signal processing unit for receiving and processing the first read signal output by the microprocessor OEL, outputting a second read signal OER to the random static memory, outputting a strobe signal for gating the address of the read operation to the address signal processing unit;

The three-mode redundant error correction unit is respectively connected to the data signal pin of the microprocessor, the error state signal pin and the data signal pin of the random static memory, and is respectively connected with the read signal processing unit and the described read signal processing unit. The write signal processing unit is connected with the address signal processing unit, and is used to perform triple-modular redundancy comparison on the input three backup data, and output error status signal ErrorStatus and comparison result data to the microprocessor, and to the random static Error correction is performed on the backup data stored in the memory.

Preferably, the write signal processing unit includes:

Write signal delay module 141, the input terminal is connected to the first write signal pin 1031, and the four output terminals respectively output the first zero-delay write signal WEL0, the second delay write signal WEL1, the third delay write signal WEL2 and the first delay write signal WEL2. The four-delay write signal WEL3 is used to output the first write signal WEL with multi-stage delay. The first write signal pin 1031 is connected to the write signal pin of the microprocessor.

Write timing module 143, the four input ends are respectively connected to the four output ends of the write signal delay module 141, and the four output ends respectively output the third write signal WER1, the first strobe signal WAddrS1, the second strobe signal WAddrS2 and the second strobe signal WAddrS2 The three strobe signals WAddrS3 are used to calculate and output the third write signal WER1 for the write operation and the strobe signals WAddrS1-WAddrS3 for strobe the address of the write operation.

The first AND module 145, the input terminal is connected to the write timing module 143 and the triple-mode redundant error correction unit, and the output terminal is connected to the second write signal pin 1032, which is used to output the second write signal WER, specifically included in the write operation sequence The third write signal WER1 for the write operation is output, and the fourth write signal WER2 for the error correction operation is output at the timing of the error correction operation. The second write signal pin 1032 is connected to the write signal pin of the RAM.

FIG. 7 is a schematic structural diagram of the write signal delay module of the triple-mode redundant controller of the asynchronous random static memory of the present invention.

As shown in FIG. 7 , preferably, the write signal delay module 141 includes a first delay sub-module WELDelay1 , a second delay sub-module WELDelay2 and a third delay sub-module WELDelay3 . The first write signal WEL is input into the write signal delay module 141 and then divided into two paths, one path directly obtains and outputs the first zero-delay write signal WEL0, and the other path is delayed by the first delay sub-module WELDelay1 to obtain and output the second delayed When writing signal WEL1. The second delayed write signal WEL1 is then delayed by the second delay sub-module WELDelay2 to obtain and output the third delayed write signal WEL2. The third delayed write signal WEL2 is then delayed by the third delay sub-module WELDelay3 to obtain and output the fourth delayed write signal WEL3.

Usually, the delay parameters of the above three delay sub-modules are the same. The selection of the delay parameter needs to be based on the asynchronous random static memory used, and should be greater than or equal to the minimum write cycle of the asynchronous random static memory.

FIG. 8 is a timing diagram of a write signal delay module of an asynchronous random SRAM triple-mode redundant controller according to the present invention. As shown in FIG. 8, after the first write signal WEL is input to the write signal delay module 141, the first zero-delay write signal WEL0 is synchronously output with zero delay, the second delay write signal WEL1, the third delay write signal WEL2 and The fourth delayed write signal WEL3 is sequentially delayed and output.

FIG. 9 is a schematic structural diagram of a write sequence module of an asynchronous random static memory triple-mode redundant controller of the present invention.

As shown in FIG. 9, preferably, the write sequence module 143 includes three 4-input NAND gates connected to the four input terminals of the write sequence module 143 respectively, and a three-input terminal connected to the three 4-input NAND gates respectively. The outputs of the 3-input AND gates are connected. The output results of the three 4-input NAND gates are respectively the first strobe signal WAddrS1 , the second strobe signal WAddrS2 and the third strobe signal WAddrS3 . The output result of the 3-input AND gate is the third write signal WER1.

Wherein, the first 4-input NAND gate has an inverting input terminal and three non-inverting input terminals, and the inverting input terminal inputs the first zero-delay write signal WEL0; the second 4-input NAND gate has Two inverting input terminals and two non-inverting input terminals, the inverting input terminal inputs the first zero-delay write signal WEL0 and the second delay write signal WEL1; the third 4-input NAND gate has three inverting inputs terminal and a non-inverting input terminal, and the inverting input terminal inputs the first zero-delay write signal WEL0, the second delay write signal WEL1 and the third delay write signal WEL2.

FIG. 10 is a timing schematic diagram of the write sequence module of the ARAM triple-mode redundant controller of the present invention. The timings of the first strobe signal WAddrS1 , the second strobe signal WAddrS2 , the third strobe signal WAddrS3 and the third write signal WER1 are shown in FIG. 10 .

When the write sequence module 143 is working, the first strobe signal WAddrS1 , the second strobe signal WAddrS2 and the third strobe signal WAddrS3 are used to strobe three different addresses in the data backup area, and the low level is active. When the first strobe signal WAddrS1 is low level, write address module 123 outputs the address of the first backup data, when the second strobe signal WAddrS2 is low level, write address module 123 outputs the address of the second backup data, and the third strobe signal WAddrS3 When it is at low level, the write address module 123 outputs the address of the third backup data, and the third write signal WER1 is all at low level during the process of selecting and outputting three write addresses.

Preferably, the read signal processing unit includes:

The read signal delay module 161, the input terminal is connected to the first read signal pin 1041, and the four output terminals respectively output the first zero-delay read signal OEL0, the second delayed read signal OEL1, the third delayed read signal OEL2 and the The four-delay read signal OEL3 is used to output the first read signal OEL with multi-level delay. The first read signal pin 1041 is connected to the read signal pin of the microprocessor.

Read timing module 163, four input terminals are respectively connected to the four output terminals of the read signal delay module 161, and the four output terminals output the second read signal OER, the fourth strobe signal RAddrS1, the fifth strobe signal RAddrS2 and the fourth strobe signal respectively. Six strobe signals RAddrS3 are used to calculate and output the second read signal OER for the read operation and the strobe signals RAddrS1 , RAddrS2 and RAddrS3 for strobe the address of the read operation. The output terminal outputting the second read signal OER is connected to the second read signal pin 1042, and the second read signal pin 1042 is connected to the read signal pin of the RAM.

FIG. 11 is a schematic structural diagram of the read signal delay module of the ARAM triple-mode redundant controller of the present invention.

As shown in FIG. 11 , preferably, the read signal delay module 161 includes a fourth delay sub-module OELDelay1 , a fifth delay sub-module OELDelay2 and a sixth delay sub-module OELDelay3 . After the first read signal OEL is input into the read signal delay module 161, it is divided into two paths, one path directly obtains and outputs the first zero-delay read signal OEL0, and the other path is delayed by the fourth delay sub-module OELDelay1 to obtain and output the second delayed When reading signal OEL1. The second delayed read signal OEL1 is then delayed by the fifth delay sub-module OELDelay2 to obtain and output the third delayed read signal OEL2. The third delayed read signal OEL2 is then delayed by the sixth delay sub-module OELDelay3 to obtain and output the fourth delayed read signal OEL3.

FIG. 12 is a timing diagram of a read signal delay module of an asynchronous random static memory triple-mode redundant controller of the present invention. As shown in FIG. 12, after the first read signal OEL is input into the read signal delay module 161, the first zero-delay read signal OEL0 is synchronously output with zero delay, the second delay read signal OEL1, the third delay read signal OEL2 and The fourth delayed read signal OEL3 is sequentially delayed and output.

FIG. 13 is a schematic structural diagram of a read sequence module of an asynchronous random static memory triple-mode redundant controller of the present invention.

As shown in FIG. 13, preferably, the read timing module 163 includes three 4-input NAND gates connected to the four input terminals of the read timing module 163 respectively, and a three-input NAND gate respectively connected to the three 4-input NAND gates. The outputs of the 3-input AND gates are connected. The output results of the three 4-input NAND gates are respectively the fourth strobe signal RAddrS1, the fifth strobe signal RAddrS2 and the sixth strobe signal RAddrS3, and the output results of the 3-input AND gate are the second read signal OER .

Wherein, the fourth 4-input NAND gate has an inverting input terminal and three non-inverting input terminals, and the inverting input terminal inputs the first zero-delay read signal OEL0. The fifth 4-input NAND gate has two inverting input terminals and two non-inverting input terminals, and the inverting input terminals input the first zero-delay read signal OEL0 and the second delay read signal OEL1 respectively. The sixth 4-input NAND gate has three inverting input terminals and one non-inverting input terminal, and the inverting input terminals respectively input the first zero-delay read signal OEL0, the second delay read signal OEL1 and the third delay read signal Signal OEL2.

FIG. 14 is a timing schematic diagram of a read timing module of an asynchronous random static memory triple-mode redundant controller of the present invention. The timings of the fourth strobe signal RAddrS1 , the fifth strobe signal RAddrS2 , the sixth strobe signal RAddrS3 and the second read signal OER are shown in FIG. 10 .

When the read sequence module 163 is working, the fourth strobe signal RAddrS1 , the fifth strobe signal RAddrS2 and the sixth strobe signal RAddrS3 are used to strobe three different addresses in the data backup area, and are active at low level. When the fourth strobe signal RAddrS1 is low level, the read address module 125 outputs the address of the first backup data, when the fifth strobe signal RAddrS2 is low level, the read address module 125 outputs the address of the second backup data, and the sixth strobe signal RAddrS3 When it is at low level, the read address module 125 outputs the address of the third backup data, and the second read signal OER is at low level during the process of selecting and outputting three read addresses.

Preferably, the address signal processing unit includes:

The address calculation module 121, the input terminal is connected to the first address signal pin 1011, and the three output terminals respectively output the first backup address signal Addr0, the second backup address signal Addr1 and the third backup address signal Addr2, which are used to calculate and output the first Three backup addresses Addr0 , Addr1 , Addr2 corresponding to the address signal AddrL. The first address signal pin 1011 is connected to the address signal pin of the microprocessor.

Write address module 123, six input terminals are respectively connected to three output terminals of output strobe signal WAddrS1, WAddrS2, WAddrS3 of write timing module 143 and three output terminals of address calculation module 121, output terminal output write operation address FA1, for receiving and processing the first strobe signal WAddrS1, the second strobe signal WAddrS2, the third strobe signal WAddrS3, and the first backup address signal Addr0, the second backup address signal Addr1, and the third backup address signal Addr2 of the write operation sequence, Output write operation address FA1.

Read address module 125, six input terminals are respectively connected to three output terminals of read timing module 163 output strobe signals RAddrS1, RAddrS2, RAddrS3 and three output terminals of address calculation module 121, output terminal output read operation address FA2, for Receive and process the fourth strobe signal RAddrS1, the fifth strobe signal RAddrS2, the sixth strobe signal RAddrS3, and the first backup address signal Addr0, the second backup address signal Addr1, and the third backup address signal Addr2 of the read operation sequence, Output the read operation address FA2.

Error correction address module 127, seven input terminals are respectively connected to the output terminal of the read timing module 163 outputting the second read signal OER, the three output terminals of the triple-mode redundant error correction unit output strobe signal and the address calculation module 121 Three output terminals, the output terminal outputs the error correction operation address FA3, which is used to receive and process the second read signal OER, the error correction operation address strobe signals EAddrS1, EAddrS2, EAddrS3 output by the triple-mode redundant error correction unit, and The first backup address signal Addr0 , the second backup address signal Addr1 , and the third backup address signal Addr2 in the error correction operation sequence output the error correction operation address FA3 .

The second AND module 129, three input terminals are respectively connected to the output terminal of the write address module 123, the output terminal of the read address module 125, and the output terminal of the error correction address module 127, and the output terminal is connected to the second address signal pin 1012 for The write operation address FA1 is output at the write operation sequence, the read operation address FA2 is output at the read operation sequence, and the error correction operation address FA3 is output at the error correction operation sequence. The second address signal pin 1012 is connected to the address signal pin of the RAM.

FIG. 15 is a schematic structural diagram of an address calculation module of an asynchronous random static memory triple-mode redundant controller of the present invention.

FIG. 16 is a timing diagram of the address calculation module of the ARAM triple-mode redundant controller of the present invention.

As shown in FIG. 15 , preferably, the address calculation module 121 is divided into three calculation circuits to perform parallel calculation processing on the first address signal AddrL, and the first address signal AddrL is respectively obtained directly through the buffer and outputs the first backup address signal Addr0, through The first adder adds the offset to obtain and output a second backup address signal Addr1, and the second adder adds to twice the offset to obtain and output a third backup address signal Addr2.

The offset is obtained by calculating the address bit width of the asynchronous random static memory.

Preferably, the address bit width of the asynchronous random static memory is N bits, then the calculation method of the offset offset is:

FIG. 21 is a schematic diagram of the principle of dividing the address space of the asynchronous random static memory by the triple-mode redundant controller of the asynchronous random static memory of the present invention. As shown in FIG. 21 , since the same data needs to be backed up three times in the asynchronous random static memory, it is first necessary to divide the storage space of the asynchronous random static memory. The address bit width of the asynchronous random static memory is N bits, so 2 ^N pieces of data can be stored in total. In order to backup three copies of data, the address space is divided into three parts according to the sequence, which are 0～(Offset-1), Offset～(2*Offset-1), 2*Offset～(3*Offset-1) . in, where the symbol Indicates rounding down. For example, in this embodiment, the address bit width N of the asynchronous random static memory is 16 bits, then At this time, the three backup address spaces are 0~0x5554, 0x5555~0xAAA9, 0xAAAA~0xFFFE in turn. After division, the effective storage space of the asynchronous random static memory is only one part, and the other two are used as the backup data of the three-mode redundancy, that is, the effective storage space of the asynchronous random static memory is reduced to one-third, from the original 0 ~2 ^N is reduced to 0~(Offset-1). The same data will be stored in Addr, Addr+Offset, Addr+2Offset respectively, where the address range of Addr is 0~(Offset-1).

Because 2 ^N cannot be divisible by 3, so can leave 1 or 2 addresses not to be used at last in the asynchronous random static memory, the address (being 0xFFFF in this embodiment) that stays at last is in the described asynchronous random static memory It is used as a no-operation address in the triple-mode redundant controller.

FIG. 17 is a schematic structural diagram of the write address module of the ARAM triple-mode redundant controller of the present invention.

As shown in FIG. 17, preferably, the write address module 123 performs three 2-input OR gates and the first strobe signal WAddrS1, the second strobe signal WAddrS2, and the third strobe signal WAddrS3 respectively to the first backup address signal Addr0, The second backup address signal Addr1 and the third backup address signal Addr2 perform output control, and combine the outputs WA1, WA2 and WA3 of the three 2-input OR gates through a 3-input AND gate to output the write operation address FA1, thereby realizing continuous Outputting the first backup address signal, the second backup address signal and the third backup address signal of the write operation timing.

Specifically, when the first strobe signal WAddrS1 is at low level, WA1 outputs the first backup address signal Addr0, when the first strobe signal WAddrS1 is at high level, WA1 outputs the last free address 0xFFFF; when the second strobe signal When WAddrS2 is low level, WA2 outputs the second backup address signal Addr1, when the second strobe signal WAddrS2 is high level, WA2 outputs the last free address 0xFFFF; when the third strobe signal WAddrS3 is low level, WA3 outputs the first Three backup address signals Addr2, when the third strobe signal WAddrS3 is high level, WA3 outputs the last free address 0xFFFF.

FIG. 18 is a timing diagram of the write address module of the ARAM triple-mode redundant controller of the present invention.

As shown in FIG. 18 , when the first strobe signal WAddrS1 , the second strobe signal WAddrS2 , and the third strobe signal WAddrS3 are all at high level, the write address FA1 is output as 0xFFFF. When the first strobe signal WAddrS1 becomes low level, the write operation address FA1 outputs the value of the first backup address signal Addr0. When the second strobe signal WAddrS2 becomes low level, the write operation address FA1 outputs the value of the second backup address signal Addr1. When the third strobe signal WAddrS3 becomes low level, the write operation address FA1 outputs the value of the third backup address signal Addr2. The final effect is that the write operation address FA1 continuously outputs three backup address signals, thereby realizing backup writing of three copies of data.

FIG. 19 is a schematic structural diagram of the read address module of the ARAM triple-mode redundant controller of the present invention.

As shown in FIG. 19, preferably, the read address module 125 performs three 2-input OR gates and the fourth strobe signal RAddrS1, the fifth strobe signal RAddrS2, and the sixth strobe signal RAddrS3 to the first backup address signal Addr0, The second backup address signal Addr1 and the third backup address signal Addr2 perform output control, and combine the outputs RA1, RA2 and RA3 of the three 2-input OR gates through a 3-input AND gate, so as to realize the first sequence of continuous output read operation timing A backup address signal, a second backup address signal and a third backup address signal.

Specifically, when the fourth strobe signal RAddrS1 is low level, RA1 outputs the first backup address signal Addr0, when the fourth strobe signal RAddrS1 is high level, RA1 outputs the last free address 0xFFFF; when the fifth strobe signal When RAddrS2 is low level, RA2 outputs the second backup address signal Addr1, when the fifth strobe signal RAddrS2 is high level, RA2 outputs the last free address 0xFFFF; when the sixth strobe signal RAddrS3 is low level, RA3 outputs the first Three backup address signals Addr2, when the sixth strobe signal RAddrS3 is high level, RA3 outputs the last free address 0xFFFF.

FIG. 20 is a timing diagram of the read address module of the ARAM triple-mode redundant controller of the present invention.

As shown in FIG. 20 , when the fourth strobe signal RAddrS1 , the fifth strobe signal RAddrS2 , and the sixth strobe signal RAddrS3 are all at high level, the output of the read operation address FA2 is 0xFFFF. When the fourth strobe signal RAddrS1 becomes low level, the read operation address FA2 outputs the value of the first backup address signal Addr0. When the fifth strobe signal RAddrS2 becomes low level, the read operation address FA2 outputs the value of the second backup address signal Addr1. When the sixth strobe signal RAddrS3 becomes low level, the read operation address FA2 outputs the value of the third backup address signal Addr2. The final effect is that the read operation address FA2 continuously outputs three backup address signals, thereby realizing backup reading of three copies of data.

Fig. 22 is a schematic structural diagram of an error correction address module of an asynchronous random static memory triple-mode redundant controller of the present invention.

As shown in FIG. 22, preferably, the error correction address module 127 includes three 2-input OR gates, a 3-input AND gate and a 10th 2-input OR gate containing an inverting input terminal, respectively through the three 2-input The OR gate and the seventh strobe signal EAddrS1, the eighth strobe signal EAddrS2, and the ninth strobe signal EAddrS3 control the output of the first backup address signal Addr0, the second backup address signal Addr1, and the third backup address signal Addr2, and output EA1, EA2 and EA3, the output terminals of the three 2-input OR gates are respectively connected to the input terminals of the 3-input AND gate, and the non-inverting input terminal of the tenth 2-input OR gate is connected to the output of the 3-input AND gate end, the reverse input end is connected to the input end of the second read signal OER, and the output end outputs the error correction operation address FA3.

Specifically, when the seventh strobe signal EAddrS1 is at low level, EA1 outputs the first backup address signal Addr0, when the seventh strobe signal EAddrS1 is at high level, EA1 outputs the last free address 0xFFFF; when the eighth strobe signal When EAddrS2 is low level, EA2 outputs the second backup address signal Addr1, when the eighth strobe signal EAddrS2 is high level, EA2 outputs the last free address 0xFFFF; when the ninth strobe signal EAddrS3 is low level, EA3 outputs the first Three backup address signals Addr2, when the ninth strobe signal EAddrS3 is at high level, EA3 outputs the last free address 0xFFFF.

EA1, EA2 and EA3 are input to the 3-input AND gate, the output of the 3-input AND gate and the second read signal OER are connected to the 2-input OR gate, and the 2-input OR gate outputs an error correction operation address FA3.

Fig. 23 is a schematic diagram of the time sequence when the second backup data of the error correction address module of the asynchronous random static memory triple-mode redundant controller of the present invention is in error.

When the error correction address module 127 is working, when the seventh strobe signal EAddrS1 , the eighth strobe signal EAddrS2 , and the ninth strobe signal EAddrS3 are all at high level, the output of the error correction operation address FA3 is 0xFFFF. When the seventh strobe signal EAddrS1 becomes low level and the second read signal OER is high level, the error correction operation address FA3 outputs the value of the first backup address signal Addr0. When the eighth strobe signal EAddrS2 becomes low level and the second read signal OER is high level, the error correction operation address FA3 outputs the value of the second backup address signal Addr1. When WAddrS3 becomes low level and the second read signal OER is high level, the error correction operation address FA3 outputs the value of the third backup address signal Addr2.

Preferably, the triple-mode redundant error correction unit includes:

The majority voting module 181, the six input terminals are respectively connected to the output terminal of the second read signal OER output by the read timing module 161, the four output terminals of the read signal delay module 163, and the second data signal pin 1022, and the six output terminals are respectively Output the first comparison result signal C12, the second comparison result signal C23, the third comparison result signal C31, the majority voting result data FinalDataOut, the majority voting result strobe signal FinalReadOutControl and the error status signal ErrorStatus, for guiding by the second data signal The three copies of backup data input by pin 1022 are compared for triple redundancy and the comparison result is output, and the error status signal ErrorStatus and the comparison result data are output to the microprocessor. The first comparison result signal C12 , the second comparison result signal C23 , and the third comparison result signal C31 are result signals of pairwise comparison of the three backup data. The second data signal pin 1022 is connected to the data signal pin of the RAM. The two output terminals outputting the majority voting result data FinalDataOut and the majority voting result strobe signal FinalReadOutControl are connected to the first data signal pin 1021, and the first data signal pin 1021 is connected to the data signal pin of the microprocessor. The output end of the error status signal ErrorStatus is connected to the first error status signal pin 1051, and the first error status signal pin 1051 is connected to the second error status signal pin of the microprocessor.

Error correction timing module 183, four input terminals are respectively connected to the output terminal of the second read signal OER output by the read timing module 163, three output terminals of the majority voting module 181 output comparison result signals C12, C23, C31, the four output terminals are respectively Connect the input end of the first AND module 145, the error correction address module 127 is used to input the three input ends of the strobe signal EAddrS1, EAddrS2, EAddrS3, for receiving and processing the second read signal OER, the first comparison result signal C12, The second comparison result signal C23 and the third comparison result signal C31 output the fourth write signal WER2 of the error correction operation to the first AND module 145, and output the seventh selection for gating the error correction operation address to the error correction address module 127. The pass signal EAddrS1, the eighth strobe signal EAddrS2 and the ninth strobe signal EAddrS3.

FIG. 24 is a schematic structural diagram of the majority voting module of the ARAM triple-mode redundant controller of the present invention.

As shown in FIG. 24, preferably, the majority voting module 181 respectively latches the three backup data through three latches, and compares the three backup data two by two through three comparators to obtain the first The comparison result signal C12, the second comparison result signal C23, and the third comparison result signal C31 are respectively obtained and outputted through logic circuit operations: the majority voting result data FinalDataOut, the majority voting result strobe signal FinalReadOutControl and the error status signal ErrorStatus.

Specifically, inside the majority voting module 181, the data signal DataRead input by the random static memory through the second data signal pin 1022 is respectively connected to the data input terminals of the three LD8CE latches, and the first zero-delay read signal OEL0 Connect to the clearing terminal (CLR) of the three LD8CE latches respectively, and the enable terminal (GE) of the three LD8CE latches is connected to a high level to indicate enabling; the second delayed read signal OEL1 is connected to the first latch The input terminal G of the device LD1, the falling edge of the second delayed read signal OEL1 latches the DataRead data, and outputs the first latched data signal RData1, which is the first backup data; the third delayed read signal OEL2 is connected to the second lock The input terminal G of the register LD2, the falling edge of the third delayed read signal OEL2 latches the DataRead data, and outputs the second latched data signal RData2, which is the second backup data; the fourth delayed read signal OEL3 is connected to the third At the input terminal G of the latch LD3, the falling edge of the fourth delayed read signal OEL3 latches the DataRead data, and outputs the third latched data signal RData3, that is, the third backup data.

The input terminal A of the first comparator COMP12 inputs the first latch data signal RData1 output by the first latch LD1, and the input terminal B inputs the second latch data signal RData2 output by the second latch LD2; the second comparator The input terminal A of COMP23 inputs the second latch data signal RData2 that the second latch LD2 outputs, and the input terminal B inputs the third latch data signal RData3 that the third latch LD3 outputs; the input terminal of the third comparator COMP31 A inputs the third latch data signal RData3 output from the third latch LD3, and input terminal B inputs the first latch data signal RData1 output from the first latch LD1. The first comparator COMP12 , the second comparator COMP23 and the third comparator COMP31 are all 8-bit comparators of the same type, and are used to compare two input data, and output 1 if the comparison result is the same, otherwise output 0.

The output terminals of the first comparator COMP12 , the second comparator COMP23 and the third comparator COMP31 respectively output a first comparison result signal C12 , a second comparison result signal C23 and a third comparison result signal C31 .

At the same time, the first latch data signal RData1 and the first comparison result signal C12 are respectively connected to the two input terminals of the 2-input AND gate FData1, when the first latch data signal RData1 is equal to the second latch data signal RData2, FData1 outputs The value of the first latch data signal RData1, otherwise FData1 outputs 0x00;

The second latch data signal RData2 and the second comparison result signal C23 are respectively connected to the two input terminals of the 2-input AND gate FData2, when the second latch data signal RData2 is equal to the third latch data signal RData3, FData2 outputs the second Latch the value of the data signal RData2, otherwise FData2 outputs 0x00;

The third latch data signal RData3 and the third comparison result signal C31 are respectively connected to the two input terminals of the 2-input AND gate FData3, when the third latch data signal RData3 is equal to the first latch data signal RData1, FData3 outputs the third Latch the value of the data signal RData3, otherwise FData3 outputs 0x00.

The outputs of the three 2-input AND gates FData1, FData2 and FData3 are input to a 3-input OR gate, and the output of the 3-input OR gate is the majority voting result data FinalDataOut.

The output ends of the first comparator COMP12, the second comparator COMP23, and the third comparator COMP31 are respectively connected to the three input ends of the 3-input OR gate FStatus, when the first comparison result signal C12, the second comparison result signal C23, the second When at least one of the three comparison result signals C31 has a value of 1, it means that at least two backup data are the same, and the output of the 3-input OR gate FStatus is 1, which means that there is a correct result output; when the first comparison result signal When C12, the second comparison result signal C23, and the third comparison result signal C31 are all 0, the output of the 3-input OR gate FStatus is 0, indicating that no correct result is output.

The first zero-delay read signal OEL0, the second read signal OER, and the output of the 3-input OR gate FStatus are respectively input to a 3-input NAND gate NAND3B1 with 1 inverting input terminal and 2 non-inverting input terminals, where The first zero-latency read signal OEL0 is connected to the reverse input terminal, and the 3-input NAND gate NAND3B1 outputs the majority voting result strobe signal FinalReadOutControl.

The first zero-delay read signal OEL0, the second read signal OER, and the output of the 3-input OR gate FStatus are respectively input to a 3-input NAND gate NAND3B2 with 2 inverting input terminals and 1 non-inverting input terminal, wherein The first zero-delay read signal OEL0 and the output of the 3-input OR gate FStatus are respectively connected to two inverting input terminals, and the 3-input NAND gate NAND3B2 outputs an error status signal ErrorStatus.

The execution sequence of the majority voting module 181 can be divided into three situations: no error data, one backup data error and three backup data are different.

Fig. 25, Fig. 26, and Fig. 27 are respectively when the majority voting module of the asynchronous random static memory triple-mode redundant controller of the present invention has no error data, when there is one error data (taking the second backup data as an example), three Schematic diagram of the timing when the data are different.

FIG. 28 is a schematic structural diagram of an error correction sequence module of an asynchronous random static memory triple-mode redundant controller of the present invention.

As shown in FIG. 28 , preferably, the error correction timing module 183 includes three input terminals that respectively input the first comparison result signal C12, the second comparison result signal C23, and the third comparison result signal C31. The 3-input NAND gate, the input terminal The 3-input AND gates are respectively connected to the output terminals of the three 3-input NAND gates, and the AND input terminals are respectively connected to the input terminals of the second read signal OER and the 2-input OR gates to the output terminals of the 3-input AND gates.

The 2-input OR gate has an inverting input terminal and a non-inverting input terminal, the second read signal OER is connected to the inverting input terminal, and the output terminal outputs the fourth write signal WER2.

The three 3-input NAND gates each have two inverting input terminals and a non-inverting input terminal, wherein the non-inverting input terminal of the first 3-input NAND gate inputs the second comparison result C23, and the output terminal Output the seventh strobe signal EAddrS1; the non-reverse input terminal of the second 3-input NAND gate inputs the third comparison result C31, and the output terminal outputs the eighth strobe signal EAddrS2; the non-reverse input of the third 3-input NAND gate The terminal inputs the first comparison result C12, and the output terminal outputs the ninth strobe signal EAddrS3.

FIG. 29 is a timing schematic diagram of the error correction sequence module of the ARAM triple-mode redundant controller of the present invention (take the second backup data error as an example).

When the fourth write signal WER2 is low level and the seventh strobe signal EAddrS1 is low level, the first backup data is wrong, and the error correction address module 127 will output the address of the first backup data; when the fourth write signal WER2 is low Level, when the eighth strobe signal EAddrS2 is low level, the second backup data is wrong, and the error correction address module 127 will output the address of the second backup data; when the fourth write signal WER2 is low level, the ninth strobe signal When EAddrS3 is at low level, the third backup data is wrong, and the error correction address module 127 will output the address of the third backup data.

Preferably, a first input buffer 191 and a first tri-state output buffer 193 controlled by the first AND module 145 are provided between the first data signal pin 1021 and the second data signal pin 1022 . A second input buffer 195 is provided between the second data signal pin 1022 and the input end of the majority voting module 181 . A second tri-state output buffer controlled by the majority voting result strobe signal FinalReadOutControl is set between the two output ends of the output majority voting result data FinalDataOut and the majority voting result strobe signal FinalReadOutControl and the first data signal pin 1021 197.

When the second write signal WER is valid, the first tri-state output buffer 193 outputs the data input by the microprocessor through the first data signal pin 1021 and the first input buffer 191 to the second data signal pin 1022 .

When the majority voting result strobe signal FinalReadOutControl is valid, the second tri-state output buffer 197 outputs the majority voting result data FinalDataOut to the first data signal pin 1021 .

Preferably, the asynchronous random static memory triple-mode redundancy controller also includes a first chip select signal pin 1061 connected to the chip select signal pin of the microprocessor and a first chip select signal pin 1061 connected to the chip select signal of the random static memory The pins are connected to the second chip selection signal pin 1062 , and the first chip selection signal pin 1061 is connected to the second chip selection signal pin 1062 .

FIG. 30 is a schematic diagram of the write operation sequence of the three-mode redundant controller of the asynchronous random SRAM according to the present invention.

As shown in Figure 30, when using the ARAM triple-mode redundancy controller of the present invention to perform a write operation, the writing sequence of the microprocessor remains unchanged, and the ARAM triple-mode redundancy controller A write operation of the microprocessor is converted into a write operation of three addresses, and only the backup addresses need to be changed in turn.

When using the triple-mode redundant controller of the asynchronous random static memory of the present invention to perform the read operation, there are three situations: no error data, one backup data error and three backup data different from each other.

FIG. 31 is a schematic diagram of the timing sequence of the read operation of the ARAM triple-mode redundant controller of the present invention when there is no error data.

As shown in Figure 31, in the case of no erroneous data, the read sequence of the microprocessor remains unchanged, and the asynchronous random static memory triple-mode redundancy controller converts one read operation of the microprocessor into three The read operation of a backup address, and then the three read data are subjected to triple-mode redundancy processing, and the correct data is output to the microprocessor.

FIG. 32 is a schematic diagram of the timing sequence of the read operation when there is an error data in the ARAM triple-mode redundant controller of the present invention.

As shown in Figure 32, in the case of an error data, the read timing of the microprocessor remains unchanged, and the asynchronous random static memory triple-mode redundancy controller converts a read operation of the microprocessor into The read operation of the three backup addresses is followed by triple-modular redundancy processing for the read three data, outputting the correct data to the microprocessor, and writing back the correct data to the asynchronous random static memory.

FIG. 33 is a schematic diagram of the timing sequence of the read operation when the three data of the three-mode redundant controller of the asynchronous random static memory of the present invention are different.

As shown in Figure 33, in the case that the three data are different, the read timing of the microprocessor remains unchanged, and the asynchronous random static memory triple-mode redundant controller converts a read operation of the microprocessor to Convert the read operation into three backup addresses, and then perform three-mode redundancy processing on the three read data. Since the three data are different, the correct result cannot be output. The asynchronous random static memory triple-mode redundancy controller The error status signal pin ErrorStatus returns a high level to indicate the error status.

FIG. 34 is a schematic diagram of the internal signal sequence of the write operation of the triple-mode redundant controller of the asynchronous random static memory of the present invention.

As shown in FIG. 34, inside the triple-mode redundant controller of the asynchronous random static memory, the writing operation includes the following steps:

(1) The external microprocessor starts the write operation: the microprocessor inputs the low-level effective first write signal WEL through the first write signal pin 1031 to start the write operation, and simultaneously inputs the first write signal WEL through the first data signal pin 1021 A data signal DataL is input to the first address signal AddrL through the first address signal pin 1011 , and the first read signal OEL related to the read operation is at a high level. The address calculation module 121 calculates the first address signal AddrL to obtain addresses of three data backup areas: AddrL, AddrL+Offset and AddrL+2Offset. At this time, the write address output by the triple-mode redundant controller of the asynchronous random static memory is AddrL, that is, to start writing the first backup data.

(2) The write signal arrives after a delay of 1: at this time, the address output by the asynchronous random static memory triple-mode redundancy controller will switch to AddrL+Offset, that is, start to write the second backup data.

(3) The write signal arrives after a delay of 2: at this time, the address output by the ARAM triple-mode redundancy controller will switch to AddrL+2Offset, that is, start to write the third backup data.

(4) The write signal arrives after a delay of 3: at this time, the address output by the asynchronous random static memory triple-mode redundant controller will switch to the no-operation address 0xFFFF, and the third write signal WER1 output at the same time becomes high level, indicating that Stop writing operations.

(5) End of write signal: the first write signal WEL becomes high level, and the write operation of the external microprocessor ends.

FIG. 35 is a schematic diagram of the internal signal sequence when the read operation of the triple-mode redundancy controller of the asynchronous random static memory of the present invention has no error data.

As shown in FIG. 35 , in the triple-mode redundant controller of the asynchronous random static memory, when the read operation has no error data, the read operation includes the following steps:

(1) The external microprocessor starts the read operation: the microprocessor inputs the first read signal OEL which is effective at low level through the first read signal pin 1041 to start the read operation, and simultaneously inputs the first address signal pin 1011 through the first address signal pin 1011 to start the read operation. An address signal AddrL, and the first write signal WEL related to the write operation is high level. The address calculation module 121 calculates the first address signal AddrL to obtain addresses of three data backup areas: AddrL, AddrL+Offset and AddrL+2Offset. At this time, the read address output by the ARAM triple redundancy controller is AddrL, that is, it starts to read the first backup data.

(2) Read signal delay 1 arrives: at this moment, described asynchronous random static memory three-mode redundant controller latches the first backup data, and the address of output will be switched to AddrL+Offset, promptly starts to read the second backup data .

(3) The read signal arrives after a delay of 2: at this moment, the three-mode redundancy controller of the asynchronous random static memory latches the second backup data, and the output address will be switched to AddrL+2Offset, that is, open

(4) The read signal arrives after a delay of 3: at this moment, the three-mode redundancy controller of the asynchronous random static memory latches the third backup data, and the output address will be switched to the no-operation address 0xFFFF, and the output second read The signal OER becomes high level, indicating that the read operation is stopped. Since the three backup data read are identical, the majority voting module 181 will output a correct result at this time.

(5) End of read signal: the first input read signal OEL becomes high level, and the read operation of the external microprocessor ends.

FIG. 36 is a schematic diagram of the internal signal sequence when there is an error data in the read operation of the triple-mode redundancy controller of the asynchronous random static memory of the present invention.

As shown in Figure 36, inside the triple-mode redundant controller of the asynchronous random static memory, when the read operation has an error data, the read operation includes the following steps:

(1) The external microprocessor starts the read operation: the microprocessor inputs the first read signal OEL which is effective at low level through the first read signal pin 1041 to start the read operation, and simultaneously inputs the first address signal pin 1011 through the first address signal pin 1011 to start the read operation. An address signal AddrL, and the first write signal WEL related to the write operation is high level. The address calculation module 121 calculates the first address signal AddrL to obtain addresses of three data backup areas: AddrL, AddrL+Offset and AddrL+2Offset. At this time, the read address output by the ARAM triple redundancy controller is AddrL, that is, it starts to read the first backup data.

(2) Read signal delay 1 arrives: at this moment, described asynchronous random static memory three-mode redundant controller latches the first backup data, and the address of output will be switched to AddrL+Offset, promptly starts to read the second backup data .

(3) Read signal delay 2 arrives: at this moment, described asynchronous random static memory three-mode redundancy controller latches the second backup data, and the address of output will be switched to AddrL+2Offset, promptly starts to read the 3rd backup data .

(4) The arrival of the read signal with a delay of 3: at this time, the ARAM triple-mode redundancy controller latches the third backup data, and the second read signal OER output at the same time becomes a high level, indicating that the read operation is stopped. Taking the second backup data error as an example here, because the first backup data read is the same as the third backup data, the second backup data is wrong, and the majority voting module 181 will output the correct result at this time, and the error correction sequence module 183 and The error correction address module 127 re-outputs the second backup address and the correct result to complete the error correction operation.

(5) End of read signal: the first input read signal OEL becomes high level, and the read operation of the external microprocessor ends.

FIG. 37 is a schematic diagram of the timing sequence of internal signals when the three data in the read operation of the asynchronous random static memory triple-mode redundant controller of the present invention are different.

As shown in FIG. 37 , in the three-mode redundant controller of the asynchronous random static memory, when the three data of the read operation are different, the read operation includes the following steps:

(1) The external microprocessor starts the read operation: the microprocessor inputs the first read signal OEL which is effective at low level through the first read signal pin 1041 to start the read operation, and simultaneously inputs the first address signal pin 1011 through the first address signal pin 1011 to start the read operation. An address signal AddrL, and the first write signal WEL related to the write operation is high level. The address calculation module 121 calculates the first address signal AddrL to obtain addresses of three data backup areas: AddrL, AddrL+Offset and AddrL+2Offset. At this time, the read address output by the ARAM triple redundancy controller is AddrL, that is, it starts to read the first backup data.

(2) Read signal delay 1 arrives: at this moment, described asynchronous random static memory three-mode redundant controller latches the first backup data, and the address of output will be switched to AddrL+Offset, promptly starts to read the second backup data .

(3) Read signal delay 2 arrives: at this moment, described asynchronous random static memory three-mode redundancy controller latches the second backup data, and the address of output will be switched to AddrL+2Offset, promptly starts to read the 3rd backup data .

(4) The arrival of the read signal with a delay of 3: at this time, the ARAM triple-mode redundancy controller latches the third backup data, and the second read signal OER output at the same time becomes a high level, indicating that the read operation is stopped. Since the first backup data, the second backup data and the third backup data read are different, the majority voting module 181 will not be able to output the correct result, and the error correction operation cannot be realized by the error correction sequence module 183 and the error correction address module 127 At this time, the output address will switch to the no-operation address 0xFFFF, and a high-level signal will be output through the error status signal pin ErrorStatus to indicate that the data is wrong and there is no valid data output.

(5) End of read signal: the first input read signal OEL becomes high level, and the read operation of the external microprocessor ends.

In order to verify the feasibility of the scheme of the present invention, the inventor of the present invention carried out principle verification on Xilinx Spartan3 series FPGA. First of all, in the Xilinx ISE integrated development environment, use the schematic diagram to input each module and overall structure of this scheme. Then write the corresponding simulation test input file, and simulate the above-mentioned various types of operations in turn.

Fig. 38 is a simulation waveform diagram of the write operation of the triple-mode redundant controller of the asynchronous random static memory of the present invention.

Fig. 39 is a simulation waveform diagram when there is no error data in the read operation of the asynchronous random static memory triple-mode redundant controller of the present invention.

Fig. 40 is a simulation waveform diagram when the first data error occurs in the read operation of the ARAM triple-mode redundant controller of the present invention.

Fig. 41 is a simulation waveform diagram when the second data error occurs in the read operation of the triple-mode redundant controller of the asynchronous random static memory of the present invention.

Fig. 42 is a simulation waveform diagram when the third data error occurs in the read operation of the ARAM triple-mode redundancy controller of the present invention.

Fig. 43 is a simulation waveform diagram when the three data of the read operation of the asynchronous random static memory triple-mode redundant controller of the present invention are different.

By comparing with the internal signal timing diagrams shown in Figures 34-37 of the flow analysis of the aforementioned solution of the present invention, the timing of the simulation results is completely consistent with the timing of the principle analysis, thus verifying the correctness of the solution of the present invention.

In addition, after the verification of the above-mentioned simulation principle is passed, the inventor also designed a dedicated test circuit to carry out actual hardware testing of the technical solution of the present invention. The test circuit uses XilinxSpartan3 series FPGA to design the three-mode redundant controller of asynchronous random static memory. The dual-port asynchronous random static memory is selected, and the AT89LS52 microcontroller uses the triple-mode redundant controller of asynchronous random static memory to implement For routine read and write operations, the test system performs single event flip simulation injection and data verification readback on the dual-port asynchronous random static memory through the PSoC chip. Through hardware test and verification, it is shown that the asynchronous random static memory triple-mode redundant controller designed by the scheme of the present invention is feasible and reliable.

In summary, the three-mode redundant controller for asynchronous random static memory provided by the present invention is set between the system microprocessor and the asynchronous random static memory as a bridge, and the write/read operation of the microprocessor to the asynchronous random static memory is automatically Convert to triple-mode redundancy and three-out-of-three majority voting operation sequence, realize automatic processing of triple-mode redundancy fault tolerance, thereby replacing the processing of triple-mode redundancy in the system software, reducing the burden on the system software, and without changing the system The microprocessor software structure reduces the complexity of system software design and ensures reliability at the same time. To sum up, the three-mode redundant controller for asynchronous random static memory of the present invention has the advantages of simple structure, strong compatibility, wide application range, and high reliability.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: it can still be Modifications are made to the technical solutions described in the foregoing embodiments, or equivalent replacements are made to some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims (17)

1. An asynchronous random access static memory triple modular redundancy controller, comprising:

the address signal processing unit is respectively connected with the address signal pins of the microprocessor and the random static memory, and is used for receiving and processing the first address signal output by the microprocessor and outputting a second address signal containing a write operation address, a read operation address or an error correction operation address to the random static memory;

the write signal processing unit is respectively connected with the microprocessor and a write signal pin of the random static memory, is connected with the address signal processing unit, and is used for receiving and processing a first write signal output by the microprocessor, outputting a second write signal to the random static memory, and outputting a gating signal for gating the write operation address to the address signal processing unit;

the read signal processing unit is respectively connected with the microprocessor and the read signal pins of the random static memory, is connected with the address signal processing unit, and is used for receiving and processing a first read signal output by the microprocessor, outputting a second read signal to the random static memory, and outputting a gating signal for gating the read operation address to the address signal processing unit;

the triple-modular redundancy error correction unit is respectively connected with a data signal pin and an error state signal pin of the microprocessor and a data signal pin of the random static memory, is respectively connected with the read signal processing unit, the write signal processing unit and the address signal processing unit, and is used for carrying out triple-modular redundancy comparison on input triple backup data, outputting error state signals and comparison result data to the microprocessor and carrying out error correction on the backup data stored in the random static memory;

the write signal processing unit includes:

the input end of the writing signal delay module is connected with a first writing signal pin, and the four output ends respectively output a first zero delay writing signal, a second delay writing signal, a third delay writing signal and a fourth delay writing signal and are used for outputting the first writing signal in a multi-stage delay way; the first write signal pin is connected with a write signal pin of the microprocessor;

the four output ends respectively output a third write signal, a first strobe signal, a second strobe signal and a third strobe signal, and are used for calculating and outputting a third write signal of write operation and a strobe signal of a strobe write operation address;

the input end of the first AND module is connected with the write time sequence module and the triple-modular redundancy error correction unit, and the output end of the first AND module is connected with a second write signal pin and is used for outputting a second write signal, specifically comprising a third write signal for outputting write operation in a write operation time sequence and a fourth write signal for outputting error correction operation in an error correction operation time sequence; the second write signal pin is connected with the write signal pin of the random static memory.

2. The triple modular redundancy controller of claim 1, wherein the write signal delay module comprises a first delay submodule, a second delay submodule, and a third delay submodule; the first write signal directly obtains and outputs the first zero-delay write signal, the second delay write signal is obtained and output through the delay of the first delay submodule, the third delay write signal is obtained and output through the delay of the first delay submodule and the second delay submodule, and the fourth delay write signal is obtained and output through the delay of the first delay submodule, the second delay submodule and the third delay submodule.

3. The triple-modular redundancy controller of claim 1, wherein the write timing module comprises three 4-input nand gates respectively connected to four inputs of the write timing module, and a 3-input and gate having three inputs respectively connected to outputs of the three 4-input nand gates; the output results of the three 4-input NAND gates are the first strobe signal, the second strobe signal and the third strobe signal respectively, and the output result of the 3-input AND gate is the third write signal;

the first 4-input NAND gate is provided with an inverted input end and three non-inverted input ends, and the first zero-delay write signal is input to the inverted input end; the second 4-input NAND gate is provided with two inverted input ends and two non-inverted input ends, and the first zero-delay write signal and the second delay write signal are input into the inverted input ends; the third 4-input nand gate has three inverting inputs and a non-inverting input, the inverting inputs inputting the first zero-delayed write signal, the second delayed write signal and the third delayed write signal.

4. The triple modular redundancy controller of claim 1, wherein the read signal processing unit comprises:

the input end of the read signal delay module is connected with a first read signal pin, and the four output ends of the read signal delay module respectively output a first zero delay read signal, a second delay read signal, a third delay read signal and a fourth delay read signal and are used for outputting the first read signal in a multi-stage delay manner; the first reading signal pin is connected with a reading signal pin of the microprocessor;

the four input ends of the read sequence module are respectively connected with the four output ends of the read signal delay module, and the four output ends respectively output the second read signal, the fourth strobe signal, the fifth strobe signal and the sixth strobe signal, and are used for calculating and outputting the second read signal of read operation and the strobe signal of strobe read operation address; the output end for outputting the second reading signal is connected with a second reading signal pin, and the second reading signal pin is connected with a reading signal pin of the random static memory.

5. The triple modular redundancy controller of claim 4, wherein the read signal delay module comprises a fourth delay submodule, a fifth delay submodule, and a sixth delay submodule; the first reading signal directly obtains and outputs the first zero delay reading signal, the second delay reading signal is obtained and output through the delay of the fourth delay submodule, the third delay reading signal is obtained and output through the delay of the fourth delay submodule and the fifth delay submodule, and the fourth delay reading signal is obtained and output through the delay of the fourth delay submodule, the fifth delay submodule and the sixth delay submodule.

6. The triple modular redundancy controller of claim 4, wherein the read timing module comprises three 4-input nand gates respectively connected to four inputs of the read timing module, and a 3-input and gate having three inputs respectively connected to outputs of the three 4-input nand gates; the output results of the three 4-input nand gates are the fourth strobe signal, the fifth strobe signal and the sixth strobe signal respectively, and the output result of the 3-input and gate is the second read signal;

the fourth 4-input NAND gate is provided with an inverted input end and three non-inverted input ends, and the first zero-delay reading signal is input to the inverted input end; the fifth 4 input NAND gate is provided with two inverted input ends and two non-inverted input ends, and the first zero delay reading signal and the second delay reading signal are respectively input to the inverted input ends; the sixth 4 input nand gate has three inverting input terminals and a non-inverting input terminal, and the inverting input terminals respectively input the first zero delay read signal, the second delay read signal, and the third delay read signal.

7. The triple modular redundancy controller of claim 4, wherein the address signal processing unit comprises:

the address calculation module is connected with the first address signal pin at the input end, and three output ends respectively output a first backup address signal, a second backup address signal and a third backup address signal and are used for calculating and outputting three backup addresses corresponding to the first address signal; the first address signal pin is connected with an address signal pin of the microprocessor;

a write address module, six input ends of which are respectively connected with three output ends of the write timing sequence module for outputting gating signals and three output ends of the address calculation module, and the output ends of which output write operation addresses, and are used for receiving and processing the first gating signal, the second gating signal and the third gating signal, and the first backup address signal, the second backup address signal and the third backup address signal of the write operation timing sequence, and outputting the write operation addresses;

the six input ends of the read address module are respectively connected with the three output ends of the read time sequence module for outputting gating signals and the three output ends of the address calculation module, and the output ends of the read address module are used for outputting a read operation address and receiving and processing the fourth gating signal, the fifth gating signal and the sixth gating signal as well as the first backup address signal, the second backup address signal and the third backup address signal of the read operation time sequence and outputting the read operation address;

an error correction address module, seven input ends of which are respectively connected with an output end of the read timing sequence module for outputting a second read signal, three output ends of the triple modular redundancy error correction unit for outputting a gating signal and three output ends of the address calculation module, wherein the output ends output an error correction operation address, and are used for receiving and processing the second read signal, the error correction operation address gating signal output by the triple modular redundancy error correction unit, and the first backup address signal, the second backup address signal and the third backup address signal of an error correction operation timing sequence, and outputting the error correction operation address;

the three input ends of the second AND module are respectively connected with the output end of the write address module, the output end of the read address module and the output end of the error correction address module, and the output ends of the second AND module are connected with a second address signal pin and used for outputting the write operation address in a write operation time sequence, outputting the read operation address in a read operation time sequence and outputting the error correction operation address in an error correction operation time sequence; the second address signal pin is connected with an address signal pin of the random static memory.

8. The triple modular redundancy controller of claim 7, wherein the address calculation module divides a triple calculation circuit into three paths to perform parallel calculation processing on the first address signal, the first address signal is directly obtained through a buffer and outputs the first backup address signal, the first adder adds an offset to the first backup address signal and outputs the second backup address signal, and the second adder adds twice the offset to the second backup address signal and outputs the third backup address signal; and the offset is obtained by calculating the address bit width of the asynchronous random static memory.

9. The triple modular redundancy controller of claim 8, wherein the address bit width of the sram is N bits, and the Offset is calculated by:

10. the triple modular redundancy controller of claim 7, wherein the write address module controls the output of the first backup address signal, the second backup address signal, and the third backup address signal through three 2-input or gates and the first strobe signal, the second strobe signal, and the third strobe signal, respectively, and combines the outputs of the three 2-input or gates through a 3-input and gate, thereby implementing the continuous output of the first backup address signal, the second backup address signal, and the third backup address signal of the write operation timing.

11. The triple modular redundancy controller of claim 7, wherein the read address module controls the outputs of the first backup address signal, the second backup address signal, and the third backup address signal through three 2-input or gates and the fourth strobe signal, the fifth strobe signal, and the sixth strobe signal, respectively, and combines the outputs of the three 2-input or gates through a 3-input and gate, thereby implementing the continuous output of the first backup address signal, the second backup address signal, and the third backup address signal of the read operation timing.

12. The triple modular redundancy controller of claim 7, wherein the error correction address module comprises three 2-input or gates, a 3-input and gate, and a tenth 2-input or gate having an inverting input, and outputs the first backup address signal, the second backup address signal, and the third backup address signal are controlled by the three 2-input or gates, a seventh strobe signal, an eighth strobe signal, and a ninth strobe signal, respectively, the output terminals of the three 2-input or gates are connected to the input terminals of the 3-input and gate, the non-inverting input terminal of the tenth 2-input or gate is connected to the output terminal of the 3-input and gate, the inverting input terminal is connected to the input terminal of the second read signal, and the output terminal outputs the error correction operation address.

13. The triple modular redundancy controller of claim 7, wherein the triple modular redundancy error correction unit comprises:

the six input ends of the majority voting module are respectively connected with the output end of the reading time sequence module for outputting a second reading signal, the four output ends of the reading signal delay module and a second data signal pin, and the six output ends of the majority voting module respectively output a first comparison result signal, a second comparison result signal, a third comparison result signal, majority voting result data, a majority voting result gating signal and an error state signal, and are used for performing triple-modular redundancy comparison on the triple backup data input through the second data signal pin, outputting a comparison result, and outputting an error state signal and comparison result data to the microprocessor; the first comparison result signal, the second comparison result signal and the third comparison result signal are result signals of pairwise comparison of the three backup data; the second data signal pin is connected with a data signal pin of the random static memory; the two output ends for outputting the majority voting result data and the majority voting result gating signal are connected with a first data signal pin, and the first data signal pin is connected with a data signal pin of the microprocessor; the output end for outputting the error state signal is connected with a first error state signal pin, and the first error state signal pin is connected with a second error state signal pin of the microprocessor;

the four input ends of the error correction timing sequence module are respectively connected with the output end of the reading timing sequence module for outputting a second reading signal and the three output ends of the majority voting module for outputting a comparison result signal, the four output ends of the error correction timing sequence module are respectively connected with the input ends of the first and module and the three input ends of the error correction address module for inputting a gating signal, and the error correction timing sequence module is used for receiving and processing the second reading signal, the first comparison result signal, the second comparison result signal and the third comparison result signal, outputting a fourth write signal of error correction operation to the first and module, and outputting a seventh gating signal, an eighth gating signal and a ninth gating signal for gating an error correction operation address to the error correction address module.

14. The triple-modular redundancy controller of claim 13, wherein the majority voting module latches the three backup data through three latches, respectively, and compares the three backup data two by two through three comparators to obtain the first comparison result signal, the second comparison result signal, and the third comparison result signal, and then obtains and outputs the majority voting result data, the majority voting result gating signal, and the error status signal through logic circuit operation, respectively.

15. The triple-modular redundancy controller of claim 13, wherein the error correction timing module comprises three inputs, a 3-input nand gate for inputting the first comparison result signal, the second comparison result signal and the third comparison result signal, a 3-input and gate having inputs connected to the outputs of the three 3-input nand gates, and a 2-input or gate having inputs connected to the input for inputting the second read signal and the output of the 3-input and gate;

the 2 input or gate output end outputs the fourth write signal;

the three 3-input nand gates are respectively provided with two inverted input ends and a non-inverted input end, wherein the non-inverted input end of the first 3-input nand gate inputs the second comparison result, the output end outputs the seventh gating signal, the non-inverted input end of the second 3-input nand gate inputs the third comparison result, the output end outputs the eighth gating signal, the non-inverted input end of the third 3-input nand gate inputs the first comparison result, and the output end outputs the ninth gating signal.

16. The triple modular redundancy controller of claim 13, wherein a first input buffer and a first tri-state output buffer controlled by the first and module are disposed between the first data signal pin and the second data signal pin; a second input buffer is arranged between the second data signal pin and the input end of the majority voting module; a second tri-state output buffer controlled by the majority voting result gating signal is arranged between the two output ends for outputting the majority voting result data and the majority voting result gating signal and the first data signal pin;

when the second write signal is valid, the first tri-state output buffer outputs the data input by the microprocessor through the first data signal pin and the first input buffer to the second data signal pin;

and when the majority voting result gating signal is effective, the second tri-state output buffer outputs the majority voting result data to the first data signal pin.

17. The triple-modular redundancy controller of any one of claims 1 to 16, further comprising a first chip select signal pin connected to a chip select signal pin of the microprocessor and a second chip select signal pin connected to a chip select signal pin of the sram, wherein the first chip select signal pin is connected to the second chip select signal pin.