CN104241201B - A kind of method of integrated power device and control device - Google Patents
A kind of method of integrated power device and control device Download PDFInfo
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- CN104241201B CN104241201B CN201410430704.2A CN201410430704A CN104241201B CN 104241201 B CN104241201 B CN 104241201B CN 201410430704 A CN201410430704 A CN 201410430704A CN 104241201 B CN104241201 B CN 104241201B
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- 238000000034 method Methods 0.000 title claims abstract description 66
- 239000002184 metal Substances 0.000 claims abstract description 114
- 229910052751 metal Inorganic materials 0.000 claims abstract description 114
- 238000005516 engineering process Methods 0.000 claims abstract description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 49
- 229910052710 silicon Inorganic materials 0.000 claims description 49
- 239000010703 silicon Substances 0.000 claims description 49
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims description 38
- 238000005530 etching Methods 0.000 claims description 20
- 239000000758 substrate Substances 0.000 claims description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 12
- 229920005591 polysilicon Polymers 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 8
- 238000002360 preparation method Methods 0.000 claims description 8
- 230000008021 deposition Effects 0.000 claims description 5
- 230000003647 oxidation Effects 0.000 claims description 5
- 238000007254 oxidation reaction Methods 0.000 claims description 5
- 238000011049 filling Methods 0.000 claims description 4
- 238000011946 reduction process Methods 0.000 claims description 3
- 125000006850 spacer group Chemical group 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 2
- 239000010931 gold Substances 0.000 claims description 2
- 229910052737 gold Inorganic materials 0.000 claims description 2
- 230000008901 benefit Effects 0.000 abstract description 6
- 238000004519 manufacturing process Methods 0.000 abstract description 6
- 238000005538 encapsulation Methods 0.000 abstract description 5
- 230000009467 reduction Effects 0.000 abstract description 2
- 230000005611 electricity Effects 0.000 description 6
- 230000000694 effects Effects 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 210000000170 cell membrane Anatomy 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000024241 parasitism Effects 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/808—Bonding techniques
- H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
- H01L2224/80895—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The present invention relates to ic manufacturing technology field, more particularly to a kind of method of integrated power device and control device, by the method for the present invention, power chip and control chip separate design and making can be made, ensure its performance, the advantage of cost, while not using line and conventional encapsulation with regard to the interconnection of control circuit and chip device can be completed；And by shared thinning and back metal technique, further reduction manufacturing cost, while the performance of power device is improve, and due to having thickeied the metal of power device back-side drain, so as to further reduce the conducting resistance of device.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly to a kind of integrated power device and control device side
Method.
Background technology
Field-effect transistor (FET) is widely used in various electronic circuits.It belongs to voltage controlled semiconductor device
Part.It is high by (10 with input resistance7~1015Ω), noise is small, low in energy consumption, dynamic range is big, be easily integrated, without second breakdown
The advantages of phenomenon, safety operation area field width, the powerful competitor as bipolar transistor and power transistor.And field is imitated
Should pipe control circuit preparation technology it is but completely different with FET, however, the work of FET depend on control electricity
The connection on road.So, while obtain FET controls a technological difficulties of the circuit as this area with it.
At present, main solution has three classes：Discrete device solution, multi-chip module solution and single-chip
Solution.
Discrete device solution is by separately designing and making vertical MOS FET power devices and control circuit core
Piece, is packaged and is connected with device pad (weld pad) using metal lead wire afterwards, is drawn with forming the input of each chip, output
Pin, and be welded on pcb board.But because each device, chip are required to encapsulation, scheme takes up room greatly, and draws due to using
Line, brings larger stray inductance, increased power consumption, and reduce the anti-electromagnetic interference capability of device and bring larger
Voltage overshoot etc., so as to have impact on the reliability of device, and due to employing lead more long between discrete device, increased
Parasitic capacitance, power consumption and current over pulse.
Multi-chip module solution (MCM) is by separately designing according to special applications demand and making vertical-type power
Device and control circuit chip, take the different chip packages that special encapsulation scheme will not encapsulated together afterwards.But should
Scheme needs that the source region of device is placed in the back side of silicon chip, and the source region with device in conventional vertical-type power device is placed in silicon chip
Front is inconsistent, therefore existing vertical-type power device is not applied for the program.And multiple chips are spread out connect in the plane,
The area of occupancy is larger.
Single chip solution is, by carrying out special chip design and making, power device and control circuit to be integrated in same
In chip, whole technique is two kinds of summations of the technique of device, and device have passed through unwanted technique, high cost.And power device
The compatibility of the performance of part and control device is not strong, have impact on the optimization of both sides' device performance.
Therefore, a kind of method for how finding integrated power MOSFET element and control device, effectively to evade above-mentioned asking
Inscribe the direction that research is endeavoured as those skilled in the art.
The content of the invention
For a kind of method that above-mentioned problem, the present invention disclose integrated power device and control device.
A kind of method of integrated power device and control device, wherein, comprise the following steps：
The power chip that providing preparation has power device has the control chip of control circuit, and the power chip with preparation
On be provided with drain region；
The power chip is vertically bonded to using front bonding technology a bonding chip is formed on the control chip
Afterwards, the back side to the power chip carries out reduction process；
The metal structure Chong Die with the drain region is formed at the back side of the power chip；
Continue at and etch the bonding chip on the exposed back side of the power chip and form some silicon holes, and in described
Metal is filled in some silicon holes, to form the interconnection line that the power device is electrically connected with the control circuit, and will
The metal lead wire that the power device, the control circuit are electrically connected with the bonding chip external structure respectively.
The method of above-mentioned integrated power device and control device, wherein, include the step of prepare the metal structure：
In the metal level of backside deposition one of the power chip；
Technique is performed etching to the metal level, the metal structure is formed.
Above-mentioned integrated power device and the method for control device, wherein, the power device includes source region electrode and grid
Pole electrode, the control circuit includes the first coordination electrode and the second coordination electrode；
Methods described also includes：
Etch the bonding chip and form the first silicon hole, the second silicon hole and the 3rd silicon hole, and first silicon is logical
Hole is exposed the part surface of the part surface of the gate electrode and the first coordination electrode, and second silicon hole will
The part surface of the source region electrode is exposed, and the 3rd silicon hole gives the part surface of second coordination electrode
Exposure；
The interconnection line is formed after filling metal in first silicon hole, the second silicon hole and the 3rd silicon hole
With the metal lead wire, the metal lead wire include the first metal lead wire and the second metal lead wire；
Wherein, the gate electrode and first coordination electrode are electrically connected by the interconnection line, by described the
One metal lead wire electrically connects the source region electrode with the bonding chip external structure, by second metal lead wire by institute
The second coordination electrode is stated to be electrically connected with the bonding chip external structure.
Above-mentioned integrated power device and the method for control device, wherein, methods described also includes：
Metal electrode is formed respectively in the upper surface of the interconnection line, the first metal lead wire, the second metal lead wire.
Above-mentioned integrated power device and the method for control device, wherein, methods described also includes：
After forming the interconnection line, the first metal lead wire, the second metal lead wire；
Continue depositing electrode metal film to be covered with by the back side of the power device；
Partial etching is located at the electrode metal film above the interconnection line and the metal lead wire, with the interconnection
Line top formed the first metal electrode, form above first metal lead wire the second metal electrode, in second metal
Lead top forms the 3rd metal electrode.
Above-mentioned integrated power device and the method for control device, wherein, methods described also includes：
After the front of the control chip forms first medium film, the power chip is hung down using front bonding technology
Directly it is bonded to and the bonding chip is formed on the control chip.
Above-mentioned integrated power device and the method for control device, wherein, the power device is vertical-type power
MOSFET element.
Above-mentioned integrated power device and the method for control device, wherein, the power chip includes：
Substrate；
Positioned at the epitaxial layer of the substrate top surface；
Positioned at the p-well substrate of the epitaxial layer upper surface；
It is arranged in the p-well substrate and extends to the gate trench in the epitaxial layer；
Grid structure in the gate trench, the grid structure includes groove gate oxidation films and the covering ditch
Groove gate oxidation films bottom and its trench polysilicon Si-gate of side wall；
It is arranged at the grid structure top and the gate electrode electrically connected with the trench polysilicon Si-gate；And
It is arranged at the grid structure top and the source region electrode isolated with the grid structure by dielectric layer.
Above-mentioned integrated power device and the method for control device, wherein, methods described also includes：
After forming the metal structure, in one layer of second medium film of backside deposition of the power chip, to described the
Second medium film is patterned technique, and the partial rear of the power chip is exposed；
Power chip described in the second medium film as mask etching, to form some silicon holes.
Above-mentioned integrated power device and the method for control device, wherein, methods described also includes：
If power chip to the dielectric layer surface stops forming hondo described in the second medium film as mask etching
Groove；
Spacer medium layer is respectively formed in the sidewall surfaces of some grooves；
Continue etching some grooves and form some silicon holes.
Above-mentioned integrated power device and the method for control device, wherein, methods described is applied to some power chips
Interconnection is realized with a control chip or a power chip and some control chips are realized into interconnection.
Foregoing invention has the following advantages that or beneficial effect：
Integrated power device disclosed by the invention and the method for control device, can make power chip and control chip mutual
Independent design and making, it is ensured that its performance, the advantage of cost, while not using line, does not use conventional encapsulation just to complete to control
The interconnection of circuit processed and chip device.And by shared thinning and back metal technique, further reduction manufacturing cost, while
The performance of power device is improve, and due to having thickeied the metal of power device back-side drain, so as to further reduce device
Conducting resistance.
Specific brief description of the drawings
By the detailed description made to non-limiting example with reference to the following drawings of reading, the present invention and its feature, outward
Shape and advantage will become more apparent.Identical mark indicates identical part in whole accompanying drawings.Not can according to than
Example draws accompanying drawing, it is preferred that emphasis is show purport of the invention.
Fig. 1-13 is the flowage structure schematic diagram of the method for integrated power device and control device in the embodiment of the present invention；
Figure 14 is the flow chart of the method for integrated power device and control device in the embodiment of the present invention.
Specific embodiment
The present invention is further illustrated with specific embodiment below in conjunction with the accompanying drawings, but not as limit of the invention
It is fixed.
As shown in figure 14, the invention provides a kind of integrated power device and the method for control device, comprise the following steps：
The power chip that providing preparation has power device has the control chip of control circuit with preparation, and is set on power chip
It is equipped with drain region；
Power chip is vertically bonded to using front bonding technology after forming a bonding chip on control chip, to power
The back side of chip carries out reduction process；
The metal structure Chong Die with drain region is formed at the back side of the power chip；
Continue the etching bonding chip from the power chip exposed back side and form some silicon holes, and in some silicon holes
Filling metal, to form the interconnection line that power device is electrically connected with control circuit, and power device, control circuit is distinguished
The metal lead wire electrically connected with bonding chip external structure.
Specifically, as represented in figures 1 through 14, the present embodiment is related to a kind of method of integrated power device and control device, the party
Method can be applied to for some power chips and control chip to realize interconnection or by a power chip and some control chips
Realize interconnection.Specifically, the method comprises the following steps：
Step S1, there is provided the power chip that preparing has power device has the control chip of control circuit, the power with preparation
Drain region is provided with chip；Power device includes source region electrode 201 (i.e. source metal) and gate electrode 202, and (i.e. grid is golden
Category), control circuit includes the first coordination electrode 51 and the second coordination electrode 52；In an embodiment of the present invention, the power device
It is vertical-type power MOSFET element, and the power chip and control chip design and making are separate such that it is able to
Ensure power device and the control respective performance of circuit and cost advantage.
Further, the structure of the power chip as shown in Figure 1a, specifically includes substrate 12, covers the upper surface of substrate 12
Epitaxial layer 13, the p-well region 16 of covering epitaxial layer 13 upper surface, it is arranged in p-well region 16 and extends to epitaxial layer 13
(grid structure includes the ditch of covering groove bottom and its side wall for gate trench, the grid structure being arranged in the gate trench
The trench polysilicon Si-gate 151 of groove gate oxidation films 141 and the bottom of covering groove gate oxidation films 141 and its side wall), be arranged at adjacent gate
The N source regions 17 in p-well region 16 between the structure of pole, the p-well contact zone 18 between N source regions 17, it is arranged at trench polysilicon
The top of Si-gate 151 and be connected by polysilicon line 152 with trench polysilicon Si-gate 151 gate electrode 202, be arranged at polysilicon
The oxide-film 142 of being isolated polysilicon line 152 and p-well region 16 between line 152 and p-well region 16 and it is arranged at
The top of trench polysilicon Si-gate 151 and the source region electrode 201 isolated with trench polysilicon Si-gate 151 by dielectric layer 19, and grid electricity
Isolate also through dielectric layer 19 between pole 202 and source region electrode 201.
Preferably, the thickness of power device bears at least thick 0.2 μm (such as 0.2 μ of thickness of the epitaxial layer of voltage than device
M, 0.3 μm, 0.5 μm or 1 μm etc.).
The structure of control chip as shown in Figure 1 b, specifically includes silicon substrate 2, the control circuit on silicon substrate 2 and is situated between
Plasma membrane 6, the active and passive device 3 being arranged in control circuit media film 6, the control being arranged in control circuit media film 6
Electric circuit metal layer 4 and it is arranged at some coordination electrodes in control circuit media film 6 and on control electric circuit metal layer 4
And metal connecting line, wherein above-mentioned coordination electrode includes the first coordination electrode 51 and the second coordination electrode 52 and other control electricity
Pole 5.
, vertically be bonded to power chip using front bonding technology a bonding chip formed on control chip by step S2,
Will power chip be bonded face-to-face with control chip together with (bonding).Specifically, first in the front of control chip
(controlling the upper surface of circuit media film 6) carries out the deposition of first medium film 31, then using front bonding technology by power
By the first medium film 21, vertical being bonded together to form bonding chip to chip face-to-face with control chip, using two kinds of differences
The longitudinal stack of functional chip, so as to reduce area, structure as shown in Figure 2.
Step S3, by the use of the silicon chip (i.e. silicon substrate 2) of control chip as support, is carried out thinning to the back side of power chip
Technique, substrate 12 is thinned to the most minimal thickness of power device needs, so as to the performance for further increasing device (is reduced and led
Be powered resistance, improves radiating efficiency), and improve thinning and its technique afterwards production yields, structure as shown in Figure 3.
Step S4, a metal level 41 is deposited in the back side (i.e. the upper surface of substrate 12) of power chip, forms as shown in Figure 4
Structure.
Step S5, in after one layer of photoresist 42 of upper surface spin coating of metal level 41, carries out photoetching and etching technics, will not be with
Drain region forms the metal level 41 for overlapping and etches away, it is also possible to the quarter of metal layer on back 41 in the region of perforate will be needed on the drain region of part
Eating away (not shown), structure as shown in Figure 5.
Step S6, removes photoresist 42, and remaining metal level 41 forms (work(of the covering on drain region Chong Die with drain region
The back side of rate chip) metal structure 41 (hereinafter referred to as remaining metal level 41 be metal structure 41), and in the back of the body of power chip
Face deposits one layer of second medium film 32 and is covered with by the exposed upper surface of the upper surface of metal structure 41 and substrate 12, such as
Structure shown in Fig. 6.
Step S7, bonding chip interconnection area and lead areas (region where non-drain region) to the second medium film
After 32 are patterned technique (including photoetching and etching technics), the part surface of substrate 12 is exposed, as shown in Figure 7
Structure.
Step S8, with remaining second medium film 32 be mask etching power chip to dielectric layer 16 upper surface stop with
Some grooves (being not entirely shown in figure) are formed, in an embodiment of the present invention, technology of the invention is illustrated in order to clearer
Scheme, only carries out follow-up elaboration by taking part of trench (first groove 331, the groove 333 of second groove 332 and the 3rd) as an example；
The isolation for being respectively formed layer in the side wall of first groove 331, the side wall of second groove 332 and the sidewall surfaces of the 3rd groove 333 is situated between
Matter layer, after follow-up filling metal, metal to be realized isolating with the silicon of power device, while can also be by spacer medium layer
Further to control to be subsequently formed the CD of silicon hole.In an embodiment of the present invention, the process of first groove 331 is formed in etching
In, oxide-film 142 is partly or entirely etched away；Structure as shown in Figure 8.
Step S9, continues to form the first silicon hole 351 (i.e. first in etching first groove 331 to the first coordination electrode 51
Coordination electrode 51 is partially etched), form the second silicon hole 352 (i.e. in etching second trenches 332 to the source region electrode 201
Source region electrode 201 is partially etched), form the 3rd silicon hole 352 (i.e. in the etching coordination electrode 52 of the 3rd groove 333 to the second
Second coordination electrode 52 is partially etched), and the first silicon hole 351 is electric by the part surface of gate electrode 202 and the first control
The part surface of pole 51 is exposed, it is preferred that the exposed part surface of gate electrode 202 is the gate electrode 202
Side wall, the second silicon hole 352 is exposed the part surface of source region electrode 201, and the 3rd silicon hole 353 is by the second coordination electrode
52 part surface is exposed, structure as shown in Figure 9.
Step S10, deposited metal 36 with full of the first silicon hole 351, the second silicon hole 352 and the 3rd silicon hole 353,
And the upper surface of the covering second medium of metal 36 film 32, structure as shown in Figure 10.
Step S11, carries out flatening process to remove the metal 36 on second medium film 32, the first silicon hole
Full of being formed power device and the interconnection line for controlling circuit to electrically connect after metal in 351, metal is full of in the second silicon hole 352
The first metal lead wire that power device is electrically connected with bonding chip external structure is formed afterwards, full of gold in the 3rd silicon hole 353
The second metal lead wire that circuit will be controlled to be electrically connected with bonding chip external structure is formed after category.In other words, i.e., by interconnection
Line can electrically connect the coordination electrode 51 of gate electrode 202 and first, by the first metal lead wire can by source region electrode 201 with
Bonding chip external structure is electrically connected, can be by the second coordination electrode 52 and bonding chip external structure by the second metal lead wire
Electrical connection；Structure as shown in figure 11.
Step S12, is removed the second medium film 32 being located at the drain region back side of power device by photoetching, etching technics
Remove, in other words, the upper surface second medium film 32 of metal level 41 will be located at and removed；Structure as shown in figure 12.
Step S13, continues depositing electrode metal film and (electrode metal film covering is covered with by the back side of power device
The upper surface of the upper surface of deielectric-coating 32, the upper surface of metal level 41, interconnection line, the first metal lead wire and the second metal lead wire),
Partial etching is located at the electrode metal film on second medium film 32, to cause that the electrode metal film on interconnection line is formed
First metal electrode 374, electrode metal film on the first metal lead wire form the second metal electrode 372, positioned at second
Electrode metal film on metal lead wire forms the 3rd metal electrode 371, the shape of electrode metal film 37 above grid structure
Into the 4th metal electrode 373, and the first metal electrode 374, the second metal electrode 372, the 3rd metal electrode 371 and the 4th metal
It is mutually isolated between electrode 373, structure as shown in fig. 13 that.
Wherein, first coordination electrode 51 and power device of circuit will be controlled by the first metal electrode 374 and interconnection line
Gate electrode 202 electrically connect and draw, by the second metal electrode 372 and the first metal lead wire by the source region electricity of power device
Pole 201 is drawn, and by the 3rd metal electrode 371 and the 3rd metal lead wire the coordination electrode 52 of circuit will be controlled to draw, so that logical
Cross using silicon hole technology, realize the interconnection of two difference in functionality chips, eliminate the line between device, reduce the electricity of parasitism
Sense and electric capacity.
In sum, the present invention is bonded and through hole interconnection using the superposition of chip, reduces line, parasitic capacitance and electricity
Sense, improves the performance of device and the reliability of technical scheme, and instead of conventional encapsulation, reduces volume and area, improves
Reliability and performance, and the present invention is smaller than MCM mode areas, and shared thinning and back metal technique, further reduce
Manufacturing cost.
It should be appreciated by those skilled in the art that those skilled in the art combine prior art and above-described embodiment can be with
The change case is realized, be will not be described here.Such change case has no effect on substance of the invention, not superfluous herein
State.
Presently preferred embodiments of the present invention is described above.It is to be appreciated that the invention is not limited in above-mentioned
Particular implementation, wherein the equipment and structure that do not describe in detail to the greatest extent are construed as giving reality with the common mode in this area
Apply；Any those of ordinary skill in the art, in the case where technical solution of the present invention ambit is not departed from, all using the disclosure above
Methods and techniques content make many possible variations and modification to technical solution of the present invention, or be revised as equivalent variations etc.
Effect embodiment, this has no effect on substance of the invention.Therefore, every content without departing from technical solution of the present invention, foundation
Technical spirit of the invention still falls within the present invention to any simple modification, equivalent variation and modification made for any of the above embodiments
In the range of technical scheme protection.
Claims (10)
1. a kind of method of integrated power device and control device, it is characterised in that comprise the following steps：
The power chip that providing preparation has power device has the control chip of control circuit with preparation, and is set on the power chip
It is equipped with drain region；
The power chip is vertically bonded to using front bonding technology after forming a bonding chip on the control chip, it is right
The back side of the power chip carries out reduction process；
The metal structure Chong Die with the drain region is formed at the back side of the power chip；
Continue at and the bonding chip is etched on the exposed back side of the power chip form some silicon holes, and in described some
Metal is filled in silicon hole, to form the interconnection line that the power device is electrically connected with the control circuit, and will be described
The metal lead wire that power device, the control circuit are electrically connected with the bonding chip external structure respectively；
The power device includes source region electrode and gate electrode, and the control circuit includes the first coordination electrode and the second control
Electrode；
Methods described also includes：
Etch the bonding chip and form the first silicon hole, the second silicon hole and the 3rd silicon hole, and first silicon hole will
The part surface of the part surface of the gate electrode and the first coordination electrode is exposed, and second silicon hole will be described
The part surface of source region electrode is exposed, and the 3rd silicon hole gives the part surface of second coordination electrode cruelly
Dew；
The interconnection line and institute are formed after filling metal in first silicon hole, the second silicon hole and the 3rd silicon hole
Metal lead wire is stated, the metal lead wire includes the first metal lead wire and the second metal lead wire；
Wherein, the gate electrode and first coordination electrode are electrically connected by the interconnection line, by first gold medal
Category lead electrically connects the source region electrode with the bonding chip external structure, by second metal lead wire by described the
Two coordination electrodes are electrically connected with the bonding chip external structure.
2. the method for integrated power device as claimed in claim 1 and control device, it is characterised in that prepare the metal knot
The step of structure, includes：
In the metal level of backside deposition one of the power chip；
Technique is performed etching to the metal level, the metal structure is formed.
3. the method for integrated power device as claimed in claim 1 and control device, it is characterised in that methods described is also wrapped
Include：
Metal electrode is formed respectively in the upper surface of the interconnection line, the first metal lead wire, the second metal lead wire.
4. the method for integrated power device as claimed in claim 3 and control device, it is characterised in that methods described is also wrapped
Include：
After forming the interconnection line, the first metal lead wire, the second metal lead wire；
Continue depositing electrode metal film to be covered with by the back side of the power device；
Partial etching is located at the electrode metal film above the interconnection line and the metal lead wire, with the interconnection line
It is square form the second metal electrode into the first metal electrode, above first metal lead wire, in second metal lead wire
Top forms the 3rd metal electrode.
5. the method for integrated power device as claimed in claim 1 and control device, it is characterised in that methods described is also wrapped
Include：
After the front of the control chip forms first medium film, using front bonding technology by the power chip axial bond
It is bonded to and the bonding chip is formed on the control chip.
6. the method for integrated power device as claimed in claim 1 and control device, it is characterised in that the power device is
Vertical-type power MOSFET element.
7. the method for integrated power device as claimed in claim 6 and control device, it is characterised in that the power chip bag
Include：
Substrate；
Positioned at the epitaxial layer of the substrate top surface；
Positioned at the p-well substrate of the epitaxial layer upper surface；
It is arranged in the p-well substrate and extends to the gate trench in the epitaxial layer；
Grid structure in the gate trench, the grid structure includes groove gate oxidation films and the covering trench gate
Oxide-film bottom and its trench polysilicon Si-gate of side wall；
It is arranged at the grid structure top and the gate electrode electrically connected with the trench polysilicon Si-gate；And
It is arranged at the grid structure top and the source region electrode isolated with the grid structure by dielectric layer.
8. the method for integrated power device as claimed in claim 7 and control device, it is characterised in that methods described is also wrapped
Include：
After forming the metal structure, in one layer of second medium film of backside deposition of the power chip, to the second medium
Film is patterned technique, and the partial rear of the power chip is exposed；
Power chip described in the second medium film as mask etching, to form some silicon holes.
9. the method for integrated power device as claimed in claim 8 and control device, it is characterised in that methods described is also wrapped
Include：
Power chip described in the second medium film as mask etching stops forming some grooves to the dielectric layer surface；
Spacer medium layer is respectively formed in the sidewall surfaces of some grooves；
Continue etching some grooves and form some silicon holes.
10. the method for integrated power device as claimed in claim 1 and control device, it is characterised in that methods described application
Realize interconnecting in by some power chips and a control chip realization interconnection or by a power chip and some control chips.
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| CN107731770B (en) * | 2017-09-29 | 2019-01-29 | 长鑫存储技术有限公司 | Dynamic random access memory of chip size wafer level scale package and manufacturing method thereof |
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| CN1976056A (en) * | 2005-11-30 | 2007-06-06 | 夏普株式会社 | Semiconductor device and its manufacturing method |
| CN102201418A (en) * | 2010-03-25 | 2011-09-28 | 索尼公司 | Semiconductor apparatus, method of manufacturing semiconductor apparatus, method of designing semiconductor apparatus, and electronic apparatus |
| CN102971851A (en) * | 2010-07-09 | 2013-03-13 | 佳能株式会社 | Solid-state image pickup device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1976056A (en) * | 2005-11-30 | 2007-06-06 | 夏普株式会社 | Semiconductor device and its manufacturing method |
| CN102201418A (en) * | 2010-03-25 | 2011-09-28 | 索尼公司 | Semiconductor apparatus, method of manufacturing semiconductor apparatus, method of designing semiconductor apparatus, and electronic apparatus |
| CN102971851A (en) * | 2010-07-09 | 2013-03-13 | 佳能株式会社 | Solid-state image pickup device |
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