CN104183475B - Grid structure and forming method thereof - Google Patents

Abstract

A gate structure and a forming method thereof, the forming method of the gate structure comprising: providing a substrate; forming a gate dielectric layer, a buffer layer on the surface of the gate dielectric layer, and a buffer layer on the surface of the buffer layer in sequence on the surface of the substrate For the gate layer, the material of the buffer layer is amorphous. The gate structure and its forming method can reduce the distribution range of the threshold voltage of the transistor.

Description

Gate structure and method of forming the same

technical field

The invention relates to the technical field of semiconductors, in particular to a gate structure and a forming method thereof.

Background technique

When the size of semiconductor devices is gradually shrinking, because the traditional polysilicon gate has many problems in the case of small size, such as polysilicon depletion effect, high resistivity and incompatibility of high K gate dielectric, etc., metal gate technology has begun to be applied to ultra-deep submicron Device preparation.

The metal gate replaces the polysilicon gate, and a high-K material is used as the gate dielectric layer, which can further reduce the thickness of the gate dielectric layer and improve the performance of the transistor. However, as the size of transistors continues to shrink, the manufacturing process and physical properties of high-k metal gate transistors are also facing more and more challenges.

Among them, the variation of the threshold voltage of the transistor is one of the important problems. Statistical measurements have found that for transistors with the same parameters formed by the same process, the threshold voltages of each transistor are not exactly the same, but are distributed within a certain range, resulting in the difference between the threshold voltages of different transistors, with a larger threshold Voltage distribution range. A wide spread of transistor threshold voltages degrades the performance of the integrated circuit and increases the power consumption of the chip. The larger the threshold voltage distribution range of the transistor, the greater the impact on the performance of the integrated circuit.

Therefore, there is a need for a method that can reduce the distribution range of threshold voltages of multiple transistors formed by the same process, and reduce the impact of differences in the threshold voltages of transistors on integrated circuits.

Contents of the invention

The problem to be solved by the present invention is to provide a gate structure and its forming method, which can reduce the distribution range of threshold voltages of multiple transistors formed by the same process.

In order to solve the above problems, the present invention provides a gate structure and a method for forming the gate structure. The method for forming the metal gate includes: providing a substrate; forming a gate dielectric layer on the surface of the substrate; The buffer layer and the gate layer located on the surface of the buffer layer, the material of the buffer layer is amorphous.

Optionally, the buffer layer is made of amorphous silicon.

Optionally, the buffer layer is formed by chemical vapor deposition process, wherein the reaction gas used includes: one or more of Si ₂ H ₆ , Si ₃ H ₈ , Si ₄ H ₈ , Si ₅ H ₁₀ , the reaction The temperature is 200°C to 400°C.

Optionally, the buffer layer is doped with carbon.

Optionally, the carbon concentration is 1E19atom/cm ³ -1E22atom/cm ³ .

Optionally, the buffer layer is formed by a chemical vapor deposition process. In the chemical vapor deposition process, the silicon source gas used includes: Si ₂ H ₆ , Si ₃ H ₈ , Si ₄ H ₈ , Si ₅ H ₁₀ One or more of them, the carbon source gas used includes one or more of C ₂ H ₂ , C ₂ H ₄ , and C ₃ H ₆ , and the reaction temperature is 300°C to 400°C.

Optionally, the buffer layer is doped with nitrogen.

Optionally, the nitrogen concentration is 1E19atom/cm ³ -1E22atom/cm ³ .

Optionally, the buffer layer is formed by a chemical vapor deposition process. In the chemical vapor deposition process, the silicon source gas used includes: Si ₂ H ₆ , Si ₃ H ₈ , Si ₄ H ₈ , Si ₅ H ₁₀ One or more of them, the nitrogen source gas used includes one or more of N ₂ O and NO, and the reaction temperature is 300°C-400°C.

Optionally, the buffer layer has a thickness of 1 nm˜5 nm.

Optionally, the buffer layer is formed by chemical vapor deposition process, plasma chemical vapor deposition process, liquid phase epitaxy process or sputtering deposition process.

Optionally, the material of the gate layer is Ni, Ti, TiN, TaN or TaC.

Optionally, the grain size of the material of the gate layer is less than 3 nm.

Optionally, an atomic layer deposition process is used to form the gate layer made of TiN, the reaction gases used are TiCl ₄ and NH ₃ , the reaction temperature is 200°C-600°C, and the reaction pressure is 0.2-2 Torr.

Optionally, the method further includes: forming spacers on the sidewall surfaces of the gate layer, the buffer layer and the gate dielectric layer, and forming a source and a drain in the uncovered substrate on both sides of the spacers.

In order to solve the above problems, the present invention also provides a gate structure, including: a substrate; a gate dielectric layer located on the surface of the substrate; a buffer layer located on the surface of the gate dielectric layer, and the material of the buffer layer is amorphous Morphology; a gate layer located on the surface of the buffer layer.

Optionally, the buffer layer is made of silicon.

Optionally, the buffer layer is doped with carbon or nitrogen, and the concentration of the carbon or nitrogen is 1E19atom/cm ³ -1E22atom/cm ³ .

Optionally, the buffer layer has a thickness of 1 nm to 5 nm

Optionally, the grain size of the material of the gate layer is less than 3 nm.

Compared with the prior art, the technical solution of the present invention has the following advantages:

In the technical solution of the present invention, in the process of forming the gate structure, a buffer layer is formed on the surface of the gate dielectric layer, the material of the buffer layer is in an amorphous state, and the atoms in the buffer layer are in a state of disordered arrangement. Subsequently, a gate layer is formed on the surface of the buffer layer. Since the structure of the gate layer is affected by the arrangement of atoms on the surface of the buffer layer at the bottom, the atoms at the bottom of the gate layer near the buffer layer also present an amorphous state. On the part of the gate layer that is close to the surface and away from the buffer layer, due to the orderly arrangement of atoms tending to low energy, there will be a mixed structure of some crystal grains and amorphous forms, but due to the influence of the underlying amorphous structure, the The size of some grains is also small. Therefore, in the subsequently formed gate layer, the grain size and quantity are relatively low, and the difference in work function caused by the grain size and quantity is reduced, so that the threshold voltage distribution range of the transistor formed by the above method is also reduced.

Further, the buffer layer is doped with elements such as carbon or nitrogen, because the atomic radii of the carbon, nitrogen and silicon atoms are different, in the process of forming the buffer layer, Si-Si, Si-C, C-C, Si -N, N-C, N-N and other different chemical bonds, the lengths of the chemical bonds are all different, resulting in lattice mismatch between different lattices, effectively inhibiting the crystallization of the buffer layer, thereby facilitating the formation of the amorphous Morphological buffer layer.

Description of drawings

1 to 5 are schematic diagrams of the formation process of the gate structure in the first embodiment of the present invention;

6 to 9 are schematic views of the formation process of the gate structure in the second embodiment of the present invention.

detailed description

As mentioned in the background art, the threshold voltage distribution of existing transistors is relatively wide, which will affect the performance of integrated circuits.

The inventors found that the threshold voltage of existing transistors is related to the work function of the gate of the transistor. Due to the difference in the formation process of the gate of the transistor, the work function of the gate changes, resulting in the distribution of the threshold voltage of the transistor in the within a certain range.

The inventor found through further research that the work function of the transistor gate is related to the size of crystal grains in the gate material. Since the crystal grains in the gate material have different crystal orientations, different crystal orientations will lead to uneven distribution of polarization charges on the interface between the gate and the gate dielectric layer, resulting in changes in the work function of the gate material. Crystal grains with different sizes or orientations have different work functions, so that the threshold voltages of multiple transistors formed by the same process will be different, showing a certain distribution.

The inventor found through further research that the larger the crystal grains of the gate material of the transistor, the greater the difference between the work functions of different grains, and thus the greater the impact on the work function of the entire gate. Reducing the size or number of grains in the gate material can reduce this difference, so that the work function of the gate is more stable, and the distribution of the threshold voltage of the transistor can be reduced. However, in the process of forming a transistor in the prior art, there is usually an annealing process at a higher temperature, such as an annealing process for forming a source and a drain, which will crystallize the gate material and form larger crystal particles.

The invention provides a gate structure and a forming method thereof, and forms a gate with a relatively low crystal particle size, thereby reducing the distribution range of threshold voltages of multiple transistors formed by the same process.

In order to make the above objects, features and advantages of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

first embodiment

Referring to FIG. 1 , a substrate 100 is provided, and a gate dielectric material layer 200 is formed on the surface of the substrate 100 .

The material of the substrate 100 is semiconductor materials such as silicon, germanium, silicon germanium, gallium arsenide, etc., which may be a bulk material or a composite structure such as silicon-on-insulator. In this embodiment, the material of the substrate 100 is silicon.

In other embodiments of the present invention, a shallow trench isolation structure is further formed in the substrate 100 .

The material of the gate dielectric material layer 200 is a high-K dielectric material, such as HfO ₂ , La ₂ O ₃ , HfSiON or HfAlO ₂ . In this embodiment, the material of the gate dielectric material layer 200 is HfO ₂ . The gate dielectric material layer 200 has a thickness of 10 angstroms to 50 angstroms.

Referring to FIG. 2 , a buffer material layer 300 is formed on the surface of the gate dielectric material layer 200 .

The material of the buffer material layer 300 is an amorphous material. The formation process of the buffer material layer 300 may be a process such as chemical vapor deposition, plasma chemical vapor deposition, liquid phase epitaxy or sputtering deposition. The buffer material layer 300 has a thickness of 1 nm˜5 nm, preferably 2 nm.

In one embodiment of the present invention, the material of the buffer material layer 300 is amorphous silicon. The amorphous silicon is formed by chemical vapor deposition process, wherein the silicon source gas used is one or more of Si ₂ H ₆ , Si ₃ H ₈ , Si ₄ H ₈ , Si ₅ H ₁₀ , and the reaction pressure is 0.1 Torr to 0.5 Torr, the reaction temperature is 300°C to 600°C, preferably 500°C. The buffer layer is formed by depositing at a higher temperature, and the crystal grain size formed by the silicon is relatively small and is not easy to form crystals, so that an amorphous silicon layer with better quality can be formed as the buffer material layer 300 .

The inventors found that adding a gas source containing carbon or nitrogen during the process of forming the amorphous silicon can prevent silicon from crystallizing during the deposition process. Due to the different atomic radii of carbon, nitrogen and silicon atoms, the atomic radius of carbon is 77 picometers, that of nitrogen is 70 picometers, and that of silicon is 111 picometers. During the deposition process, different chemical bonds such as Si-Si, Si-C, C-C, Si-N, N-C, and N-N will be formed in the buffer material layer 300, and the lengths of the three chemical bonds are different, so that During the deposition process of the buffer material layer, lattice mismatch between different crystal lattices is caused, thereby reducing the size of crystal grains in the buffer material layer. The size of the grains decreases as the concentration of carbon atoms or nitrogen atoms increases, and when the concentration of carbon atoms or atoms reaches a certain concentration, an amorphous buffer material layer will be formed.

In this embodiment, the buffer material layer 300 is made of carbon-doped amorphous silicon. Specifically, the buffer material layer is formed by chemical vapor deposition process, wherein the silicon source gas used is Si ₃ H ₈ , the carbon source gas used is C ₂ H ₂ , the carrier gas is H ₂ , and the reaction pressure is 1 torr- 500 Torr, the reaction temperature is 300°C-600°C, such as 350°C, the flow rate of Si ₃ H ₈ is 50 sccm-1000 sccm, the flow rate of C ₂ H ₂ is 10 sccm-500 sccm, and the flow rate of H ₂ is 100 sccm-5000 sccm. The buffer material layer 300 formed has a thickness of 1 nm˜5 nm, preferably, the buffer material layer 300 has a thickness of 2 nm. The concentration of carbon atoms in the buffer material layer 300 is 1E19atom/cm ³ -1E22atom/cm ³ , preferably, the concentration of carbon atoms is 1E20atom/cm ³ . In other embodiments of the present invention, the silicon source gas can also be one or more of Si ₂ H ₆ , Si ₃ H ₈ , Si ₄ H ₈ , Si ₅ H ₁₀ , and the carbon source gas can be One or more of C ₂ H ₂ , C ₂ H ₄ , and C ₃ H ₆ .

In other embodiments of the present invention, the buffer material layer 300 is made of nitrogen-doped amorphous silicon. Wherein, the concentration of nitrogen is 1E19atom/cm ³ -1E22atom/cm ³ , preferably, the concentration of carbon atoms is 1E20atom/cm ³ . The nitrogen-doped amorphous silicon can be formed by chemical vapor deposition process, wherein the silicon source gas used can be one or more of Si ₂ H ₆ , Si ₃ H ₈ , Si ₄ H ₈ , Si ₅ H ₁₀ , The nitrogen source gas can be one or both of N ₂ O and NO.

In other embodiments of the present invention, the material of the buffer material layer 300 may be amorphous silicon doped with carbon and nitrogen at the same time, wherein the total concentration of carbon and nitrogen is 1E19 atom/cm ³ -1E22 atom/cm ³ .

In other embodiments of the present invention, the buffer material layer 300 may also be formed by a plasma chemical vapor deposition process, a liquid phase epitaxy process or a sputtering deposition process.

Referring to FIG. 3 , a gate material layer 400 is formed on the surface of the buffer material layer 300 .

The material of the gate material layer 300 is Ni, Ti, TiN, TaN or TaC, and the gate material layer 400 is formed by atomic layer deposition (ALD).

In this embodiment, the material of the gate material layer 400 is TiN.

Specifically, in the process of forming the gate material layer 300 by atomic layer deposition (ALD), the precursor gases are TiCl ₄ and NH ₃ , which are alternately transported into the reaction chamber in a pulsed manner, He is used as the auxiliary gas, and the reaction temperature is 400°C to 650°C, preferably above 550°C. In other embodiments of the present invention, the metal precursor gas containing Ti may also be diethylaminotetratitanium (TDEAT) or dimethylaminotetratitanium (TDMAT).

When the gate material layer 400 is formed on the surface of the buffer material layer 300, since the buffer material layer 300 is in an amorphous state, the atomic arrangement is in a disordered state, resulting in disordered atomic arrangement on the surface of the buffer material layer 300 . The ALD process grows upward layer by layer in the form of monoatomic layers on the surface of the buffer material layer 300, and transfers the lattice structure upward layer by layer. Therefore, the structure of the gate material layer 400 is influenced by the underlying buffer material layer. 300 is strongly influenced by the lattice arrangement. Since the atomic arrangement on the surface of the buffer material layer 300 is disordered, the atomic arrangement of the atomic layer formed on the surface of the buffer material layer 300 is also in a disordered state. With the gradual growth of the atomic layer, this disordered structure gradually Pass up. Although, as the thickness of the gate material layer 400 increases, in the gate material layer 400 away from the surface of the buffer material layer, the atoms will gradually tend to form crystal grains of a certain size in an orderly arrangement with low energy through diffusion, However, there are still a lot of amorphous forms in the gate material layer 400 . Compared with the prior art, the gate material layer 400 is a mixture of amorphous and crystal grains, and the crystal grains are smaller in size. In the gate material layer 400 , the grain size of the gate material is less than 3 nm.

Moreover, in the prior art, the gate material layer is directly formed on the surface of the gate dielectric material layer. Since the atomic arrangement on the surface of the gate dielectric material layer is relatively orderly, the atoms tend to be more orderly arranged in the subsequent deposition process. , will first form an island-shaped crystal nucleus on the surface of the gate dielectric material layer, and then continue to grow on the surface of the crystal nucleus to form a gate material layer, so the size and number of crystal grains in the formed gate material layer will be relatively large . However, in the technical solution of the present invention, due to the disordered arrangement of the surface atoms of the buffer material layer, no or only a small amount of island-shaped nuclei are formed on the surface of the buffer material layer, so that the subsequently formed gate material layer The size and number of medium grains will be smaller.

Referring to FIG. 4, the gate material layer 400, the buffer material layer 300 and the gate dielectric material layer 200 (please refer to FIG. 3) are etched to form a gate stack structure, which includes a gate dielectric layer 201, buffer layer 301 and gate layer 401.

Specifically, the method for forming the gate stack structure is: forming a patterned mask layer on the surface of the gate material layer, the patterned mask layer covers the position of the gate stack structure, and The mask layer is used as a mask, and the gate material layer 400, the buffer material layer 300 and the gate dielectric material layer 200 are etched by a dry etching process (please refer to FIG. 3 ) to form the gate dielectric layer 201 and the buffer layer 301. and gate layer 401 .

Compared with the prior art, in the gate layer 401 located on the surface of the buffer layer 301, the number and size of crystal grains are correspondingly reduced, so that multiple gate structures are formed by using the above process, and the gate structures in the gate structure The difference in the work function of the gate layer is small, so the difference in the threshold voltage of the subsequently formed transistor is also small, and the distribution range of the threshold voltage of the transistor becomes smaller.

Referring to FIG. 5 , a spacer 500 is formed on the sidewall surface of the gate stack structure, and the source-drain ion implantation is performed on the semiconductor substrate 100 using the spacer 500 and the gate stack structure as a mask, and The annealing treatment activates the implanted ions to form a source 101 and a drain 102 in the semiconductor substrate 100 on both sides of the gate structure.

The material of the sidewall 500 is silicon nitride. The sidewall 500 may also be a multi-layer stack structure, such as a stack structure of silicon oxide and silicon nitride.

In other embodiments of the present invention, it is also possible to first form a first sidewall on the sidewall surface of the gate stack structure, use the first sidewall and the gate structure as a mask, and Lightly doped ion implantation is performed in the semiconductor substrate on the side; then, a second side wall is formed on the surface of the first side wall, and the semiconductor substrate exposed on both sides of the first side wall and the second side wall The source region and the drain region are formed by heavily doped ion implantation, and the lightly doped ion implantation process can reduce the hot carrier injection effect and short channel effect of the MOS transistor.

In other embodiments of the present invention, after the sidewalls are formed on both sides of the gate stack structure, the sidewalls and the gate stack structure are used as a mask to expose both sides of the sidewalls. The semiconductor substrate is etched to form a trench, and the trench is filled with silicon germanium material or silicon carbide material by epitaxial process to form a source region and a drain region. The silicon germanium material or silicon carbide material is in-situ doped with P-type or N-type impurity ions during the epitaxy process. In other embodiments, after the silicon germanium material or the silicon carbide material is formed, the silicon germanium material or the silicon carbide material may be doped with impurity ions by using an ion implantation process. Using the silicon germanium material or silicon carbide material to form the source region and the drain region will cause stress to the crystal lattice of the channel region of the MOS transistor, which is conducive to increasing the mobility of carriers in the channel region and improving the electrical performance of the MOS transistor.

In the prior art, further annealing in the process of forming the source and drain will further increase the grain size in the gate material; and in the technical solution of the present invention, since the gate layer 401 is located in the buffer layer 301 surface, and the buffer layer 301 is amorphous, although annealing treatment will be performed in the subsequent process of forming the source and drain of the transistor, but due to the existence of the buffer layer 301, the buffer layer 301 Doped with elements such as carbon or nitrogen, it is not easy to crystallize during high-temperature annealing, and there is an amorphous and partial grain structure in the gate layer 401 on the surface of the buffer layer 301. During the annealing process, the number of grains It may increase, but the grain size will not increase significantly, and it can still be kept within the range of less than 3nm.

Since the grain size of the material of the gate layer 401 is small, the grain size is less than 3nm, so the grain size of the gate layer 401 has little influence on the work function of the gate layer 401, thereby enabling The threshold voltage distribution range of the formed transistor is small.

second embodiment

In this embodiment, the transistor may also be formed by a gate-last process, and please refer to FIG. 6 to FIG. 9 for specific forming methods.

Please refer to FIG. 6, a dummy gate structure 503 and a sidewall 504 on the sidewall surface of the dummy gate structure 503 are formed on the surface of the semiconductor substrate 500; using the sidewall 504 and the dummy gate structure 503 as a mask, Source-drain ion implantation and annealing are performed in the semiconductor substrate on both sides of the dummy gate structure 503 to form a source electrode 501 and a drain electrode 502; a dielectric layer 600 is formed on the surface of the semiconductor substrate, and the surface of the dielectric layer and the dummy gate The surface of structure 503 is flush.

The material of the dummy gate structure 503 is a polysilicon layer.

The dummy gate structure 503 may include a dummy gate dielectric layer located on the surface of the semiconductor substrate and a polysilicon layer on the surface of the dummy gate dielectric layer, the material of the dummy gate dielectric layer may be a silicon dioxide layer, and the subsequent removal of all While removing the dummy gate structure 503, the dummy gate dielectric layer and the polysilicon layer are removed.

The dummy gate structure 503 may include a gate dielectric layer on the surface of the semiconductor substrate 500 and a polysilicon layer on the surface of the gate dielectric layer, and the gate dielectric layer will be retained later.

Referring to FIG. 7 , the dummy gate structure 503 (please refer to FIG. 6 ) is removed.

The dummy gate structure 503 is removed by a wet or dry etching process to form an opening 601 . Subsequently, a gate stack structure is formed in the opening 601 .

Referring to FIG. 8 , the gate dielectric material layer 602 , buffer material layer 603 and gate material layer 604 are sequentially formed on the surface of the dielectric layer 600 and the surface of the opening 601 (please refer to FIG. 7 ).

Please refer to FIG. 9 , the dielectric layer 600 is used as a polishing stop layer for chemical mechanical polishing, and part of the gate dielectric material layer 602, buffer material layer 603 and gate material layer 604 above the dielectric layer are removed to form a gate stack. structure, the gate stack structure includes: a gate dielectric layer 602a, a buffer layer 603a and a gate layer 604a.

In other embodiments of the present invention, an etching process may also be used to remove part of the gate dielectric material layer 602 , the buffer material layer 603 and the gate material layer 604 above the dielectric layer to form a gate stack structure.

In this embodiment, the gate-last process is adopted, the source and drain of the transistor are formed before forming the gate stack structure, and the source and drain are annealed, so the gate stack structure is subsequently formed In this case, high-temperature annealing treatment is not required to avoid crystallization of materials in the gate layer caused by annealing, thereby further reducing the number and size of crystal grains in the gate layer, and further reducing the distribution range of the threshold voltage of the transistor.

In other embodiments of the present invention, the above method can also be used to form the gate structure of the fin transistor.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims (18)

1. A method for forming a gate structure, comprising: provide the substrate; sequentially forming a gate dielectric layer, a buffer layer on the surface of the gate dielectric layer, and a gate layer on the surface of the buffer layer on the surface of the substrate; Using a high-K material as the gate dielectric layer, the gate layer is a metal gate; The material of the buffer layer is amorphous silicon; The gate material layer is a mixture of both amorphous and crystal grains. 2. The method for forming the gate structure according to claim 1, characterized in that the buffer layer is formed by chemical vapor deposition process, wherein the reaction gases used include: Si ₂ H ₆ , Si ₃ H ₈ , Si ₄ One or more of H ₈ , Si ₅ H ₁₀ , the reaction temperature is 300℃～600℃. 3. The method for forming the gate structure according to claim 1, wherein the buffer layer is doped with carbon. 4 . The method for forming the gate structure according to claim 3 , wherein the carbon concentration is 1E19 atom/cm ³ -1E22 atom/cm ³ . 5. The method for forming the gate structure according to claim ₃ , wherein the buffer layer is formed by a chemical vapor deposition process, and in the chemical vapor deposition process, the silicon source gas used includes: _Si2H6 , Si ₃ H ₈ , Si ₄ H ₈ , Si ₅ H ₁₀ one or more, the carbon source gas used includes one or more of C ₂ H ₂ , C ₂ H ₄ , C ₃ H ₆ , the reaction temperature is 300°C to 600°C. 6 . The method for forming the gate structure according to claim 1 , wherein the buffer layer is doped with nitrogen. 7 . The method for forming the gate structure according to claim 6 , wherein the nitrogen concentration is 1E19 atom/cm ³ -1E22 atom/cm ³ . 8. The method for forming the gate structure according to claim 6, wherein the buffer layer is formed by a chemical vapor deposition process, and in the chemical vapor deposition process, the silicon source gas used includes: Si ₂ H ₆ , Si ₃ H ₈ , Si ₄ H ₈ , Si ₅ H ₁₀ one or more, the nitrogen source gas used includes one or more of N ₂ O and NO, and the reaction temperature is 300℃～600℃ . 9 . The method for forming a gate structure according to claim 1 , wherein the buffer layer has a thickness of 1 nm˜5 nm. 10 . The method for forming the gate structure according to claim 1 , wherein the buffer layer is formed by a chemical vapor deposition process, a plasma chemical vapor deposition process, a liquid phase epitaxy process or a sputtering deposition process. 11 . 11 . The method for forming the gate structure according to claim 1 , wherein the material of the gate layer is Ni, Ti, TiN, TaN or TaC. 12 . The method for forming the gate structure according to claim 1 , wherein the grain size of the material of the gate layer is less than 3 nm. 13 . 13. The method for forming the gate structure according to claim 11, characterized in that the gate layer made of TiN is formed by atomic layer deposition process, the reaction gases are TiCl ₄ and NH ₃ , and the reaction temperature is 200° C. to 600° C. °C, the reaction pressure is 0.2 torr to 2 torr. 14. The method for forming the gate structure according to claim 1, further comprising: forming sidewalls on the sidewall surfaces of the gate layer, the buffer layer and the gate dielectric layer, and forming sidewalls on both sides of the sidewalls. Source and drain electrodes are formed in the uncovered substrate on the side. 15. A gate structure, characterized in that the gate structure comprises: Substrate; a gate dielectric layer located on the surface of the substrate; a buffer layer located on the surface of the gate dielectric layer; a gate layer located on the surface of the buffer layer; Using a high-K material as the gate dielectric layer, the gate layer is a metal gate; The material of the buffer layer is amorphous silicon; The gate material layer is a mixture of both amorphous and crystal grains. 16 . The gate structure according to claim 15 , wherein the buffer layer is doped with carbon or nitrogen, and the concentration of the carbon or nitrogen is 1E19 atom/cm ³ -1E22 atom/cm ³ . 17. The gate structure according to claim 15, wherein the buffer layer has a thickness of 1 nm˜5 nm. 18. The gate structure according to claim 15, wherein the grain size of the material of the gate layer is less than 3 nm.