CN104241130B - PMOS transistor and forming method thereof, semiconductor devices and forming method thereof - Google Patents

Abstract

A PMOS transistor and its forming method, a semiconductor device and its forming method. The forming method of the PMOS transistor includes: providing a semiconductor substrate; forming a first gate structure on the semiconductor substrate; forming first grooves in the semiconductor substrate on both sides of the first gate structure; A stress buffering material layer is formed on the bottom and side walls of the first groove, and the stress buffering material layer is etched to form a stress buffering layer, which is located at the bottom of the first groove by a thickness of The ratio to the thickness of the buffer stress layer on the side wall of the first groove is 1:1-0.8; a main stress layer is formed in the first groove including the buffer stress layer. The performance of the PMOS transistor and semiconductor device formed by the invention is better.

Description

PMOS transistor and its forming method, semiconductor device and its forming method

technical field

The invention relates to the technical field of semiconductor manufacturing, in particular to a PMOS transistor and its forming method, a semiconductor device and its forming method.

Background technique

Metal-oxide-semiconductor (MOS) transistors have become common semiconductor devices in integrated circuits. The MOS transistors include: P-type metal oxide semiconductor (PMOS) transistors and N-type metal oxide semiconductor (NMOS) transistors.

As element density and integration of semiconductor devices increase, the gate size of PMOS transistors or NMOS transistors becomes shorter than before. However, the shortening of the gate size of the PMOS transistor or the NMOS transistor will produce a short channel effect, thereby generating a leakage current and affecting the electrical performance of the CMOS transistor. In the prior art, the carrier mobility is mainly increased by increasing the stress of the channel region of the transistor, thereby increasing the driving current of the transistor and reducing the leakage current in the transistor.

In the prior art, in order to increase the stress of the channel region of the PMOS transistor, a main stress layer made of silicon germanium (SiGe) is formed in the source region and drain region of the PMOS transistor, and the stress formed by the lattice mismatch between silicon and silicon germanium Stress is used to increase the mobility of holes in the channel region of the PMOS transistor, thereby improving the performance of the PMOS transistor.

When forming the above-mentioned PMOS transistor in the existing process, it includes: providing a semiconductor substrate, and forming a gate structure on the semiconductor substrate; forming first grooves in the semiconductor substrate on both sides of the gate structure; A silicon germanium layer is formed in the first groove.

Since the compressive stress in the silicon germanium layer is related to the content of germanium in the silicon germanium layer, in order to increase the stress of the silicon germanium layer, the atomic percentage of germanium in the silicon germanium layer is greater than 30%. However, due to the difference in lattice arrangement between the silicon germanium layer and the semiconductor substrate (the material is silicon), dislocations (Stackfalse) occur between the silicon germanium layer and the semiconductor substrate at the contact surface between the silicon germanium layer and the semiconductor substrate, resulting in The compressive stress in the silicon germanium layer is released before being transmitted to the channel region of the PMOS transistor, and the effect of the silicon germanium layer on increasing the compressive stress in the channel region of the PMOS transistor is limited.

In view of the above problems, prior to forming the silicon germanium layer in the first groove, the prior art forms a buffer stress layer of silicon germanium on the bottom and side walls of the first groove, and makes the atoms occupied by germanium in the buffer stress layer The percentage is kept between 5% and 25% to avoid or reduce dislocations at the contact surface between the silicon-germanium layer and the semiconductor substrate, so that the compressive stress in the silicon-germanium layer can be transmitted to the channel of the PMOS transistor region, increasing the compressive stress in the channel region of the PMOS transistor.

However, when testing the PMOS transistor including the buffer stress layer, it is found that the compressive stress in the channel region of the PMOS transistor does not increase significantly, and the performance of the PMOS transistor can be improved by adding a buffer stress layer between the semiconductor substrate and the silicon germanium layer. The effect is limited.

Contents of the invention

The problem solved by the present invention is to provide a PMOS transistor and its forming method, a semiconductor device and its forming method, improve the mobility of holes in the channel region of the PMOS transistor, and improve the performance of the PMOS transistor and the semiconductor device including the PMOS transistor.

In order to solve the above problems, the present invention provides a method for forming a PMOS transistor, comprising:

Provide semiconductor substrates;

forming a first gate structure on the semiconductor substrate;

forming first grooves in the semiconductor substrate on both sides of the first gate structure;

A buffer stress material layer is formed on the bottom and side walls of the first groove, and the buffer stress material layer is etched to form a buffer stress layer, which is located on the bottom of the first groove. The ratio of the thickness to the thickness of the buffer stress layer on the side wall of the first groove is 1:1-0.8;

A main stress layer is formed in the first groove including the buffer stress layer.

Optionally, the material of the stress buffer layer is silicon germanium, and the atomic percentage of germanium in the stress buffer layer ranges from 5% to 25%.

Optionally, the method of etching the buffer stress material layer is dry etching.

Optionally, the temperature range of the dry etching is 0°C-1000°C, the pressure range is 0torr-2000torr, the power range of the RF power supply is 0W-1000W, the range of the RF bias voltage is 30V-2000V, the etching gas It is one or any combination of HCl, HBr and HF, and the flow rate range of the etching gas is 0 sccm-500 sccm.

Optionally, forming the buffer stress material layer, etching the buffer stress material layer and forming the main stress layer are performed in the same device.

Optionally, etching the stress buffering material layer is performed simultaneously with forming the stress buffering material layer.

Optionally, the method of etching the buffer stress material layer is wet etching.

Optionally, the wet etching solution is an inorganic alkaline solution, and the pH value of the inorganic alkaline solution is in the range of 8-14.

Optionally, the inorganic alkaline solution includes one or any combination of KOH, NaOH and NH ₄ OH.

Optionally, the inorganic alkaline solution is a potassium hydroxide solution, and the etching rate ratio of the potassium hydroxide solution to the buffer stress material layer on (110), (100) and (111) crystal planes is 1.5-2.5 :1:1/500～1/250.

Optionally, the wet etching solution is an organic alkaline solution.

Optionally, the organic alkaline solution is a tetramethylammonium hydroxide solution, and the tetramethylammonium hydroxide solution can buffer stress material layers on (110), (100) and (111) crystal planes The speed ratio is 1.5～2:1:1/50～1/30.

Optionally, the buffer stress layer has a thickness ranging from 3 nm to 20 nm.

Optionally, the material of the main stress layer is boron-containing silicon germanium, the atomic percentage of germanium in the main stress layer is greater than the atomic percentage of germanium in the buffer stress layer, and the main stress The atomic percentage of germanium in the layer is greater than or equal to 30%.

Optionally, after forming the main stress layer in the first groove including the buffer stress layer, the method further includes: forming a covering layer on the upper surfaces of the buffer stress layer and the main stress layer.

Optionally, the material of the covering layer is silicon germanium, the atomic percentage of germanium in the covering layer is smaller than the atomic percentage of germanium in the buffer stress layer, and the atomic percentage of germanium in the covering layer is The atomic percentage is greater than 0% and less than or equal to 10%.

Optionally, the first gate structure includes a first gate dielectric layer and a first gate electrode, after the first gate structure is formed on the semiconductor substrate, and on both sides of the first gate structure Before forming the first groove in the semiconductor substrate, it also includes: forming an offset spacer covering the sidewall of the first gate dielectric layer and the sidewall of the first gate electrode on the semiconductor substrate; A barrier layer is formed on the top of the first gate electrode; ion implantation is performed using the barrier layer and the offset spacer as a mask to form a lightly doped region in the semiconductor substrate; After forming the main stress layer in the groove, it also includes: forming a side wall covering the side wall of the offset spacer; performing ion implantation using the barrier layer and the side wall as a mask, and performing ion implantation under the main stress forming a heavily doped region in the layer; forming a metal silicide layer on the heavily doped region; forming a first interlayer dielectric layer on the metal silicide layer, the sidewall and the barrier layer, and performing chemical mechanical polishing until the remaining upper surface of the first interlayer dielectric layer is flush with the upper surface of the first gate electrode.

Correspondingly, the present invention also provides a method for forming a semiconductor device, where the semiconductor device includes a PMOS transistor, and the PMOS transistor is formed by using any one of the methods for forming a PMOS transistor described above.

The invention provides a PMOS transistor, comprising:

semiconductor substrate;

a gate structure located on the semiconductor substrate;

a main stress layer in the semiconductor substrate located on both sides of the gate structure;

a buffer stress layer located between the main stress layer and the semiconductor substrate;

The ratio of the thickness of the buffer stress layer below the main stress layer to the thickness of the buffer stress layer on the side wall of the main stress layer is 1:1-0.8.

Correspondingly, the present invention also provides a semiconductor device, including the above-mentioned PMOS transistor.

Compared with the prior art, the technical solution of the present invention has the following advantages:

After forming a first gate structure on a semiconductor substrate, and forming first grooves in the semiconductor substrate on both sides of the first gate structure, forming a buffer stress material layer on the bottom and side walls of the first groove, and Etching the buffer stress material layer to form a buffer stress layer, so that the ratio of the thickness of the buffer stress layer on the bottom of the first groove to the thickness of the buffer stress layer on the side wall of the first groove is 1 :1～0.8. When the volume of the first groove is the same and the thickness of the buffer stress layer on the side wall of the first groove is not much different, the volume in the first groove except the buffer stress layer is larger, so that the formed main stress layer The larger volume increases the compressive stress applied to the channel region of the PMOS transistor, improves the performance of the formed PMOS transistor, and further improves the performance of the semiconductor device including the PMOS transistor.

In addition, the buffer stress layer serves as a seed layer for the subsequent formation of the main stress layer, which can improve the crystallization quality of the formed main stress layer.

Further, forming the buffer stress material layer, etching the buffer stress material layer and forming the main stress layer are carried out in the same equipment, so as to prevent the surface of the formed buffer stress layer from being separated from the semiconductor substrate during the transfer process. Air contact, thereby avoiding oxidation on the surface of the buffer stress layer, preventing oxidation from affecting the crystallization quality of the main stress layer, so that the buffer stress layer and the main stress layer are better combined, which is conducive to the transfer of stress in the main stress layer to the PMOS transistor. In the channel region, the performance of the formed PMOS transistor is improved.

Moreover, when dry etching is used to etch the buffer stress material layer, the etching of the buffer stress material layer and the formation of the buffer stress material layer may also be performed simultaneously. That is, while forming the stress buffering material layer, dry anisotropic in-situ etching is performed on the formed stress buffering material layer. Since the deposition rate of the buffer stress material layer on the bottom of the first groove is greater than the deposition rate of the buffer stress material layer on the sidewall of the first groove, the dry etching has an effect on the etching of the buffer stress material layer deposited on the bottom of the first groove. The etch rate is greater than the etch rate of the buffer stress material layer deposited on the sidewall of the first groove, so the thickness of the buffer stress material layer on the bottom of the first groove and the side wall can increase substantially uniformly until the buffer stress layer is formed . While avoiding the oxidation of the surface of the buffer stress layer in contact with air, it also reduces the steps of transferring the semiconductor substrate, simplifies the steps of forming PMOS transistors, and saves the manufacturing time and process cost of forming PMOS transistors.

Further, wet etching is used to etch the buffer stress material layer until the buffer stress layer is formed. The wet etching solution is an organic alkaline solution or an inorganic alkaline solution with a pH value in the range of 8-14. Due to the different dangling bonds on different crystal planes of silicon, organic alkaline solutions and inorganic alkaline solutions with a pH value in the range of 8 to 14 can etch the stress buffer material layer on the (100) and (110) crystal planes much faster than that on the (100) and (110) crystal planes. (111) The etch rate of the stress buffer material layer on the crystal surface, the etch rate of the stress buffer material layer on the bottom of the first groove by wet etching is greater than that of the stress buffer material layer on the side wall of the first groove The etching rate is such that the ratio of the thickness of the buffer stress layer on the bottom of the first groove to the thickness of the buffer stress layer on the sidewall of the first groove is gradually approaching 1:1 to 0.8, and finally at the bottom of the first groove And the buffer stress layer is formed on the side wall. And because there is no ion bombardment when forming the buffer stress layer by wet etching, the surface of the formed buffer stress layer is uniform and smooth, which is beneficial to the formation of the subsequent main stress layer, and the performance of the formed PMOS transistor is good.

Further, the material of the main stress layer is boron-containing silicon germanium, and the main stress layer can be doped with boron ions while forming the silicon germanium in the main stress layer or after the formation of silicon germanium in the main stress layer to form main stress layer. Boron ions in the main stress layer can reduce the resistance of the main stress layer, and the buffer stress layer can prevent the diffusion of boron dopant ions in the main stress layer to the channel region of the subsequently formed PMOS transistor, preventing channel breakdown and heavy doping The region is shorted, improving the performance of the formed PMOS transistor.

Further, after the buffer stress layer and the main stress layer are formed, a covering layer is formed on the upper surfaces of the buffer stress layer and the main stress layer. Since the surface of the formed cover layer is flat, it is beneficial to the subsequent ion implantation process of the heavily doped region, so that the shape of the formed heavily doped region is better, and thus the performance of the formed PMOS transistor is improved.

Description of drawings

1 to 11 are schematic diagrams of a first embodiment of a method for forming a PMOS transistor of the present invention;

FIG. 12 is a schematic diagram of a second embodiment of the method for forming a PMOS transistor of the present invention.

Detailed ways

The inventor found through research that although the buffer stress layer can prevent dislocations at the contact surface between the main stress layer and the semiconductor substrate, improve the crystallization quality of the main stress layer, and enable the subsequent formation of the silicon germanium layer, the compressive stress can be completely transferred to the channel region of the PMOS transistor, and can block the diffusion of boron doped ions in the main stress layer to the channel direction. However, due to the large aspect ratio of the first groove and the growth rate of silicon germanium on the (100) crystal plane is much higher than that on the (111) crystal plane, the step coverage is limited during the growth of silicon germanium. The thickness of the buffer stress layer on the side wall of the first groove is much thinner than the thickness of the buffer stress layer on the bottom (thickness ratio ranges from 1:3 to 5).

Moreover, in order to ensure that the stress buffer layer on the side wall of the first groove can play the role of the seed layer and block the diffusion of boron doped ions in the main stress layer to the channel region, the buffer stress layer on the side wall of the first groove Need to be greater than a certain thickness. In this way, the buffer stress layer on the bottom of the first groove is too thick, and the volume for growing the main stress layer in the first groove is reduced. The compressive stress in the silicon germanium layer (including the main stress layer and the buffer stress layer) is related to the content of germanium in the silicon germanium layer. Most of the compressive stress is provided by the silicon germanium main stress layer. The medium pressure stress becomes smaller, which in turn leads to a smaller compressive stress applied to the channel region of the formed PMOS transistor, resulting in a limited improvement in the performance of the PMOS device.

After further research, the inventor found that the formed stress buffering material layer can be etched during or after the stress buffering material layer is formed to form a stress buffering layer so that the stress buffering layer at the bottom of the first groove The ratio of the thickness of the stress buffering material layer to the thickness of the stress buffering material layer on the side wall of the first groove is in the range of 1:1˜0.8. Under the premise of ensuring that the thickness of the buffer stress layer on the side wall of the first groove is greater than a certain thickness, the thickness of the buffer stress layer on the bottom of the first groove is smaller, so that the volume of the first groove for subsequent growth of the main stress layer is smaller. Larger, the volume of the main stress layer in the first groove is larger, which increases the compressive stress applied by the main stress layer to the channel region of the PMOS transistor, and improves the performance of the formed PMOS transistor.

In order to make the above objects, features and advantages of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

first embodiment

Referring to FIG. 1 , a semiconductor substrate 201a is provided, in which a shallow trench isolation structure 203 is formed, and the semiconductor substrate 201a between adjacent shallow trench isolation structures 203 is the active region of the formed PMOS transistor .

In this embodiment, the material of the semiconductor substrate 201a is single crystal silicon or silicon on insulator. The material of the shallow trench isolation structure 203 is silicon oxide, and the formation process of the shallow trench isolation structure 203 is well known to those skilled in the art, and will not be repeated here.

Continuing to refer to FIG. 1 , a first gate structure 205 is formed on the semiconductor substrate 201 a.

Specifically, the first gate structure 205 includes a first gate dielectric layer 205a on the semiconductor substrate 201a and a first gate electrode 205b on the first gate dielectric layer 205a.

The material of the first gate dielectric layer 205a can be one or a combination of silicon oxide, silicon oxynitride, and silicon nitride; the material of the first gate dielectric layer 205a can also be hafnium dioxide, hafnium silicon oxide, lanthanum oxide , lanthanum aluminum oxide, zirconia, zirconia silicon, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide or lead zinc niobate and other high-k metals One or more oxides.

The material of the first gate electrode 205b can be polysilicon; the material of the first gate electrode 205b can also be Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, TaN, Ta, TaC, TaSiN, W , WN, WSi and other metal materials or one or more.

In this embodiment, the material of the first gate dielectric layer 205a is silicon oxide, and the material of the first gate electrode 205b is polysilicon. The methods for forming the first gate dielectric layer 205a and the first gate electrode 205b are well known to those skilled in the art, and will not be repeated here.

Continuing to refer to FIG. 1 , an offset spacer 207 a covering sidewalls of the first gate structure 205 is formed on the semiconductor substrate 201 a.

In this embodiment, the material of the offset spacer 207a is silicon nitride. The method of forming the offset spacers 207a may be a chemical vapor deposition process.

Continuing to refer to FIG. 1 , a blocking layer 209 is formed on top of the first gate electrode 205 b.

In this embodiment, the material of the barrier layer 209 is silicon nitride, and the method of forming the barrier layer 209 may be a chemical vapor deposition process. The barrier layer 209 is used to protect the first gate electrode 205b in subsequent processes (such as the formation process of the first groove, the formation process of the metal silicide layer, etc.).

Continuing to refer to FIG. 1 , using the barrier layer 209 and the offset spacer 207 a as a mask, ion implantation is performed to form a lightly doped region (not shown) in the semiconductor substrate 201 a.

For a PMOS transistor, the conductivity type of the ion-implanted dopant ions is P-type, such as boron ions or boron difluoride ions. After forming the lightly doped region, it may further include: performing heat treatment on the semiconductor substrate 201a, so that the P-type dopant ions in the lightly doped region are uniformly diffused vertically and laterally.

Continuing to refer to FIG. 1 , dummy sidewalls 211 covering the sidewalls of the offset spacers 207 a and the sidewalls of the barrier layer 209 are formed on the semiconductor substrate 201 a.

Specifically, the dummy spacer 211 may be a single-layer structure, and its material may be silicon nitride. The dummy spacer 211 can also be a stacked structure, which includes a silicon oxide layer (not shown) on the semiconductor substrate 201a covering the offset spacer 207a and the sidewall of the barrier layer 209 and a silicon oxide layer (not shown) on the semiconductor substrate 201a. A silicon nitride layer (not shown) on the silicon oxide layer. The dummy sidewall 211 is used to protect the offset spacer 207 a from damage during the formation of the first groove, and serves as a mask for the subsequent formation of the first groove.

In this embodiment, the dummy sidewall 211 may be a single-layer structure, and its material may be silicon nitride.

Referring to FIG. 2, using the barrier layer 209 and the dummy spacer 211 as a mask, the semiconductor substrate 201a in FIG. Groove 213a.

In this embodiment, the first groove 213a is sigma-shaped. Forming the first groove 213a may include: using the barrier layer 209 and the dummy spacer 211 in FIG. An opening (not shown) with a sidewall perpendicular to the bottom is formed in the semiconductor substrate 201a; wet etching is performed on the opening until a sigma-shaped first groove 213a is formed in the semiconductor substrate 201b .

In other embodiments, the first groove 213a may also be a bowl-shaped groove, that is, the sidewall of the first groove 213a is nearly perpendicular to the bottom.

Referring to FIG. 3 , a stress buffering material layer 215 a is formed on the bottom and sidewalls of the first groove 213 a in FIG. 2 to form the first groove 213 b including the stress buffering material layer 215 a.

In this embodiment, the stress buffering material layer 215a is made of silicon germanium, and the atomic percentage of germanium in the stress buffering material layer 215a ranges from 5% to 25%. For example, the atomic percentage of germanium in the buffer stress material layer 215a is 5%, 15%, 20% or 25%. The method of forming the buffer stress material layer 215a may be a chemical vapor deposition process or an atomic layer deposition process.

In this embodiment, during the process of forming the buffer stress material layer 215a, the reaction gas introduced into the deposition equipment includes one or any combination of HCl, HBr and HF, so as to prevent the formed silicon germanium from adhering to the material and causing oxidation. silicon (shallow trench isolation structure 203 ) and silicon nitride (barrier layer 209 and dummy spacer 211 ) on the structure. At this time, the flow rate of the reaction gas in the deposition chamber ranges from 0sccm to 500sccm, the temperature ranges from 100°C to 1000°C, the pressure ranges from 0torr to 2000torr, the power range of the RF power supply ranges from 0W to 1000W, and the RF bias voltage is 0V.

In this embodiment, during the process of forming the stress buffering material layer 215a, the thickness _d31 of the stress buffering material layer 215a formed on the bottom of the first groove 213b is equal to that formed in the first groove 213b due to the gravitational force of germanium atoms and silicon atoms. The ratio of the thicknesses d ₁₁ and d ₂₁ of the stress buffering material layer 215a on the sidewall is in the range of 3˜5:1.

Referring to FIG. 5, the buffer stress material layer 215a in FIG. 3 is etched to form a buffer stress layer 215b in the first groove 213c, so that the thickness of the buffer stress layer 215b on the bottom of the first groove 213c is The ratio of d ₃₂ to the thicknesses d ₁₂ and d ₂₂ of the buffer stress layer 215b on the sidewall of the first groove 213c is 1:1˜0.8. For example, the ratio of the thickness d ₃₂ to the thickness d ₁₂ is 1:1, 1:0.9 or 1:0.8, etc.; the ratio of the thickness d ₃₂ to the thickness d ₂₂ is 1:1, 1:0.95 or 1:0.8, etc.

In this embodiment, the method of etching the buffer stress material layer 215a in FIG. 3 may be wet etching. The wet etching solution may be an organic alkaline solution or an inorganic alkaline solution.

Referring to FIGS. 3 to 5, FIG. 4 is an enlarged view of the buffer stress material layer 215a in FIG. 3, and the dotted line in FIG. The enclosed solid line shows the upper surface of the buffer stress layer 215a before wet etching.

When the wet etching solution is an organic alkaline solution, the organic alkaline solution may be tetramethylammonium hydroxide (Tetramethylammonium Hydroxide, TMAH for short). The etching rate ratio of the tetramethylammonium hydroxide to the buffer stress material layer 215a on (110), (100) and (111) crystal planes is 1.5˜2:1:1/50˜1/30. For example, the etching rate ratios of tetramethylammonium hydroxide on the (110), (100) and (111) crystal planes of the buffer stress material layer 215a are 1.5:1:1/50, 1.5:1:1/30, 2:1:1/50, 2:1:1/30 or 1.7:1:1/40 etc.

When the wet etching solution is an inorganic alkaline solution, the pH value of the inorganic alkaline solution is in the range of 8-14. The inorganic alkaline solution is one or any combination of KOH, NaOH and NH ₄ OH. For example, the wet etching solution is a potassium hydroxide solution, and the etching rate ratio of the potassium hydroxide solution to the buffer stress material layer on the (110), (100) and (111) crystal planes is 1.5- 2.5:1:1/500～1/250. For example, the etch rate ratio of potassium hydroxide solution to buffer stress material layer on (110), (100) and (111) crystal planes is 1.5:1:1/500, 1.5:1:1/250, 2.5:1 :1/500, 2.5:1:1/250 or 2:1:1/300 etc.

Due to the different dangling bonds on different crystal planes of silicon, the etching rate of the stress buffer material layer 215a on the (110) crystal plane is higher than that on the (100) crystal plane by an organic alkaline solution or an inorganic alkaline solution with a pH value in the range of 8 to 14. The etching rate of the stress buffer material layer 215a on the crystal plane, and the etching rate of the stress buffer material layer 215a on the (100) and (110) crystal planes by the above alkaline solution is much higher than that on the (111) crystal plane. The etch rate of the material layer 215a. Therefore, the stress buffer material layer 215a can be wet-etched by an organic alkaline solution or an inorganic alkaline solution with a pH value in the range of 8 to 14, so that the buffer stress material layer 215a located on the bottom of the first groove 213b in FIG. (the crystal plane is (100)) is gradually approaching the thickness of the buffer stress material layer 215a (the crystal planes are (110) and (111)) on the side wall of the first groove 213b, and finally the first concave A buffer stress layer 215b is formed on the bottom and side walls of the groove 213c, so that the thickness d ₃₂ of the buffer stress layer 215b on the bottom of the first groove 213c is the same as the thickness d ₁₂ of the buffer stress layer 215b on the side walls of the first groove 213c. The ratios of d ₂₂ are all in the range of 1:1-0.8 (that is, both d ₃₂ :d ₁₂ and d ₃₂ :d ₂₂ are in the range of 1:1-0.8).

Moreover, when the buffer stress layer 215b is formed by wet etching, there is no ion bombardment, the surface of the formed buffer stress layer 215b is uniform and smooth, and the morphology of the buffer stress layer 215b is better, which is beneficial to the formation of the subsequent main stress layer. The performance of the formed PMOS transistor is good.

In this embodiment, because the ratio of the thickness _{d32 of} the buffer stress layer 215b on the bottom of the first groove 213c to the thicknesses d12 and _d22 of the buffer stress layer 215b on the sidewall of the first groove 213c is between 1:1 and Within the range of 0.8, the volume of the first groove 213a is the same, and the thickness of the buffer stress layer on the side wall of the first groove 213a is not much different, so that the volume in the first groove 213c except the buffer stress layer 215b is larger , so that the volume of the subsequently formed principal stress layer is larger. The buffer stress layer 215b can reduce serious dislocations (Stackfalse) at the interface between the subsequently formed main stress layer and the semiconductor substrate 210b, and prevent the compressive stress in the main stress layer from being released before being transmitted to the channel region of the PMOS transistor. At the same time, the volume of the formed main stress layer is increased, and the electrical performance of the formed PMOS transistor is improved.

In addition, the buffer stress layer 215b can be used as a seed layer of the formed main stress layer, and when the main stress layer is subsequently formed on the buffer stress layer 215b, the crystallization quality of the formed main stress layer can be improved.

Moreover, in the subsequent process of forming the main stress layer, the main stress layer will be doped with boron ions to reduce the resistance of the main stress layer. The buffer stress layer 215b does not need to be doped with boron ions, and the buffer stress layer 215b can prevent the diffusion of boron dopant ions in the main stress layer to the channel region of the subsequently formed PMOS transistor, preventing channel breakdown and redoping. Miscellaneous area short circuit.

Referring to FIG. 6 , a main stress layer 217 is formed in the first groove 213c except the buffer stress layer 215b in FIG. 5 .

In this embodiment, the material of the main stress layer 217 is silicon germanium, and the atomic percentage of germanium in the main stress layer 217 is greater than or equal to 30%. For example, the atomic percentage of germanium in the main stress layer 217 is 30%, 35%, 55% or 70%. The method of forming the main stress layer 217 may be a chemical vapor deposition process or an epitaxial growth process.

Since the ratio of the thickness of the buffer stress layer 215b on the bottom of the first groove 213c to the thickness of the buffer stress layer 215b on the side wall of the first groove 213c is 1:1-0.8, the volume of the first groove 213a is the same When the thickness difference between the bottom of the first groove side wall 213c and the buffer stress layer 215b on the side wall is not much different, the volume of the first groove 213c other than the buffer stress layer 215b is larger, so that the formed main stress layer 217 The larger volume increases the compressive stress applied to the channel region of the PMOS transistor, improves the mobility of holes in the channel region of the subsequently formed PMOS transistor, and improves the performance of the formed PMOS transistor.

It should be noted that when the main stress layer 217 is formed by chemical vapor deposition process, HCl gas can also be introduced into the deposition chamber to prevent the formed silicon germanium from adhering to the shallow trench isolation structure in the semiconductor substrate 201b 203 , barrier layer 209 and dummy sidewall 211 . In addition, when the main stress layer 217 is formed by the chemical vapor deposition process, or after the main stress layer 217 is formed, the formed main stress layer 217 can also be doped with boron ions in situ to reduce the main stress. The resistance of layer 217.

It should also be noted that when wet etching is used to etch the buffer stress material layer 215a in FIG. 3 to form the buffer stress layer 215b, the bottom and sides of the first groove 213a in FIG. Forming the buffer stress material layer 215a on the wall, performing wet etching on the buffer stress material layer 215a in FIG. Avoid the surface of the formed buffer stress layer 215b from being in contact with air, avoid oxidation on the surface of the buffer stress layer 215b, avoid oxidation from affecting the crystallization quality of the main stress layer 217, and make the bonding degree of the buffer stress layer 215b and the main stress layer 217 relatively high. Well, it is beneficial to transfer the stress in the main stress layer 217 to the channel region of the PMOS transistor, improving the performance of the formed PMOS transistor.

Specifically, the buffer stress layer 215b has a thickness ranging from 3 nm to 20 nm. For example, the buffer stress layer 215b has a thickness of 3nm, 5nm, 10nm, 15nm, 17nm or 20nm. After ion implantation is performed on the main stress layer 217 to form a P-type heavily doped region, the buffer stress layer 215b can block the diffusion of boron ions in the main stress layer 217 to the semiconductor substrate 201b, preventing the formation of PMOS transistors. The punch through of the channel region improves the electrical performance of the formed PMOS transistor.

However, if the thickness of the buffer stress layer 215b is less than 3nm, it is not enough to block the diffusion of boron ions in the main stress layer 217 to the semiconductor substrate 201b, and the electrical performance of the formed PMOS transistor is relatively poor; if the thickness of the buffer stress layer 215b is greater than 20nm, In turn, the volume of the first groove 213c including the buffer stress layer 215b in FIG. 5 is reduced, which in turn leads to a small volume of the main stress layer 217 in FIG. 7, and the compressive stress applied to the channel region of the PMOS transistor by the main stress layer 217 is reduced , the effect of the main stress layer 217 on improving the hole mobility in the channel region of the PMOS transistor is limited.

It should be noted that when the main stress layer 217 is formed in the first groove 213c except the buffer stress layer 215b in FIG. function to make the buffer stress layer 215b thinner. However, due to the low velocity of reactive ions in the chemical vapor deposition process, the thinning of the buffer stress layer 215b is small, which has little effect on the performance of the PMOS transistor.

It should also be noted that, in order to ensure that the formed main stress layer 217 can completely fill the first groove 213c except the buffer stress layer 215b in FIG. 5 , the upper surface of the main stress layer 217 formed in this embodiment slightly higher than the upper surface of the buffer stress layer 215b. In other embodiments, the upper surface of the main stress layer 217 may also be flush with the upper surface of the buffer stress layer 215b.

Continuing to refer to FIG. 6 , a cover layer 219 covering the buffer stress layer 215 b and the main stress layer 217 is formed.

Specifically, the material of the covering layer 219 is silicon or silicon germanium. The method of forming the covering layer 219 is a chemical vapor deposition process or an atomic layer deposition process. The thickness of the covering layer 219 ranges from 50 angstroms to 250 angstroms.

When the material of the covering layer 219 is silicon germanium, the atomic percentage of germanium in the covering layer 219 is smaller than the atomic percentage of germanium in the buffer stress layer 215b, and the atomic percentage of germanium in the covering layer 219 is The atomic percentage is greater than 0% and less than or equal to 10%. For example, the atomic percentage of germanium in the covering layer 219 is 1%, 3%, 5%, 8%, 9% or 10%.

In this embodiment, the material of the covering layer 219 is silicon.

The covering layer 219 is used to prevent the subsequent formation of the metal silicide layer directly on the main stress layer 217, avoiding dislocations between the contact surface of the main stress layer 217 and the metal silicide layer, thereby avoiding large leakage currents .

Moreover, due to the different growth rates of germanium and silicon at different crystal plane positions, the surfaces of the main stress layer 217 and the buffer stress layer 215b are not completely flush, which is not conducive to the subsequent ion implantation process in the heavily doped region, the formation process of metal silicide, and the metal insertion process. Plug formation process. By forming a flat cover layer 219 on the upper surfaces of the stress buffer layer 215b and the main stress layer 217, the subsequent ion implantation process in the heavily doped region, the formation process of metal silicide and metal plugs can be simplified, and the formed heavy The morphology of the doped region, the metal silicide layer and the metal plug disposed above the heavily doped region is better.

In other embodiments, the step of forming the covering layer 219 may also be omitted.

Referring to FIG. 7 , the dummy sidewall 211 in FIG. 6 is removed.

In this embodiment, the method for removing the dummy sidewall 211 in FIG. 6 is wet etching, and the specific etching process is well known to those skilled in the art, and will not be repeated here.

Continuing to refer to FIG. 7 , sidewalls 221 a covering sidewalls of the barrier layer 209 and sidewalls of the offset spacers 207 a are formed on the semiconductor substrate 201 b and part of the capping layer 219 .

In this embodiment, the material of the side wall 221a is silicon nitride, and its specific formation process is well known to those skilled in the art, and will not be repeated here.

In other embodiments, the dummy sidewall 211 may not be removed, and the sidewall 221 a is directly formed on the sidewall of the dummy sidewall 211 .

After the sidewalls 221a are formed, ion implantation is performed using the barrier layer 209 and the sidewalls 221a as a mask to form a heavily doped region (not shown) in the main stress layer 217 .

For PMOS transistors, the conductivity type of the doped ions in the heavily doped region is P-type, such as boron ions or boron difluoride ions.

Referring to FIG. 8 , a metal silicide layer 223 is formed on the capping layer 219 .

The metal silicide layer 223 is used to reduce the contact resistance at the contact between the heavily doped region and the subsequently formed metal plug. The material of the metal silicide layer 223 may be nickel silicon compound. The formation process of the metal silicide layer 223 may be a deposition process or a selective epitaxial growth process.

In this embodiment, the formation process of the metal silicide layer 223 is a deposition process.

After forming the metal silicide layer 223 , it also includes: performing an annealing process to change the crystal type of the metal silicide layer 223 .

Continuing to refer to FIG. 8 , a first interlayer dielectric layer 225 a is formed on the shallow trench isolation structure 203 , the metal silicide layer 223 , the barrier layer 209 and the sidewall 221 a.

In this embodiment, the material of the first interlayer dielectric layer 225a may be silicon oxide or silicon oxynitride. The method of forming the first interlayer dielectric layer 225a may be chemical vapor deposition.

Referring to FIG. 9, the first interlayer dielectric layer 225a, the barrier layer 209, the spacer 221a, the first gate electrode 205b and the offset spacer 207a in FIG. 8 are chemically mechanically polished until the remaining first layer Top surfaces of the interlayer 225b, the offset spacer 207b, the first gate electrode 205c, and the spacer 221b are flush.

Referring to FIG. 10 , the remaining first gate electrode 205 c and first gate dielectric layer 205 a in FIG. 9 are sequentially removed to expose the semiconductor substrate 201 b to form a second groove (not shown).

In this embodiment, the method for removing the first gate electrode 205c and the first gate dielectric layer 205a may be dry etching or wet etching, which does not limit the protection scope of the present invention.

Continuing to refer to FIG. 10 , a second gate structure 227 is formed in the second groove.

In this embodiment, the second gate structure 227 includes a second gate dielectric layer 227a and a second gate electrode 227b. The second gate dielectric layer 227a is located on the semiconductor substrate 201b at the bottom of the second groove; the second gate electrode 227b is located on the second gate dielectric layer and 227a. The second gate structure 227 is used to control the channel opening of the PMOS transistor.

The material of the second gate dielectric layer 227a can be hafnium dioxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, barium oxide One or more of high-k metal oxides such as strontium titanium, yttrium oxide, aluminum oxide, lead scandium tantalum oxide or lead zinc niobate. The material of the second gate electrode 227b may be one or more of Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, TaN, Ta, TaC, TaSiN, W, WN, WSi and other metal materials.

In another embodiment, the material of the first gate dielectric layer 205a is metal oxide, and the material of the first gate electrode 205b is polysilicon. After chemical mechanical polishing, only the first gate electrode 205c can be removed, and the second gate electrode can be directly formed on the first gate dielectric layer 205a, which is formed by the first gate dielectric layer 205a and the second gate electrode. Gate structure of a PMOS transistor.

In yet another embodiment, the material of the first gate dielectric layer 205a is metal oxide, and the material of the first gate electrode 205b is Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, TaN, One or more of Ta, TaC, TaSiN, W, WN, WSi and other metal materials. After performing chemical mechanical polishing, the first gate dielectric layer 205 a and the remaining first gate electrode 205 c together serve as the gate structure of the formed PMOS transistor.

In yet another embodiment, the material of the first gate dielectric layer 205a is one or a combination of silicon oxide, silicon oxynitride, and silicon nitride, and the material of the first gate electrode 205b is polysilicon. After performing chemical mechanical polishing, the first gate dielectric layer 205 a and the remaining first gate electrode 205 c together serve as the gate structure of the formed PMOS transistor.

Referring to FIG. 11 , a second interlayer dielectric layer 229 is formed on the first interlayer dielectric layer 225 b , sidewalls 221 b and second gate electrode 227 b in FIG. 10 .

The material of the second interlayer dielectric layer 229 is a low-k or ultra-low-k material, and the method for forming the second interlayer dielectric layer 229 may be a chemical vapor deposition process.

Continuing to refer to FIG. 11, a first metal plug 231 connected to the metal silicide layer 223 is formed in the first interlayer dielectric layer 225b and the second interlayer dielectric layer 229 above the metal silicide layer 223, and in the A second metal plug 233 connected to the second gate electrode 227b is formed in the second interlayer dielectric layer 229 above the second gate electrode 227b.

The first metal plug 231 is used to electrically connect the heavily doped region under the metal silicide layer 223 with an external power source. The second metal plug 233 is used to electrically connect the second gate electrode 227b to an external power source.

In this embodiment, the material of the first metal plug 231 and the second metal plug 233 can be copper, and the specific forming process thereof is well known to those skilled in the art, and will not be repeated here.

In this embodiment, the ratio of the thickness of the buffer stress layer 215b formed on the bottom of the first groove 213c to the thickness of the buffer stress layer 215b on the sidewall of the first groove 213c is 1:1˜0.8. When the volume of the first groove 213a is the same and the thickness of the buffer stress layer 215b on the side wall of the first groove 213c is not much different, the volume in the first groove 213c other than the buffer stress layer 215b is larger, thereby making The volume of the main stress layer 217 formed is larger, the compressive stress applied to the channel region of the PMOS transistor is larger, and the performance of the formed PMOS transistor is better.

second embodiment

Referring to FIG. 12 , after the semiconductor structure in FIG. 3 is formed, dry etching is performed on the buffer stress material layer 215 a in FIG. 3 . The buffer stress layer 215c formed after dry etching is shown in FIG. 12 .

Specifically, the temperature range of the dry etching is 0°C-1000°C, the pressure range is 0torr-2000torr, the power range of the RF power supply is 0W-1000W, the range of the RF bias voltage is 30V-2000V, and the etching gas is One or any combination of HCl, HBr and HF, the flow rate of the etching gas ranges from 0 sccm to 500 sccm. At this time, the etching rate of the stress buffering material layer 215a on the bottom of the first groove 213b in FIG. The thickness of the stress buffering material layer 215a on the bottom of the first groove 213b in FIG. 3 gradually approaches the thickness of the stress buffering material layer 215a on the sidewall of the first groove 213b until the stress buffering layer 215c is formed. The ratios of the thickness d ₃₄ of the buffer stress layer 215c on the bottom of the first groove 213d to the thicknesses d ₁₄ and d ₂₄ of the buffer stress layer 215c on the sidewall of the first groove 213d are both in the range of 1:1˜0.8.

Since the deposition rate of the stress buffering material layer on the bottom of the first groove 213a is greater than the deposition rate of the stress buffering material layer on the sidewall of the first groove 213a, dry etching has a negative impact on the stress buffering material deposited on the bottom of the first groove 213a. The etch rate of the layer is greater than the etch rate of the buffer stress material layer deposited on the sidewall of the first groove 213a, therefore, the thickness of the buffer stress material layer on the bottom and sidewall of the first groove 213a can be made substantially uniform increase until the buffer stress layer 215c is formed.

And because the etching gas contains one or any combination of HCl, HBr and HF, the silicon germanium formed at this time will not grow on the structure made of silicon oxide and silicon nitride, which can avoid the formation of buffer stress material layer on the shallow trench isolation structure 203 , the barrier layer 209 and the dummy spacer 211 .

It can be seen from Figure 5 and Figure 12 that the upper surface of the buffer stress layer 215b formed by wet etching is parallel to the (111) and (100) crystal planes, while the upper surface of the buffer stress layer 215c formed by dry etching is more Continuous, approximately arc-shaped.

It should be noted that in the existing process, in order to prevent the silicon germanium formed from growing on the shallow trench isolation structure 203, the barrier layer 209 and the dummy sidewall 211, when silicon germanium is formed, it will also be injected into the silicon germanium forming equipment. HCl was passed through. However, since the power of the RF power supply is 0V when silicon germanium is formed, HCI performs isotropic etching on the formed silicon germanium, and the deposition rate of silicon germanium at the bottom of the first groove is still greater than that of germanium on the sidewall of the first groove. For the deposition rate of silicon, the thickness of the buffer stress layer on the bottom of the first groove is still far greater than the thickness of the buffer stress layer on the sidewall of the first groove. Even HCI can not improve the morphology of the formed stress buffer layer.

It should also be noted that when dry etching is used to etch the buffer stress material layer 215a in FIG. 3 to form the buffer stress layer 215c in FIG. 12, the first groove 213a in FIG. Form a buffer stress material layer 215a on the bottom and side walls, perform dry etching or wet etching on the buffer stress material layer 215a in FIG. The layers are carried out in the same equipment, avoiding the surface of the formed buffer stress layer 215c from contacting with air, avoiding oxidation on the surface of the buffer stress layer 215c, avoiding the influence of oxidation on the crystallization quality of the main stress layer, and making the buffer stress layer 215c and the main stress layer The combination degree of the layers is good, which is beneficial to transfer the stress in the main stress layer to the channel region of the PMOS transistor, and improves the performance of the formed PMOS transistor.

In other embodiments, after the first groove 213a in FIG. 2 is formed, the stress buffering material layer 215a in FIG. anisotropic in-situ etching) until the buffer stress layer 215c is formed. Then, a main stress layer is formed in-situ on the buffer stress layer 215c.

The temperature range of the dry etching is 100°C-1000°C, the pressure range is 0torr-2000torr, the power range of the RF power supply is 0W-1000W, the range of the RF bias voltage is 30V-2000V, and the etching gas is HCl, HBr One or any combination of HF and HF, the flow rate of the etching gas ranges from 0 sccm to 500 sccm.

For the embodiment in which the formation of the buffer stress material layer 215a and the dry etching of the formed buffer stress material layer 215a are carried out simultaneously, while avoiding the oxidation of the surface of the buffer stress layer 215c in contact with air, it also reduces the transfer of the semiconductor substrate. The step at the bottom 201b simplifies the steps of forming the PMOS transistor and saves the manufacturing time and process cost of forming the PMOS transistor.

In this embodiment, after the buffer stress layer 215c in FIG. 12 is formed, please refer to the first embodiment for the formation process of the PMOS transistor, which will not be repeated here.

Correspondingly, this embodiment also provides a PMOS transistor, including:

semiconductor substrate;

a gate structure on a semiconductor substrate;

a main stress layer in the semiconductor substrate located on both sides of the gate structure;

a buffer stress layer located between the main stress layer and the semiconductor substrate;

The ratio of the thickness of the buffer stress layer below the main stress layer to the thickness of the buffer stress layer on the side wall of the main stress layer is 1:1-0.8.

For its specific structure, reference may be made to the above-mentioned embodiments, and details are not repeated here.

The main stress layer and the buffer stress layer are made of silicon germanium, and the atomic percentage of germanium in the buffer stress layer is greater than that of germanium in the main stress layer.

The atomic percentage of germanium in the main stress layer is greater than 30%, and the atomic percentage of germanium in the buffer stress layer is greater than or equal to 5% and less than or equal to 25%. The buffer stress layer has a thickness ranging from 3nm to 20nm.

The gate structure includes a gate dielectric layer and a gate, and the gate is located on the gate dielectric layer.

The material of the gate dielectric layer can be one or a combination of silicon oxide, silicon oxynitride, and silicon nitride; correspondingly, the material of the gate is polysilicon.

The material of the gate dielectric layer can also be a metal oxide; correspondingly, the material of the gate can be Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, TaN, Ta, TaC, TaSiN, W , WN, WSi and other metal materials or one or more.

A covering layer may also be formed on the main stress layer and the buffer stress layer. The material of the covering layer is silicon or silicon germanium. When the covering layer is made of silicon germanium, the atomic percentage of germanium in the covering layer is smaller than the atomic percentage of germanium in the buffer stress layer. The atomic percentage of germanium in the covering layer is greater than 0% and less than or equal to 10%.

It should be noted that the PMOS transistor can be formed by using the method for forming the PMOS transistor in the previous embodiment, but the present invention is not limited thereto.

In this embodiment, since the ratio of the thickness of the buffer stress layer below the main stress layer to the thickness of the buffer stress layer on the side wall of the main stress layer is 1:1 to 0.8, the volume of the main stress layer on the buffer stress layer is more Larger, the compressive stress applied to the channel region of the PMOS transistor is greater, the mobility of carriers in the PMOS transistor is faster, and the performance of the semiconductor device of the PMOS transistor is also better.

This embodiment also provides a semiconductor device including the above-mentioned PMOS transistor and a method for forming the same. The PMOS transistor in the semiconductor device can be formed by using the above-mentioned method for forming a PMOS transistor.

Specifically, the semiconductor device including the above-mentioned PMOS transistor may be a CMOS transistor. When forming the buffer stress layer and the main stress layer of the PMOS transistor in the semiconductor device, a protective layer and a photoresist layer can be sequentially formed on the surface of the entire semiconductor device area, and then the photoresist layer on the area where the PMOS transistor is located is removed by a photolithography process , the remaining protective layer located in the NMOS transistor region can protect the NMOS region in the subsequent process, and prevent silicon germanium from growing on the NMOS transistor region, which will affect the formation process of the subsequent NMOS transistor; then use the remaining photoresist layer as mask, etch the protective layer on the area where the PMOS transistor is located, to form dummy sidewalls covering the barrier layer and offset spacer sidewalls in the PMOS transistors, and the dummy sidewalls can protect the sidewalls in subsequent processes. Move the gap wall. For the formation process of the PMOS transistor among the CMOS transistors, reference may be made to the foregoing embodiments, and for the formation process of the NMOS transistor, reference may be made to the prior art, which will not be repeated here.

It should be noted that the semiconductor device is not limited to a CMOS transistor, and it may also be other semiconductor devices including a PMOS transistor, which is not limited in the present invention.

Because the stress in the channel region of the PMOS transistor in the semiconductor device is relatively large, and the mobility of holes in the channel region is high, the performance of the PMOS transistor is better, and the performance of the semiconductor device including the PMOS transistor is also better.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims (20)

1. A kind of 1. forming method of PMOS transistor, it is characterised in that including：

   Semiconductor substrate is provided；

   First grid structure is formed on the semiconductor substrate；

   The first groove is formed in the Semiconductor substrate of the first grid structure both sides；

   Buffering stress material layer is formed on the bottom of first groove and side wall, the buffering in the first recess sidewall should The dead-wood bed of material is more than certain thickness, and thickness ratio thickness on side wall of the buffering stress material layer on the first bottom portion of groove is thick to be obtained More, thickness ratio is 3~5:1；

   The buffering stress material layer is performed etching, to form buffering stressor layers, is ensured slow in the first recess sidewall Blow stress layer is more than the certain thickness, and the thickness for making to buffer stressor layers on the first bottom portion of groove reduces, recessed positioned at described first The ratio that thickness of the thickness of stressor layers with buffering stressor layers in first recess sidewall is buffered on trench bottom is 1:1~ 0.8, the certain thickness enables the buffering stressor layers in the first recess sidewall to play inculating crystal layer and stop in principal stress layer The effect that boron Doped ions are spread into channel region；

   Principal stress layer is formed in the first groove including the buffering stressor layers.
2. 2. the forming method of PMOS transistor as claimed in claim 1, it is characterised in that it is described buffering stressor layers material be Germanium silicon, the atomicity percentage range buffered in stressor layers shared by germanium is 5%~25%.
3. 3. the forming method of PMOS transistor as claimed in claim 2, it is characterised in that to it is described buffering stress material layer into The method of row etching is dry etching.
4. 4. the forming method of PMOS transistor as claimed in claim 3, it is characterised in that the temperature range of the dry etching For 0 DEG C~1000 DEG C, pressure range is 0torr~2000torr, and the power bracket of radio-frequency power supply is 0W~1000W, and radio frequency is inclined The scope of pressure is 30V~2000V, one kind or any combination in etching gas HCl, HBr and HF, the stream of the etching gas Amount scope is 0sccm~500sccm.
5. 5. the forming method of PMOS transistor as claimed in claim 3, it is characterised in that form the buffering stress material Layer, perform etching and formed the principal stress layer to the buffering stress material layer and carried out in same equipment.
6. 6. the forming method of PMOS transistor as claimed in claim 5, it is characterised in that to it is described buffering stress material layer into Row etching is carried out at the same time with forming the buffering stress material layer.
7. 7. the forming method of PMOS transistor as claimed in claim 2, it is characterised in that to it is described buffering stress material layer into The method of row etching is wet etching.
8. 8. the forming method of PMOS transistor as claimed in claim 7, it is characterised in that the solution of the wet etching is nothing Machine alkaline solution, the scope of the inorganic caustic solutions pH value is 8~14.
9. 9. the forming method of PMOS transistor as claimed in claim 8, it is characterised in that the inorganic caustic solutions include KOH, NaOH and NH₄One or any combination in OH.
10. 10. the forming method of PMOS transistor as claimed in claim 9, it is characterised in that the inorganic caustic solutions are hydrogen Potassium oxide solution, etch rate of the potassium hydroxide solution to buffering stress material layer on (110), (100) and (111) crystal face Than for 1.5~2.5:1:1/500~1/250.
11. 11. the forming method of PMOS transistor as claimed in claim 7, it is characterised in that the solution of the wet etching is Organic alkaline solution.
12. 12. the forming method of PMOS transistor as claimed in claim 11, it is characterised in that the organic alkaline solution is four Ammonium hydroxide solution, the tetramethyl ammonium hydroxide solution on (110), (100) and (111) crystal face to buffering stress material The etch rate ratio of layer is 1.5~2:1:1/50~1/30.
13. 13. the forming method of PMOS transistor as claimed in claim 1, it is characterised in that the thickness of the buffering stressor layers Scope is 3nm~20nm.
14. 14. the forming method of PMOS transistor as claimed in claim 1, it is characterised in that the material of the principal stress layer is The germanium silicon of boracic, the atomicity percentage in the principal stress layer shared by germanium are more than the atom shared by germanium in the buffering stressor layers Number percentages, the atomicity percentage in the principal stress layer shared by germanium are more than or equal to 30%.
15. 15. the forming method of PMOS transistor as claimed in claim 1, it is characterised in that including the buffering stressor layers The first groove in formed principal stress layer after, further include：In the buffering stressor layers and the upper surface shape of the principal stress layer Into coating.
16. 16. the forming method of PMOS transistor as claimed in claim 15, it is characterised in that the material of the coating is germanium Silicon, the atomicity percentage in the coating shared by germanium are less than the atomicity percentage shared by germanium in the buffering stressor layers, Atomicity percentage in the coating shared by germanium is more than 0% and less than or equal to 10%.
17. 17. the forming method of PMOS transistor as claimed in claim 1, it is characterised in that the first grid structure includes First gate dielectric layer and first gate electrode, form after first grid structure on the semiconductor substrate, and described first Formed before the first groove, further included in the Semiconductor substrate of gate structure both sides：Covering is formed on the semiconductor substrate The offset by gap wall of the side wall of first gate dielectric layer and the side wall of first gate electrode；Formed at the top of the first gate electrode Barrier layer；Using the barrier layer and the offset by gap wall as mask, ion implanting is carried out, is formed in the Semiconductor substrate Lightly doped district；Formed after principal stress layer, further included in the first groove including buffering stressor layers：Formed and cover the offset The side wall of the side wall of clearance wall；Using the barrier layer and the side wall as mask, ion implanting is carried out, in the principal stress layer Form heavily doped region；Metal silicide layer is formed on the heavily doped region；In the metal silicide layer, the side wall and institute State and the first interlayer dielectric layer is formed on barrier layer, and carry out chemical mechanical grinding, until remaining first interlayer dielectric layer Upper surface and the first gate electrode upper surface flush.
18. 18. a kind of forming method of semiconductor devices, it is characterised in that the semiconductor devices includes PMOS transistor, described PMOS transistor uses the forming method for including the PMOS transistor any one of claim 1 to 17 to be formed.
19. A kind of 19. PMOS transistor, it is characterised in that including：

    Semiconductor substrate；

    Gate structure in the Semiconductor substrate；

    Principal stress layer in the Semiconductor substrate of the gate structure both sides；

    Buffering stressor layers between the principal stress layer and Semiconductor substrate, the buffering stress in the first recess sidewall Layer is more than certain thickness, and the certain thickness enables the buffering stressor layers in the first recess sidewall to play inculating crystal layer and stop The effect that boron Doped ions are spread into channel region in principal stress layer；

    The thickness of buffering stressor layers on the principal stress layer side wall with buffering stressor layers below the principal stress layer The ratio of thickness is 1:1~0.8.
20. 20. a kind of semiconductor devices, it is characterised in that including the PMOS transistor described in claim 19.