[go: up one dir, main page]

CN104170068B - 用于低蚀刻速率硬模膜的具有氧掺杂的pvd氮化铝膜 - Google Patents

用于低蚀刻速率硬模膜的具有氧掺杂的pvd氮化铝膜 Download PDF

Info

Publication number
CN104170068B
CN104170068B CN201380014792.1A CN201380014792A CN104170068B CN 104170068 B CN104170068 B CN 104170068B CN 201380014792 A CN201380014792 A CN 201380014792A CN 104170068 B CN104170068 B CN 104170068B
Authority
CN
China
Prior art keywords
hard mold
oxygen
aluminium nitride
mold
gas
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201380014792.1A
Other languages
English (en)
Other versions
CN104170068A (zh
Inventor
曹勇
大东和也
拉尹库曼·雅卡尔尤
唐先明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Applied Materials Inc
Original Assignee
Applied Materials Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Applied Materials Inc filed Critical Applied Materials Inc
Publication of CN104170068A publication Critical patent/CN104170068A/zh
Application granted granted Critical
Publication of CN104170068B publication Critical patent/CN104170068B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • CCHEMISTRY; METALLURGY
    • C04CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES
    • C04BLIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE
    • C04B35/00Shaped ceramic products characterised by their composition; Ceramics compositions; Processing powders of inorganic compounds preparatory to the manufacturing of ceramic products
    • C04B35/515Shaped ceramic products characterised by their composition; Ceramics compositions; Processing powders of inorganic compounds preparatory to the manufacturing of ceramic products based on non-oxide ceramics
    • C04B35/58Shaped ceramic products characterised by their composition; Ceramics compositions; Processing powders of inorganic compounds preparatory to the manufacturing of ceramic products based on non-oxide ceramics based on borides, nitrides, i.e. nitrides, oxynitrides, carbonitrides or oxycarbonitrides or silicides
    • C04B35/581Shaped ceramic products characterised by their composition; Ceramics compositions; Processing powders of inorganic compounds preparatory to the manufacturing of ceramic products based on non-oxide ceramics based on borides, nitrides, i.e. nitrides, oxynitrides, carbonitrides or oxycarbonitrides or silicides based on aluminium nitride
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
    • C23C14/0617AIII BV compounds, where A is Al, Ga, In or Tl and B is N, P, As, Sb or Bi
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02178Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02266Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by physical ablation of a target, e.g. sputtering, reactive sputtering, physical vapour deposition or pulsed laser deposition
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0332Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02538Group 13/15 materials
    • H01L21/0254Nitrides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/0257Doping during depositing
    • H01L21/02573Conductivity type
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/02631Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Materials Engineering (AREA)
  • Organic Chemistry (AREA)
  • Ceramic Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Inorganic Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Structural Engineering (AREA)
  • Physical Vapour Deposition (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

本发明大体涉及掺杂的氮化铝硬模以及制造掺杂的氮化铝硬模的方法。在形成所述氮化铝硬模时通过添加少量掺杂剂,例如氧,可显著降低所述硬模的湿蚀刻速率。此外,与无掺杂的氮化铝硬模相比,硬模的颗粒尺寸由于掺杂剂的存在而缩小。缩小的颗粒尺寸使硬模中的特征更平滑,导致使用所述硬模时更加精确的下层蚀刻。

Description

用于低蚀刻速率硬模膜的具有氧掺杂的PVD氮化铝膜
技术领域
本发明的实施方式大体涉及掺杂的氮化铝硬模(hardmask)以及制造掺杂的氮化铝硬模的方法。
背景技术
随着半导体器件尺寸持续缩小,形成此类小器件所需的精确度增加。不仅缩小半导体芯片尺寸已变得益发困难,更有甚者,缩小形成电气互连的个别特征的尺寸也变得益发困难。
制造半导体芯片要执行许多工艺。图案化是这些工艺中之一。在图案化工艺中,掩模,比如硬模,被形成在要被图案化的一或多个层之上。之后,使用所述硬模让下层或这些下层暴露至蚀刻剂,以除去暴露的材料(即未被所述硬模或光掩模覆盖的材料)并转印所述硬模的图案至所述下层或这些下层。
在理想的蚀刻工艺中,暴露材料被蚀刻而所述硬模不被蚀刻。换句话说,所述硬模理想上对蚀刻剂是惰性的,所述蚀刻剂可采用液态蚀刻剂或气态蚀刻剂的形态。若所述硬模对所述蚀刻剂是惰性的,则所述硬模的特征可很好地转印至所述下层或这些下层。
自然地,制造化学惰性的硬模并不实际。因此,硬模的一些蚀刻在意料之中。由于硬模被蚀刻,因此损害了图案转印的精确度。
因此,本领域中对用来从硬模转印图案至下层的蚀刻工艺是更加化学惰性的硬模有需要。
发明内容
本发明大体涉及掺杂的氮化铝硬模以及制造掺杂的氮化铝硬模的方法。在形成氮化铝硬模时通过添加少量掺杂剂,例如氧,能显著降低所述硬模的湿蚀刻速率。此外,与无掺杂的氮化铝硬模相比,硬模的颗粒尺寸由于掺杂剂的存在而缩小。缩小的颗粒尺寸使硬模内的特征更平滑,导致使用所述硬模时更加精确的下层蚀刻。
在一个实施方式中,硬模包含氮化铝与掺杂剂。在另一实施方式中,制造硬模的方法包含在含有惰性气体、含氮气体及含氧气体的气氛中溅射铝靶材,以形成氧掺杂的氮化铝材料,其中含氮气体的量比含氧气体的量的两倍更多。所述方法另外包含图案化所述氧掺杂的氮化铝材料以形成硬模。
在另一实施方式中,制造硬模的方法包含在含有惰性气体、含氮气体及含氧气体的气氛中溅射氮化铝靶材,以形成氧掺杂的氮化铝材料,其中含氮气体的量比含氧气体的量的两倍更多。所述方法另外包含图案化所述氧掺杂的氮化铝材料以形成硬模。
附图说明
为了能够详细了解本发明的上述特征,可通过参考实施方式得到上文简要概述的本发明的更具体的描述,这些实施方式的一些实施方式在附图中示出。但应注意到,附图仅示出本发明的典型实施方式,因此不应视为对本发明的范围的限制,因为本发明可允许其他等同效果的实施方式。
图1是根据一个实施方式的物理气相沉积(PVD)设备的简要截面图。
图2是形成在一层之上的硬模的简要截面图。
图3A和图3B分别示出未掺杂的氮化铝膜及氧掺杂的氮化铝膜的颗粒结构。
为了帮助理解,已尽可能使用相同的标记数字来表示各附图共有的相同元件。应理解到在一个实施方式中揭示的元件可有利地用于其他实施方式而不需特定详述。
具体实施方式
本发明大体涉及掺杂的氮化铝硬模以及制造掺杂的氮化铝硬模的方法。在形成氮化铝硬模时通过添加少量掺杂剂,例如氧,能显著降低硬模的湿蚀刻速率。此外,与无掺杂的氮化铝硬模相比,硬模的颗粒尺寸由于掺杂剂的存在而缩小。缩小的颗粒尺寸使硬模内的特征更平滑,导致使用所述硬模时更加精确的下层蚀刻。
图1是根据一个实施方式的PVD设备100的简要截面图。设备100包含腔室主体102。气体从气源104被输送至腔室主体102。溅射靶材108被设置在腔室主体102内与基板114相对。溅射靶材108被接合至背板106。从电源110施加偏压至背板106。基板114被设置在基板支撑件112上。可由电源116施加偏压于基板支撑件112。应了解基板支撑件112可电气漂浮或直接接地。电源110可包含DC电源、脉冲DC电源、AC电源或RF电源。背板106是导电的。
如上所述,本文揭示的实施方式涉及一种硬模及形成所述硬模的方法。图2是形成在层202之上的硬模204的简要截面图。硬模204已被图案化以使特征206形成在硬模204中,以暴露层202的部分208。在一个实施方式中,层202可包含钨。在另一实施方式中,层202可包含多晶硅。硬模204包含掺杂的氮化铝。掺杂剂可包含一或多种选自由氧、硅、氟、碳及这些物质的组合组成的群组的掺杂剂。硬模204可包含可高达25原子百分比的量的掺杂剂。
所述掺杂剂具有若干益处。当掺杂剂是氧时,氧能够控制硬模204的应力。当没有氧做为掺杂剂时,未掺杂的氮化铝硬模会有约400MPa的张应力。然而,氧能显著减少应力至非常低的张应力或甚至压应力。在一个实施方式中,应力水平是约0,以致硬模204内实质上无应力。硬模204的应力抵消全部下层的残余应力。因此,可调整硬模204的应力以抵消其上设置硬模204的结构的应力。
此外,氧掺杂剂缩小所形成的硬模204的颗粒尺寸。确切地说,与未掺杂的氮化铝硬模相比,氧掺杂的氮化铝硬模具有较小的颗粒尺寸。通过XRD(X射线衍射)分析测量时,未掺杂的氮化铝硬模具有[0002]峰。但是,氧掺杂的氮化铝硬模虽仍有[0002]峰,但氧掺杂的氮化铝硬模的[0002]峰的高度是未掺杂的氮化铝硬模[0002]峰的高度的约1/10。此外,氧掺杂的氮化铝硬模的密度比未掺杂的氮化铝硬模的密度低。
由于氧掺杂剂的存在,所形成的硬模有较小的颗粒尺寸(与未掺杂的氮化铝硬模相比),这使特征206更平滑,因而导致在蚀刻下层202的图案化工艺期间下层202的较陡(sharper)且较平直的蚀刻。此外,与未掺杂的氮化铝硬模相比,氧掺杂的氮化铝硬模具有低很多的蚀刻速率。确切地说,氧掺杂的氮化铝硬模在稀释的HF溶液(100:1)中具有每分钟约4埃的湿蚀刻速率,而未掺杂的氮化铝硬模具有每分钟约18埃的湿蚀刻速率。在一个实施方式中,因此,如上所述,虽然完全惰性的硬模无法通过添加诸如氧之类的掺杂剂形成,但更加耐受蚀刻的硬模通过使用诸如氧之类的掺杂剂而形成。由于更耐蚀刻的硬模,氧掺杂的氮化铝硬模在蚀刻工艺期间维持其结构(优于未掺杂的氮化铝硬模),因而在下层202中导致界定较佳的特征。
在形成氧掺杂的氮化铝硬模时,使用这样微量的氧以致少量至无铝-氧键形成。可通过在其之上含有层202的基板114对面提供铝靶材108来形成硬模204。从气源104将惰性气体、含氮气体及含氧气体全引到腔室主体102。由电源110施加电偏压至背板106,而基板114在基板支撑件112上电气接地。电源110施加DC电偏压至溅射靶材108,以在腔室主体内产生等离子体并从靶材108射出铝原子。这些铝原子与氮反应形成氮化铝。氧没有与铝反应因而对形成在基板114上的氮化铝层进行掺杂。在一个实施方式中,靶材108可包含氮化铝,而电源110包含RF电源。在一个实施方式中,溅射靶材可在毒化模式(poisoned mode)下操作,此时靶材包含铝,但氮化铝膜形成在暴露的靶材表面上。因此,在溅射工艺开始时,从溅射靶材溅射出氮化铝。
在一个实施方式中,含氮气体包含N2且含氧气体包含O2。惰性气体可包含氩。惰性气体与含氮气体的比可介于约1:1至约1:20之间。在一个实施方式中,惰性气体与含氮气体的比可以是约1:5。含氮气体与含氧气体的比大于2:1并且可介于约100:1至约20:1之间。在一个实施方式中,含氮气体与含氧气体的比可以是约50:3。
一旦沉积,氧掺杂的硬模可具有高达约25原子百分比的氧含量。在一个实施方式中,氧含量可高达约10原子百分比。可维持腔室主体102的腔室压力在约1毫托耳与约100毫托耳之间,以及基板支撑件112温度在约摄氏25度与约摄氏500度之间。可由电源110供给约1千瓦与约20千瓦之间的功率至溅射靶材108。所形成的掺杂的氮化铝硬模是多晶的。图3A和图3B分别示出未掺杂的氮化铝膜及氧掺杂的氮化铝膜的颗粒结构。如图3B所示,颗粒尺寸显著缩小。
通过使用掺杂剂,比如氧,可制造出与未掺杂的氮化铝硬模相比具有较慢的蚀刻速率的氮化铝硬模。此外,掺杂的氮化铝硬模有较小的颗粒尺寸,因此,图案化时有更平滑的表面。由此,掺杂的氮化铝硬模虽然并非化学惰性,但可容许在图案化工艺期间在掺杂的氮化铝硬模下的层中形成更精细、更复杂的特征。
虽然前述内容针对本发明的实施方式,但在不背离本发明的基本范围的情况下可设计出本发明的其他及进一步的实施方式,且本发明的范围由下面的要求保护的范围确定。

Claims (13)

1.一种硬模,包含:
氧掺杂的多晶氮化铝材料。
2.如权利要求1所述的硬模,其中所述氧以高达25原子百分比的量存在。
3.如权利要求2所述的硬模,其中所述硬模具有[0002]峰,所述[0002]峰比未掺杂的氮化铝硬模的硬模的[0002]峰小。
4.如权利要求3所述的硬模,其中所述硬模所具有的颗粒尺寸小于未掺杂的氮化铝硬模的颗粒尺寸,其中氧掺杂的氮化铝硬模的[0002]峰是所述未掺杂的氮化铝硬模的[0002]峰的尺寸的1/10。
5.如权利要求1所述的硬模,其中所述硬模具有在-5MPa与5MPa之间的应力。
6.一种制造硬模的方法,包含:
在含有惰性气体、含氮气体及含氧气体的气氛中溅射铝靶材,以沉积氧掺杂的多晶氮化铝材料,其中所述含氮气体的量比所述含氧气体的量的两倍更多;及
图案化所述氧掺杂的多晶氮化铝材料以形成所述硬模。
7.如权利要求6所述的方法,其中所述含氮气体包含N2
8.如权利要求7所述的方法,其中所述含氧气体包含O2
9.如权利要求8所述的方法,其中所述惰性气体与所述N2的比介于1:1至1:20之间,且其中所述N2与所述O2的比介于100:1至20:1之间。
10.如权利要求6所述的方法,其中在摄氏25度与摄氏500度之间的温度下发生溅射,且其中在1毫托耳与100毫托耳之间的腔室压力下发生溅射。
11.如权利要求6所述的方法,其中所述溅射是DC溅射或脉冲DC溅射。
12.一种制造硬模的方法,包含:
在含有惰性气体、含氮气体及含氧气体的气氛中溅射氮化铝靶材,以形成氧掺杂的多晶氮化铝材料,其中所述含氮气体的量比所述含氧气体的量的两倍更多;及
图案化所述氧掺杂的多晶氮化铝材料以形成所述硬模。
13.如权利要求12所述的方法,其中所述溅射是射频溅射。
CN201380014792.1A 2012-04-24 2013-04-18 用于低蚀刻速率硬模膜的具有氧掺杂的pvd氮化铝膜 Active CN104170068B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201261637804P 2012-04-24 2012-04-24
US61/637,804 2012-04-24
PCT/US2013/037245 WO2013163004A1 (en) 2012-04-24 2013-04-18 Pvd aln film with oxygen doping for a low etch rate hardmask film

Publications (2)

Publication Number Publication Date
CN104170068A CN104170068A (zh) 2014-11-26
CN104170068B true CN104170068B (zh) 2019-05-10

Family

ID=49483772

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201380014792.1A Active CN104170068B (zh) 2012-04-24 2013-04-18 用于低蚀刻速率硬模膜的具有氧掺杂的pvd氮化铝膜

Country Status (7)

Country Link
US (1) US9162930B2 (zh)
EP (1) EP2842158A4 (zh)
JP (1) JP6272830B2 (zh)
KR (1) KR102073414B1 (zh)
CN (1) CN104170068B (zh)
TW (1) TWI575605B (zh)
WO (1) WO2013163004A1 (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10675788B2 (en) * 2014-11-12 2020-06-09 Sharp Kabushiki Kaisha Method for producing mold
US11410937B2 (en) 2020-03-06 2022-08-09 Raytheon Company Semiconductor device with aluminum nitride anti-deflection layer
US12002773B2 (en) 2021-03-03 2024-06-04 Raytheon Company Hybrid pocket post and tailored via dielectric for 3D-integrated electrical device
US11894477B2 (en) 2021-05-17 2024-02-06 Raytheon Company Electrical device with stress buffer layer and stress compensation layer
US11851785B2 (en) 2021-05-21 2023-12-26 Raytheon Company Aluminum nitride passivation layer for mercury cadmium telluride in an electrical device
CN115377400B (zh) * 2022-10-26 2022-12-27 星恒电源股份有限公司 钠离子电池正极材料及其制备方法、正极极片和钠离子电池

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6177351B1 (en) * 1997-12-24 2001-01-23 Texas Instruments Incorporated Method and structure for etching a thin film perovskite layer
US6576482B1 (en) * 2002-05-07 2003-06-10 Texas Instruments Incorporated One step deposition process for the top electrode and hardmask in a ferroelectric memory cell
CN1846299A (zh) * 2003-08-29 2006-10-11 日本电气株式会社 氮化物半导体基底以及使用该基底的氮化物半导体装置
WO2009118514A1 (en) * 2008-03-25 2009-10-01 Aviza Technologies Limited Method of depositing an amorphus aluminium oxynitride layer by reactive sputtering of an aluminium target in a nitrogen / oxygen atmosphere
JP2011044493A (ja) * 2009-08-19 2011-03-03 Hitachi Kokusai Electric Inc 半導体装置の製造方法
CN102263175A (zh) * 2010-05-26 2011-11-30 北京北方微电子基地设备工艺研究中心有限责任公司 Led衬底及其制备方法

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6534809B2 (en) * 1999-12-22 2003-03-18 Agilent Technologies, Inc. Hardmask designs for dry etching FeRAM capacitor stacks
GB0116688D0 (en) * 2001-07-07 2001-08-29 Trikon Holdings Ltd Method of depositing aluminium nitride
WO2003026019A1 (en) * 2001-09-12 2003-03-27 Nec Corporation Semiconductor device and production method therefor
JP4024510B2 (ja) * 2001-10-10 2007-12-19 株式会社半導体エネルギー研究所 記録媒体、および基材
KR100532446B1 (ko) * 2003-07-10 2005-11-30 삼성전자주식회사 반도체 소자의 금속배선층 형성방법
US7157366B2 (en) * 2002-04-02 2007-01-02 Samsung Electronics Co., Ltd. Method of forming metal interconnection layer of semiconductor device
US20030221620A1 (en) 2002-06-03 2003-12-04 Semiconductor Energy Laboratory Co., Ltd. Vapor deposition device
US7045406B2 (en) 2002-12-03 2006-05-16 Asm International, N.V. Method of forming an electrode with adjusted work function
US6927651B2 (en) * 2003-05-12 2005-08-09 Agilent Technologies, Inc. Acoustic resonator devices having multiple resonant frequencies and methods of making the same
KR100636796B1 (ko) * 2005-08-12 2006-10-20 한양대학교 산학협력단 반도체 소자 및 그 제조방법
KR100753152B1 (ko) * 2005-08-12 2007-08-30 삼성전자주식회사 질화물계 발광소자 및 그 제조방법
TW200839874A (en) * 2007-03-16 2008-10-01 Au Optronics Corp Manufacturing method for low leakage aluminum nitride dielectric layer
JP4997448B2 (ja) * 2007-12-21 2012-08-08 独立行政法人産業技術総合研究所 窒化物半導体の製造方法および窒化物半導体デバイス
WO2009151767A2 (en) * 2008-04-21 2009-12-17 Honeywell International Inc. Design and use of dc magnetron sputtering systems
CN111326435B (zh) 2010-04-23 2023-12-01 株式会社半导体能源研究所 半导体装置的制造方法
WO2011142467A1 (en) 2010-05-14 2011-11-17 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US8467232B2 (en) 2010-08-06 2013-06-18 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US8422272B2 (en) 2010-08-06 2013-04-16 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and driving method thereof
CN103026416B (zh) 2010-08-06 2016-04-27 株式会社半导体能源研究所 半导体装置
US8467231B2 (en) 2010-08-06 2013-06-18 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and driving method thereof
US8446171B2 (en) 2011-04-29 2013-05-21 Semiconductor Energy Laboratory Co., Ltd. Signal processing unit

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6177351B1 (en) * 1997-12-24 2001-01-23 Texas Instruments Incorporated Method and structure for etching a thin film perovskite layer
US6576482B1 (en) * 2002-05-07 2003-06-10 Texas Instruments Incorporated One step deposition process for the top electrode and hardmask in a ferroelectric memory cell
CN1846299A (zh) * 2003-08-29 2006-10-11 日本电气株式会社 氮化物半导体基底以及使用该基底的氮化物半导体装置
WO2009118514A1 (en) * 2008-03-25 2009-10-01 Aviza Technologies Limited Method of depositing an amorphus aluminium oxynitride layer by reactive sputtering of an aluminium target in a nitrogen / oxygen atmosphere
JP2011044493A (ja) * 2009-08-19 2011-03-03 Hitachi Kokusai Electric Inc 半導体装置の製造方法
CN102263175A (zh) * 2010-05-26 2011-11-30 北京北方微电子基地设备工艺研究中心有限责任公司 Led衬底及其制备方法

Also Published As

Publication number Publication date
KR20150022755A (ko) 2015-03-04
JP6272830B2 (ja) 2018-01-31
US20130296158A1 (en) 2013-11-07
KR102073414B1 (ko) 2020-02-04
EP2842158A4 (en) 2015-12-02
JP2015515552A (ja) 2015-05-28
TWI575605B (zh) 2017-03-21
CN104170068A (zh) 2014-11-26
EP2842158A1 (en) 2015-03-04
WO2013163004A1 (en) 2013-10-31
US9162930B2 (en) 2015-10-20
TW201351503A (zh) 2013-12-16

Similar Documents

Publication Publication Date Title
CN104170068B (zh) 用于低蚀刻速率硬模膜的具有氧掺杂的pvd氮化铝膜
US6599178B1 (en) Diamond cutting tool
KR102513424B1 (ko) 스페이서 및 하드마스크 애플리케이션을 위한 실란 및 알킬실란 종으로부터의 보란 매개 탈수소화 프로세스
US8993454B2 (en) Ultra high selectivity doped amorphous carbon strippable hardmask development and integration
US20160099148A1 (en) Method of processing target object
US10658192B2 (en) Selective oxide etching method for self-aligned multiple patterning
JP2019519109A (ja) ハフニア及びジルコニアの蒸気相エッチング
JP2024096717A (ja) パターニング応用のための高密度炭素膜
JP7471492B2 (ja) 炭化タングステン膜の接着性及び欠陥を改善する技法
CN107424923A (zh) 一种自限制精确刻蚀硅的方法
CN109101756B (zh) 一种冗余图形添加方法
US10607852B2 (en) Selective nitride etching method for self-aligned multiple patterning
US20200190664A1 (en) Methods for depositing phosphorus-doped silicon nitride films
KR20230048108A (ko) 저응력 붕소 함유 층들의 증착
CN104347390A (zh) 一种等离子体刻蚀基片的方法
KR20110120675A (ko) 불순물을 이용한 불균일한 러프니스를 갖는 나노 스케일의 구조물 제조 방법

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant