CN104143901B - Control circuit of power converter and related control method - Google Patents

Abstract

The invention provides a control circuit of a power converter and a related control method, wherein one of the control circuits comprises a pulse width modulation signal generating circuit, a power estimation circuit and a current limiting signal generating circuit. The pulse width modulation signal generating circuit is used for generating a pulse width modulation signal according to the current sensing signal and the current limiting signal so as to set the conducting state of a switching circuit of the power converter and supply power to a load. The power estimation circuit is used for generating a power estimation signal to estimate the energy output to the load by the power converter. The current-limiting signal generating circuit generates a current-limiting signal according to the power estimation signal, so that the power conversion circuit can output proper energy to a load. The above embodiment can set the power converter to output sufficient energy to the load, and prevent the power converter from outputting excessive energy to the load to cause damage, so that the load can operate normally.

Description

Control circuit of power converter and related control method

technical field

The present invention relates to a control circuit of a power converter, in particular to a control circuit of a power converter capable of accurately controlling the maximum output power and a related control method.

Background technique

In electronic products, power converters are often used to convert input power into appropriate voltage signals or current signals to supply power to loads. In order to prevent the load of the power converter from being damaged due to receiving excessive energy, the control circuit of the power converter must accurately estimate and adjust the output energy of the power converter.

In general power converters, the control circuit often uses a simpler mechanism to estimate the energy output by the power converter. However, when the control circuit cannot accurately estimate the energy output by the power converter, the power converter may not be able to output enough energy to the load, resulting in abnormal operation of the load. In addition, when the power converter outputs too much energy to the load, it may cause damage to the load.

However, when the impedance values of the circuit components in the power converter vary greatly, the power converter is coupled to input power sources of different voltages, or when the voltage of the input power source changes, the control circuit often cannot accurately estimate Due to the energy output by the power converter, the power converter may not be able to output proper energy to the load, which may cause problems in system operation.

In addition, the power converter may operate in continuous current mode or discontinuous current mode. In these two operating modes, the control circuit of the general power converter cannot use the same mechanism to estimate the power The output energy of the converter needs to be estimated by using multiple sets of circuit structures, resulting in the complexity of control circuit design and the increase of hardware cost.

Contents of the invention

In view of this, how to control the circuit to accurately estimate and adjust the output energy of the power converter is a problem to be solved in the industry.

This specification provides an embodiment of a control circuit of a power converter, which is used to set the conduction state of a switch circuit of a power converter to supply power to a load. The control circuit includes: a current limiting signal generating circuit, which is set A current limiting signal is generated; a pulse width modulation signal generating circuit is configured to generate a pulse width modulation signal according to a current sensing signal and the current limiting signal, so as to set the conduction state of the current switch; and a A power estimation circuit configured to generate a power estimation signal according to the pulse width modulation signal, the current sensing signal and the current limiting signal; wherein the current limiting signal generation circuit compares the power estimation signal with a preset power signal comparison to generate the current limit signal; the power estimation circuit will be based on the current sensing signal at a third time point, and based on the current sensing signal at a fourth time point and the current sensing signal at a second time point A difference between the measured signals to generate the power estimation signal; the second time point is the time point when the pulse width modulation signal maintains a valid state and reaches a preset ratio; the third time point is later than the second Time point—a preset delay time; the fourth time point is a time point when the PWM signal changes from an active state to an inactive state.

This specification provides an embodiment of a control method of a power converter, which is used to set the conduction state of a switch circuit of a power converter to supply power to a load. The control method includes: generating a current limiting signal; according to a A pulse width modulation signal is generated by the current sensing signal and the current limiting signal to set the conduction state of the current switch; a power is generated according to the pulse width modulation signal, the current sensing signal and the current limiting signal estimate signal; and compare the power estimate signal with a preset power signal to generate the current limit signal; wherein the power estimate signal is based on the current sensing signal at a third time point, and based on a fourth time point Generated by a difference between the current sensing signal at a point and the current sensing signal at a second time point; the second time point is the time during which the PWM signal maintains an active state to a preset ratio point; the third time point is later than the second time point by a preset delay time; the fourth time point is the time point when the PWM signal changes from an active state to an inactive state.

One of the advantages of the above embodiment is that the control circuit can set the power converter to output enough energy to the load, and avoid damage caused by the power converter outputting too much energy to the load, so that the load can operate normally.

Another advantage of the above-described embodiment is that the power estimation signal used by the control circuit is not affected by the impedance value of the circuit components or the signal value of the input power source. Therefore, when the impedance value of the circuit element changes, the power converter is coupled to the input power of different voltage, or when the voltage of the input power changes, etc., the control circuit can still accurately estimate the output voltage of the power converter. Energy, so that the power converter outputs the appropriate energy to the load.

Another advantage of the above embodiment is that when the power converter operates in continuous current mode or discontinuous current mode, the control circuit can use the same mechanism to accurately estimate the output energy of the power converter and set the power converter to output an appropriate energy to load. Therefore, the complexity of the design of the control circuit and the cost of the hardware can be greatly reduced.

Other advantages of the present invention will be explained in more detail with the following description and accompanying drawings.

Description of drawings

The drawings described here are used to provide a further understanding of the application and constitute a part of the application. The schematic embodiments and descriptions of the application are used to explain the application and do not constitute an improper limitation to the application.

Fig. 1 is a simplified functional block diagram of a power converter according to an embodiment of the present invention

FIG. 2 is a simplified functional block diagram of an embodiment of the control circuit in FIG. 1 .

FIG. 3 is a simplified functional block of an embodiment of the power estimation circuit in FIG. 2 .

FIG. 4 is a simplified timing diagram of an embodiment of several signals in the power converter of FIG. 1 .

detailed description

Embodiments of the present invention will be described below with reference to the accompanying drawings. In these drawings, the same reference numerals represent the same or similar elements or method flows.

FIG. 1 is a simplified functional block diagram of a power converter 100 according to an embodiment of the present invention. The power converter 100 includes a transformer 110 , a first switch circuit 120 , a resistor 130 and a control circuit 140 for supplying power to a load 192 according to an input power 191 . To make the drawing concise and easy to explain, other components of the power converter 100 and related connections are not shown in FIG. 1 .

In the embodiment of FIG. 1, the transformer 110 is coupled to the input power source 191 and the load 192, the switch circuit 120 is coupled to the transformer 110 and the resistor 130, and one end of the resistor 130 is coupled to a preset potential V1 (for example, the potential of the ground terminal or other suitable potential). The control circuit 140 is coupled to the control terminal of the switch circuit 120 , and uses a pulse width modulation signal (PWM) to set the conduction state of the switch circuit 120 . In this embodiment, the switch circuit 120 is implemented in the form of a transistor. In other embodiments, the switch circuit 120 may also be implemented in the form of various suitable active and/or passive components.

The control circuit 140 is coupled to the resistor 130 , and can estimate the energy output from the power converter 100 to the load 192 according to the current sensing signal Vcs at one end of the resistor 130 to adjust the conduction state of the switch circuit 120 .

FIG. 2 is a simplified functional block diagram of an embodiment of the control circuit 140 of FIG. 1 . In the embodiment of FIG. 2 , the control circuit 140 includes a PWM signal generation circuit 210 , a power estimation circuit 230 and a current limit signal generation circuit 250 . In order to make the drawing concise and easy to explain, other components and related connections of the control circuit 140 are not shown in FIG. 2 .

The pulse width modulation signal generation circuit 210 is configured to generate a pulse width modulation signal PWM according to the current sensing signal Vcs and the current limit signal Vcl, so as to use the pulse width modulation signal PWM to set the conduction state of the switch circuit 120 . The PWM signal generation circuit 210 turns on the switch circuit 120 intermittently, so that the power converter 100 provides the required energy to the load 192 . When the current sensing signal Vcs is greater than the current limiting signal Vcl, it means that the power converter 100 has provided enough energy to the load 192, and the pulse width modulation signal generating circuit 21 sets the switch circuit 120 to present a non-conducting state, so as to avoid the power converter 100 continues to provide energy to load 192 without causing damage to load 192 .

In the embodiment of FIG. 2 , the PWM signal generation circuit 210 includes a periodic signal generation circuit 211 , a first comparison circuit 213 and an SR latch (SR latch) circuit 215 . The period signal generation circuit 211 is configured to generate the period signal Vp, and output the period signal Vp to the S input terminal of the SR latch circuit 215 . For example, the periodic signal generation circuit 211 can generate periodic signals such as pulse wave, square wave, sinusoidal wave and ramp. The comparison circuit 213 generates a reset signal Vreset according to the current sensing signal Vcs and the current limit signal Vcl, and outputs the reset signal Vreset to the R input terminal of the SR latch circuit 215 . Therefore, when the period signal Vp is at a high potential, the pulse width modulation signal PWM provided by the Q output terminal of the SR latch circuit 215 is correspondingly set at a high potential, so that the switch circuit 120 is in an on state. When the current sensing signal Vcs is greater than the current limiting signal Vcl, the comparison circuit 213 will set the reset signal Vreset to a high potential, and the pulse width modulation signal PWM provided by the Q output terminal of the SR latch circuit 215 will be correspondingly set to A low potential makes the switch circuit 120 in a non-conductive state. In other embodiments, the pulse width modulation signal generation circuit 210 may also be implemented with other suitable circuit structures to provide the required pulse width modulation signal PWM.

The power estimating circuit 230 is configured to generate a power estimating signal Vspc according to the current sensing signal Vcs, the current limiting signal Vcl and the pulse width modulation signal PWM, so as to estimate the output of the power converter 100 to the load 192 according to the signal value of the power estimating signal Vspc energy of.

The current-limit signal generating circuit 250 is configured to adjust the signal value of the current-limit signal Vcl according to the preset power signal Vspt and the power estimation signal Vspc.

In the embodiment of FIG. 2 , the current limiting signal generating circuit 250 includes a second comparison circuit 251 , a second switch circuit 253 , and resistors 255 and 257 . When the power estimation signal Vspc is smaller than the preset power signal Vspt, the comparison circuit 251 will provide a high potential output signal to turn on the switch circuit 253, the output current of the switch circuit 253 passes through the resistors 255 and 257, and is between the resistors 255 and 257 The node produces the required current-limiting signal Vcl. When the estimated power signal Vspc is greater than the preset power signal Vspt, the comparator circuit 251 will provide an output signal with a low potential, so that the switch circuit 253 is in a non-conductive state. In other embodiments, the current-limit signal generating circuit 250 can also be implemented with other suitable circuit structures to generate the required current-limit signal Vcl. Therefore, the required current limiting signal Vcl can be generated by setting the signal value of the preset power signal Vspt, so that the PWM signal generating circuit 210 can set the conduction state of the switch circuit 120 according to the current limiting signal Vcl, The power converter 100 can output the required energy to the load 192 .

In the embodiment of FIG. 2 , the switch circuit 253 is coupled to the second preset potential V2 , for example, the potential V2 can be set to 5 volts or other suitable potentials. The resistor 257 is coupled to the third preset potential V3, for example, the potential V3 can be set as the potential of the ground terminal or other suitable potentials.

FIG. 3 is a simplified functional block of an embodiment of the power estimation circuit 230 in FIG. 2 . In the embodiment of FIG. 3, the power estimation circuit 230 includes a phase-locked loop circuit 310, a delay circuit 320, pulse signal generation circuits 331 and 332, switch circuits 335, 336 and 337, capacitors 341, 342 and 343, transconductance A transconductance circuit 350 , comparison circuits 361 , 362 and 363 , an inversion circuit 370 , SR latch circuits 381 and 382 , and a ramp signal generation circuit 390 . In order to make the drawing concise and easy to explain, other components and related connections of the power estimation circuit 230 are not shown in FIG. 3 .

The phase-locked loop circuit 310 will generate a half-width signal PWMh according to the pulse width modulation signal PWM, and maintain the half-width signal PWMh in an active state (for example, the signal is high when the signal is active at a high level, and the signal is at an active low when it is indicated The time of low potential) is set as a preset ratio of the time that the pulse width modulation signal PWM maintains an active state. For example, in this embodiment, the preset ratio is set to 1/2.

The inversion circuit 370 inverts the pulse width modulation signal PWM to transmit to the S input terminal of the SR latch circuit 381 . The comparison circuit 361 performs a comparison operation on the reference signal Vref and the current sensing signal Vcs to transmit to the R input terminal of the SR latch circuit 381 . The SR latch circuit 381 provides the delay time signal Tdelay to the delay circuit 320 at the Q output terminal.

The delay circuit 320 correspondingly delays the half-width signal PWMh according to the delay time signal Tdelay to generate the half-width delayed signal PWMhd. The half-width signal PWMh and the half-width delayed signal PWMh maintain the same valid state, and the half-width delayed signal PWMh maintains the valid state later than the half-width signal PWM maintains the valid state. According to the delay time signal Tdelay, the delay circuit 320 correspondingly sets the time gap between the time when the half-width delay signal PWMh is in the active state and the time when the half-width signal PWM is in the active state to be proportional to the delay time signal Tdelay.

The pulse signal generating circuits 331 and 332 respectively set the conduction states of the third switch circuit 335 and the fourth switch circuit 336 according to the half-width signal PWMh and the half-width delay signal PWMhd, so as to respectively control the current sensing signal Vcs on the first switch circuit. The charging or discharging time of the first capacitor 341 and the second capacitor 342 .

The transconductance circuit 350 generates a current signal Itx correspondingly according to the voltage value Vtx on both sides of the capacitor 341 , so that the current signal Itx and the voltage value Vtx exhibit a proportional relationship.

The ramp signal generation circuit 390 is configured to generate the ramp signal Var. The comparison circuit 362 compares the voltage value of the capacitor 342 with the ramp signal Var, and outputs the comparison result to the S input terminal of the SR latch circuit 382 . The comparison circuit 363 compares the current-limit signal Vcl with the ramp signal Var, and outputs the comparison result to the R input terminal of the SR latch circuit 382 . The Q output terminal of the SR latch circuit 382 correspondingly generates a switch control signal Tdelta to set the conduction state of the fifth switch circuit 337 . Therefore, the power estimation circuit 230 can adjust the charging time of the third capacitor 343 by the current signal Itx through the switch control signal Tdelta, so as to generate the required power estimation signal Vspc.

In the embodiment of FIG. 3 , the capacitors 341 , 342 and 343 are all coupled to the fourth preset potential V4 (for example, the potential of the ground terminal or other suitable potentials). In other embodiments, the capacitors 341 , 342 and 343 may also be coupled to the same or different potentials according to different design considerations, and the embodiment of FIG. 3 is modified accordingly.

FIG. 4 is a simplified timing diagram of an embodiment of several signals in the power converter 100 of FIG. 1 . The following will further illustrate how the control circuit 140 estimates the output power of the power converter 100 with reference to FIGS. 1 to 4 . In the embodiment of FIG. 4 , the time point T0 is the time point when the pulse width modulation signal PWM changes from an inactive state to an active state. The first time point T1 is a time point when the current sensing signal Vcs changes corresponding to the signal value corresponding to the change of the pulse width modulation signal PWM at the time point T0. The second time point T2 is a time point when the pulse width modulation signal PWM maintains an active state and reaches a preset ratio. For example, in the embodiment of FIG. 4 , the preset ratio is set to 1/2, that is, T2=(T0+T4)/2. The third time point T3 is a time point when the current sensing signal Vcs changes corresponding to the signal value corresponding to the change of the pulse width modulation signal PWM at the time point T2. The fourth time point T4 is a time point when the pulse width modulation signal PWM changes from an active state to an inactive state. The fifth time point T5 is a time point when the current sensing signal Vcs changes corresponding to the signal value corresponding to the change of the pulse width modulation signal PWM at the time point T4.

The embodiment of FIG. 4 shows the pulse width modulation signal PWM generated by the control circuit 140 and the current sensing signal Vcs detected at one end of the resistor 130 . When the control circuit 140 uses the pulse width modulation signal PWM to turn on the switch circuit 120 at the time point T0, the transformer 110 and the switch circuit 120 need a preset delay time Td to transmit the current to the resistor 130 correspondingly. Therefore, at the first time point T1, the control circuit 140 detects the corresponding current sensing signal Vcs at the resistor 130 .

In this embodiment, the load 192 is located on the secondary side of the transformer 110 , and the energy provided by the power converter 100 on the primary side is proportional to the energy received by the load on the secondary side. From the first time point T0 to the fourth time point T4, the energy P=(I(T4)×I(T4)-I(T0)×I(T0))×L provided by the power converter 100 on the primary side /2, where I(T0) and I(T4) are the currents provided by the transformer 110 at the primary side at time points T0 and T4 respectively, and L is the inductance of the transformer 110 .

Corresponding to the currents I(T0) and I(T4) provided by the transformer 110 at time points T0 and T4, the control circuit 140 receives corresponding current sensing signals Vcs(T1) and Vcs( T5), Vcs(T1)=I(T0)/R, Vcs(T5)=I(T4)/R, T1=T0+Td, T5=T4+Td, wherein R is the resistance value of the resistor 130. Therefore, the energy P=(Vcs(T5)×Vcs(T5)-Vcs(T1)×Vcs(T1))×L/(2×R×R)=(Vcs( T5)+Vcs(T1))×(Vcs(T5)–Vcs(T1))×L/(2×R×R).

In the embodiment of Fig. 4, the second time point T2=(T0+T4)/2, the third time point T3=(T1+T5)/2, wherein T1=T0+Td, T3=T2+Td, T5 =T4+Td. In addition, from the first time point T1 to the fifth time point T5, the current sensing signal Vcs substantially exhibits a linear change. Therefore, the current sensing signal Vcs( T3 )=(Vcs( T5 )+Vcs( T1 ))/2 at the third time point T3 . Furthermore, Vcs(T5)−Vcs(T1)=2×(Vcs(T5)−Vcs(T3))=2×(Vcs(T4)−Vcs(T2)). The energy P=2×Vcs(T3)×2×(Vcs(T4)−Vcs(T2))×L/(2×R×R)=Vcs(T3)×( Vcs(T4)-Vcs(T2))×K, where K=2×L/(R×R), that is, the energy P provided by the power converter 100 on the primary side will be presented with the signal value of Vcs(T3) proportional relationship, and presents a proportional relationship with the signal value of (Vcs(T4)-Vcs(T2)).

Therefore, the power estimation circuit 230 can accurately generate the required power estimation signal Vspc according to Vcs( T3 ) and (Vcs( T4 )−Vcs( T2 )). In addition, because the signal value of Vcs(T5) is not easy to measure accurately, the power estimation circuit 230 of this embodiment does not rely on the signal value of (Vcs(T5)−Vcs(T3)), but on the basis of (Vcs(T4)− The signal value of Vcs(T2)) generates the estimated power signal Vspc, avoiding the need to use the less accurate signal value of Vcs(T5) to accurately generate the desired estimated power signal Vspc.

In the embodiment of FIG. 3, the inverter circuit 370, the comparison circuit 361, and the SR latch circuit 381 are configured to generate a delay time corresponding to the preset delay time Td according to the pulse width modulation signal PWM, the reference signal Vref, and the current sensing signal Vcs. The delay time signal Tdelay. In one embodiment, the reference signal Vref is set to a value close to 0 (for example, 0.1 volts or other suitable values), and when the pulse width modulation signal PWM presents a low potential at time point S4, the inverter circuit 370 will generate The high potential output signal is sent to the S input terminal of the SR latch circuit 381 , so that the Q output terminal of the SR latch circuit 381 presents a high potential. When the current sensing signal Vcs is smaller than the reference signal Vref near the time point S5, the comparison circuit 361 generates a high potential output signal to the R input terminal of the SR latch circuit 381, so that the Q output terminal of the SR latch circuit 381 exhibits a low potential. Therefore, the delay time signal Tdelay output from the Q output terminal of the SR latch circuit 381 will be in an active state at the time points S4 to S5 , and will be proportional to the preset delay time Td between the time points S4 to S5 .

Since the delay circuit 320 correspondingly delays the half-width signal PWMh according to the delay time signal Tdelay, to generate the half-width delayed signal PWMhd. The phase-locked loop circuit 310, the delay circuit 320 and the pulse signal generating circuit 331 will set the switch circuit 335 to be in a conduction state from the time point T1 (ie T0+Td) to T3 (ie T2+Td), so that the current sensing signal Vcs After the capacitor 341 is charged or discharged, the signal value of the voltage Vtx on both sides of the capacitor 341 is proportional to the signal value of Vcs(T3). Therefore, the current signal Itx generated by the transconductance circuit 350 according to the voltage value Vtx is proportional to the signal value of Vcs(T3).

The PLL circuit 310 and the pulse signal generating circuit 332 set the switch circuit 336 to be turned on at time points T0 to T2, so that the current sensing signal Vcs charges or discharges the capacitor 342 to the signal value of Vcs(T2). In addition, at the time point T4, the current sensing signal Vcs (T4) is greater than or equal to the current limiting signal Vcl, and the pulse width modulation signal generation circuit 21 will set the pulse width modulation signal PWM to a low potential, so the current limiting signal Vcl It is substantially equal to Vcs(T4).

Therefore, the comparison circuit 362, the comparison circuit 363 and the SR latch circuit 382 will correspondingly generate the switch control signal Tdelta according to the signal value of Vcs(T2), the signal value of Vcs(T4) and the ramp signal Var, so as to set the switch circuit 337 conduction state. The comparison circuit 362 will compare the signal value of Vcs(T2) with the ramp signal Var, and when the ramp signal Var is greater than the signal value of Vcs(T2), the comparison circuit 362 will generate a high potential output signal to the SR latch circuit 382 The S input makes the switch control signal Tdelta generated by the Q output of the SR latch circuit 382 present a high potential state. The comparison circuit 363 will compare the signal value of Vcs(T4) with the ramp signal Var, and when the ramp signal Var is greater than the signal value of Vcs(T4), the comparison circuit 363 will generate a high potential output signal to the SR latch circuit 382 The R input terminal makes the switch control signal Tdelta generated by the Q output terminal of the SR latch circuit 382 present a low potential state. Therefore, the time when the switch control signal Tdelta is in a valid state will be proportional to the value of (Vcs(T4)-Vcs(T2)), and the conduction time of the switch 337 can be set so that the charging time of the current signal Itx to the capacitor 343 It is proportional to (Vcs(T4)-Vcs(T2)).

In the embodiment of FIG. 3 , the signal value of the power estimation signal Vspc is proportional to the current signal Itx, and is proportional to the signal value of the current sensing signal Vcs(T3) at the third time point T3. In addition, the signal value of the power estimation signal Vspc is proportional to the time when the current signal Itx charges the capacitor 337, and is related to the current sensing signal Vcs(T4) at the fourth time T4 and the current sensing signal Vcs at the second time T2. The difference (Vcs(T4)-Vcs(T2)) between (T2) exhibits a proportional relationship. Therefore, the signal value of the power estimation signal Vspc can be accurately used to estimate the energy P provided by the power converter 100 on the primary side, so that the control circuit 140 can accurately set the energy output from the power converter 100 to the load 192 .

In the embodiment of FIG. 3 , the circuit block 301 includes a phase-locked loop circuit 310, a delay circuit 320, a pulse signal generation circuit 331, a switch circuit 335, a capacitor 341, a transconductance circuit 350, a comparison circuit 361, and an inverting circuit. 370 and an SR latch circuit 381 for generating a current signal Itx that is proportional to the current sensing signal Vcs(T3). The circuit block 302 includes a pulse signal generation circuit 332, a switch circuit 336, a capacitor 342, comparison circuits 362 and 363, an SR latch circuit 382, and a ramp signal generation circuit 390, and can be operated with the phase-locked loop circuit 310 to The time for the switch control signal Tdelta to be in a valid state is proportional to (Vcs(T4)−Vcs(T2)).

In another embodiment, the current signal Itx can also be set to have a proportional relationship with (Vcs(T4)-Vcs(T2)) by appropriately modifying the embodiment shown in FIG. The effective state time is proportional to Vcs (T3), so that the signal value of the power estimation signal Vspc can be accurately used to estimate the energy P provided by the power converter 100 on the primary side, so that the control circuit 140 can accurately set the power conversion The energy output by the device 100 to the load 192.

In the above embodiments, the power converter 100 operates in the continuous current mode, and the value of Vcs(T1) is not zero. In other embodiments, when the power converter 100 operates in discontinuous current mode, the value of Vcs(T1) is 0, according to the above formula, the signal value of the power estimation signal Vspc can still be accurately used to estimate the power converter 100 The energy P provided on the primary side. Therefore, no matter whether the control circuit 140 operates in the continuous current mode or the discontinuous current mode, it can precisely set the energy output from the power converter 100 to the load 192 .

In the above-mentioned embodiments, each functional block can be realized by one or more circuit elements, and multiple functional blocks can also be integrated into a single circuit element. For example, the periodic signal generating circuit 211 of the PWM signal generating circuit 210 may also be disposed outside the control circuit 140 , and the switch circuit 120 and the control circuit 120 may also be disposed on the same integrated circuit chip.

In the above-mentioned embodiments, each signal and functional block are respectively implemented in an active high manner. In other embodiments, each signal and functional block can be implemented in an active-high or active-low manner according to different design considerations.

It can be seen from the foregoing description that the above-mentioned embodiment can accurately estimate the energy P provided by the power converter 100 on the primary side through the current sensing signal, and can accurately set the energy output from the power converter 100 to the load 192 . Therefore, the control circuit can set the power converter to output enough energy to the load, and avoid the damage caused by the power converter outputting too much energy to the load, so that the load can operate normally

It can be seen from the above formula that the estimated power signal Vspc used in the above embodiment will not be affected by the impedance value of the circuit element or the signal value of the input power. Therefore, when the impedance value of the circuit element changes, the power converter is coupled to the input power of different voltage, or when the voltage of the input power changes, etc., the control circuit can still accurately estimate the output voltage of the power converter. Energy, so that the power converter outputs the appropriate energy to the load.

In addition, regardless of whether the power converter operates in continuous current mode or discontinuous current mode, in both modes of operation, the control circuit can use the same mechanism to accurately estimate the output energy of the power converter and set the power conversion The converter outputs appropriate energy to the load. Therefore, the complexity of the design of the control circuit and the cost of the hardware can be greatly reduced.

Certain terms are used in the description and claims to refer to particular elements. Those skilled in the art may use different terms for the same element. The specification and claims do not use the difference in name as a way to distinguish components, but use the difference in function of components as a basis for distinction. The "comprising" mentioned in the description and the claims is an open term and should be interpreted as "including but not limited to". In addition, the term "coupled" herein includes any direct and indirect means of connection. Therefore, if it is described in the text that the first element is coupled to the second element, it means that the first element can be directly connected to the second element through electrical connection or signal connection means such as wireless transmission or optical transmission, or through other elements or connections. The means is indirectly electrically or signally connected to the second element.

The description of "and/or" used herein includes any combination of one or more of the listed items. In addition, unless otherwise specified in the specification, any singular term also includes plural meanings.

The above description is only an embodiment of the present application, and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and changes. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included within the scope of the claims of the present application.

Claims (8)

1. A control circuit of a power converter, used to set the conduction state of a switch circuit of a power converter to supply power to a load, characterized in that the control circuit comprises: A current-limiting signal generating circuit, configured to generate a current-limiting signal; a pulse width modulation signal generating circuit configured to generate a pulse width modulation signal according to a current sensing signal and the current limiting signal to set the conduction state of the current switch; and a power estimation circuit configured to generate a power estimation signal according to the pulse width modulation signal, the current sensing signal and the current limiting signal; Wherein the current limiting signal generating circuit compares the power estimation signal with a preset power signal to generate the current limiting signal; the power estimation circuit will base on the current sensing signal at a third time point and a first A difference between the current sensing signal at four time points and the current sensing signal at a second time point to generate the power estimation signal; the second time point maintains an active state for the PWM signal A time point at which a preset ratio is reached; the third time point is later than the second time point by a preset delay time; the fourth time point is a time point at which the PWM signal changes from an active state to an inactive state; The power estimation circuit sets the current sensing signal to charge a first capacitor according to the pulse width modulation signal and a delay time signal, and generates a current signal according to a voltage value of the first capacitor, so that the The current signal is proportional to the current sensing signal at the third time point. 2. The control circuit according to claim 1, wherein the power estimating circuit generates a switch control signal according to the pulse width modulation signal and the current limiting signal, and the time for which the switch control signal maintains an effective state It is proportional to the difference between the current sensing signal at the fourth time point and the current sensing signal at the second time point; the switch control signal is used to set the conduction state of a fifth switch circuit , to set the current signal to charge a third capacitor to generate the power estimation signal. 3. A control circuit of a power converter, used to set the conduction state of a switch circuit of a power converter to supply power to a load, characterized in that the control circuit comprises: A current-limiting signal generating circuit, configured to generate a current-limiting signal; a pulse width modulation signal generating circuit configured to generate a pulse width modulation signal according to a current sensing signal and the current limiting signal to set the conduction state of the current switch; and a power estimation circuit configured to generate a power estimation signal according to the pulse width modulation signal, the current sensing signal and the current limiting signal; Wherein the current limiting signal generating circuit compares the power estimation signal with a preset power signal to generate the current limiting signal; the power estimation circuit will base on the current sensing signal at a third time point and a first A difference between the current sensing signal at four time points and the current sensing signal at a second time point to generate the power estimation signal; the second time point maintains an active state for the PWM signal A time point at which a preset ratio is reached; the third time point is later than the second time point by a preset delay time; the fourth time point is a time point at which the PWM signal changes from an active state to an inactive state; The power estimation circuit sets the current sensing signal to charge a first capacitor according to the pulse width modulation signal and the current limiting signal, and generates a current signal according to a voltage value of the first capacitor, so that the The current signal is proportional to the difference between the current sensing signal at the fourth time point and the current sensing signal at the second time point. 4. The control circuit according to claim 3, wherein the power estimating circuit generates a switch control signal according to the pulse width modulation signal and a delay time signal, and the time for which the switch control signal maintains an effective state It has a proportional relationship with the current sensing signal at the third time point; the switch control signal is used to set the conduction state of a fifth switch circuit, so as to set the current signal to charge a third capacitor to generate the power estimation signal . 5. A control method of a power converter, used to set the conduction state of a switch circuit of a power converter to supply power to a load, characterized in that the control method comprises: Generate a current limiting signal; generating a pulse width modulation signal according to a current sensing signal and the current limiting signal to set the conduction state of the current switch; generating a power estimation signal according to the pulse width modulation signal, the current sensing signal and the current limit signal; and comparing the estimated power signal with a preset power signal to generate the current limiting signal; setting the current sensing signal to charge a first capacitor according to the pulse width modulation signal and a delay time signal; and generating a current signal according to a voltage value of the first capacitor, so that the current signal is proportional to the current sensing signal at a third time point; Wherein the power estimation signal is based on the current sensing signal at the third time point, and based on a difference between the current sensing signal at a fourth time point and the current sensing signal at a second time point and generated; the second time point is the time point when the pulse width modulation signal maintains an effective state and reaches a preset ratio; the third time point is later than the second time point by a preset delay time; the fourth time point is the time point when the PWM signal changes from an active state to an inactive state. 6. The control method according to claim 5, further comprising: A switch control signal is generated according to the pulse width modulation signal and the current limiting signal, and the time for the switch control signal to maintain an effective state is related to the current sensing signal at the fourth time point and the current at the second time point The difference between the sensing signals is proportional; and The switch control signal is used to set the conduction state of a fifth switch circuit, so as to set the current signal to charge a third capacitor to generate the power estimation signal. 7. A control method for a power converter, used to set the conduction state of a switch circuit of a power converter to supply power to a load, characterized in that the control method comprises: Generate a current limiting signal; generating a pulse width modulation signal according to a current sensing signal and the current limiting signal to set the conduction state of the current switch; generating a power estimation signal according to the pulse width modulation signal, the current sensing signal and the current limit signal; and comparing the estimated power signal with a preset power signal to generate the current limiting signal; setting the current sensing signal to charge a first capacitor according to the pulse width modulation signal and the current limiting signal; and A current signal is generated according to a voltage value of the first capacitor, so that a difference between the current signal and the current sensing signal at a fourth time point and the current sensing signal at a second time point appears ratio; Wherein the power estimation signal is based on the current sensing signal at a third time point, and based on the difference between the current sensing signal at the fourth time point and the current sensing signal at the second time point and generated; the second time point is the time point when the pulse width modulation signal maintains an effective state and reaches a preset ratio; the third time point is later than the second time point by a preset delay time; the fourth time point is the time point when the PWM signal changes from an active state to an inactive state. 8. The control method according to claim 7, further comprising: generating a switch control signal according to the pulse width modulation signal and a delay time signal, so that the time during which the switch control signal maintains an effective state is proportional to the current sensing signal at the third time point; and The switch control signal is used to set the conduction state of a fifth switch circuit, so as to set the current signal to charge a third capacitor to generate the power estimation signal.