CN104135276B - A kind of Wireless RF transmitter - Google Patents

Abstract

The invention discloses a wireless radio frequency transmitting device, which includes: a frequency and phase detector, a charge pump, a loop filter and a twin voltage-controlled oscillator; wherein, the twin voltage-controlled oscillator includes a first a voltage-controlled oscillator and a second voltage-controlled oscillator, wherein when the twin voltage-controlled oscillators are in a receiving mode, the first voltage-controlled oscillator and the second voltage-controlled oscillator are coupled to each other to form a quadrature A voltage-controlled oscillator, the quadrature voltage-controlled oscillator forms a phase-locked loop with the frequency and phase detector, charge pump, and loop filter to generate a quadrature carrier wave for receiving information; when the twin voltage When the oscillator is in the transmission mode, the first voltage-controlled oscillator forms a phase-locked loop with the frequency and phase detector, charge pump, and loop filter, and the second voltage-controlled oscillator is used for transmitting The data is frequency modulated. The invention can keep the carrier frequency stable while transmitting high data rate, and has very short frequency hopping locking time.

Description

A radio frequency transmitter

technical field

The invention relates to the technical field of wireless radio frequency communication circuits, in particular to the field of radio frequency communication circuits requiring high-speed transmission and high energy efficiency.

Background technique

With the rapid development of wireless communication technology, the demand for low-power high-speed radio frequency transmitters is also increasing. Examples include wireless capsule endoscopy and neural recording applications that require transmission of high data rates.

Due to the constant envelope characteristic of frequency shift keying modulation, high-efficiency non-linear power amplifiers can be used in the transmitter, so this modulation method has been widely used in occasions requiring low-power transmission.

At present, the transmitters that can be used for frequency shift keying mainly include structures based on mixers and structures based on phase-locked loops. The transmitter based on the mixer structure has high flexibility and can be used for different kinds of modulations, but this structure requires high power consumption of digital-to-analog converters and mixers, so it is not suitable for low-power applications.

For the transmitter based on the phase-locked loop structure, there are roughly four implementation methods at present. One is to add the modulation signal to the frequency divider. This method is simple and has high accuracy. However, for the modulation signal, the phase-locked loop exhibits low-pass filtering characteristics, so the transmitted data rate is limited by the phase-locked loop. loop bandwidth. The second method is closed-loop voltage-controlled oscillator modulation. In this method, the modulation data is directly added to the locked voltage-controlled oscillator. In this case, the phase-locked loop exhibits high-pass filter characteristics for the modulation signal, so the modulation signal Low frequency components will be destroyed. The third method is to add the modulation signal to the frequency divider and the voltage-controlled oscillator at the same time. This modulation transmission method is also called two-point modulation. This modulation method combines the advantages of the previous two methods. Ideally , if the high-pass path and the low-pass path are perfectly matched, then the transmitted signal data rate will not be limited by the loop bandwidth of the PLL. However, the requirements for the gain and bandwidth matching of the two signal paths increase the design complexity and power consumption of the system. The fourth method is open-loop voltage-controlled oscillator modulation. This modulation method first locks the voltage-controlled oscillator on a certain transmit carrier frequency through the phase-locked loop, and then disconnects the phase-locked loop, and directly adds the modulation signal to the voltage-controlled oscillator. controlled oscillator, so that the transmit data rate will get rid of the limitation of the loop bandwidth of the phase-locked loop. However, since the phase-locked loop is in an open-loop state during the transmission process, the oscillation frequency of the voltage-controlled oscillator is prone to frequency drift. Frequency drift is generally caused by leakage current, external interference and ambient temperature changes.

Contents of the invention

(1) Technical problems to be solved

The main purpose of the present invention is to provide a high-speed and low-power wireless radio frequency transmitting device, which can not only transmit high data rate signals, but also keep the carrier stable, so that it can be applied to high data rate applications such as medical electronics.

(2) Contents of the invention

The invention provides a wireless radio frequency transmitting device, which includes: a frequency and phase detector, a charge pump, a loop filter and a twin voltage-controlled oscillator;

Wherein, the twin voltage-controlled oscillators include a first voltage-controlled oscillator and a second voltage-controlled oscillator with the same structure, wherein, when the twin voltage-controlled oscillators are in the receiving mode, the first voltage-controlled The oscillator and the second voltage-controlled oscillator are mutually coupled to form an orthogonal voltage-controlled oscillator, and the orthogonal voltage-controlled oscillator forms a phase-locked loop with the frequency and phase detector, charge pump, and loop filter, Generate a quadrature carrier wave for receiving information; when the twin voltage-controlled oscillators are in the transmit mode, the first voltage-controlled oscillator forms a phase-lock with the frequency and phase detector, charge pump, and loop filter In a loop, the second voltage-controlled oscillator is used for frequency modulation of transmitted data.

Wherein, the twin voltage-controlled oscillator further includes: a first coupling branch and a second coupling branch, wherein the output terminal of the first voltage-controlled oscillator is connected to the first coupling branch and the second coupling branch respectively. The input terminals of the coupling branch are connected, and the output terminals of the second voltage-controlled oscillator are respectively connected with the input terminals of the first coupling branch and the second coupling branch.

Wherein, when the first coupling branch and the second coupling branch add current, the first voltage-controlled oscillator and the second voltage-controlled oscillator are performed through the first coupling branch and the second coupling branch coupled to form a quadrature voltage-controlled oscillator, the twin voltage-controlled oscillators switched to receive mode;

After the currents of the first coupling branch and the second coupling branch are disconnected, the first voltage-controlled oscillator and the second voltage-controlled oscillator are decoupled, and the twin voltage-controlled oscillators are switched to a transmission mode.

Wherein, the oscillation frequencies of the first voltage-controlled oscillator and the second voltage-controlled oscillator are controlled by the first frequency control signal.

Wherein, the frequency and phase detector, the charge pump and the loop filter adjust the first frequency control signal according to the feedback value of the output frequency of the twin voltage-controlled oscillator.

The device also includes:

A frequency preset module is used for the phase-locked loop to preset the frequency of the twin voltage-controlled oscillator during frequency hopping.

Wherein, the frequency preset module changes the first frequency control signal according to a first frequency preset control word.

Wherein, the oscillation frequencies of the first voltage-controlled oscillator and the second voltage-controlled oscillator are also controlled by the second frequency preset control word.

Wherein, the first frequency preset control word and the second frequency preset control word are preset according to the target frequency to which the twin voltage-controlled oscillators will jump.

The device further includes: a digital processor, which samples the output frequency of the twin voltage-controlled oscillator when powered on, so as to obtain the output frequency of the twin voltage-controlled oscillator and the first frequency preset Correspondence between the preset control word and the second frequency preset control word.

(3) Beneficial effects

As can be seen from the foregoing technical solutions, the present invention has the following beneficial effects:

1. In the radio frequency transmitting device provided by the present invention, all circuits can be integrated with a standard CMOS process single chip, and the system structure is simple, which meets the low-cost requirements of practical applications. The transmitter realizes high data rate communication with low power consumption, and solves the problem of related applications The low power consumption problem in.

2. The radio frequency transmitting device provided by the present invention adopts a twin voltage-controlled oscillator in the phase-locked loop, and the phase-locked loop can work in two different modes: receiving mode and transmitting mode. In the receiving mode, the twin voltage-controlled oscillators are in the quadrature coupling mode, which can provide a quadrature carrier for the receiver; in the transmitting mode, the twin voltage-controlled oscillators are decoupled and oscillate independently. In this way, the overall hardware overhead of the transceiver can be reduced, the area can be saved, and the cost can be reduced.

3. In the radio frequency transmitting device provided by the present invention, when in the transmitting mode, the twin voltage-controlled oscillators are decoupled and oscillate independently, wherein one voltage-controlled oscillator (iVCO) is locked by a phase-locked loop, and the other voltage-controlled oscillator (iVCO) is locked by a phase-locked loop. qVCO) is not locked, and the modulation signal is added to the qVCO, so that the transmission data rate gets rid of the limitation of the bandwidth of the phase-locked loop, and at the same time, the stability of the transmission carrier frequency can be maintained.

4. The radio frequency transmitting device provided by the present invention adopts frequency preset technology, which can not only greatly shorten the locking time of the phase-locked loop, but also reduce the influence of output load capacitance mismatch on the oscillation frequency of the voltage-controlled oscillator, and improve the frequency Accuracy.

5. In the radio frequency transceiver provided by the present invention, the variable gain power amplifier is composed of a power drive stage and a power amplification stage. Its power drive stage adopts a class AB circuit structure, and the power amplifier stage adopts a class B complementary push-pull structure, which reduces system power consumption while meeting the linearity requirements of the power amplifier. The input of the power driver stage adopts inductance matching to increase the gain of the transmitter, and when there is no radio frequency signal input, only the power driver stage consumes power, which reduces the transmission power consumption and improves the transmission efficiency.

6. The radio frequency transmitting device provided by the present invention is particularly suitable for use in the field of wireless communication requiring high-speed and low-power transmission applications.

Description of drawings

Fig. 1 is a kind of high-speed wireless radio frequency transmitting device provided by the present invention;

Fig. 2 is the circuit diagram of the frequency preset module 13 provided by the present invention;

Fig. 3 is the circuit diagram of twin voltage-controlled oscillator 14 that the present invention provides;

FIG. 4 is a circuit structure diagram of the power amplifier 16 provided by the present invention.

detailed description

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

Fig. 1 shows a system block diagram of a phase-locked loop-based high-speed wireless radio frequency transmitting device provided by the present invention, and the transmitting device is used for transmitting digital baseband signals modulated by frequency shift keying. As shown in Figure 1, the radio frequency transmitting device includes: a frequency and phase detector 10, a charge pump 11, a loop filter 12, a frequency preset module 13, a reconfigurable twin voltage-controlled oscillator 14, a buffer 15, Power amplifier 16 , redundancy module 17 , programmable frequency divider 18 , dual-mode frequency divider 19 , digital processor 20 and non-volatile memory 21 .

Wherein, the first input terminal of the frequency and phase detector 10 receives the externally input reference signal f _ref , the second input terminal receives the output signal f _div of the programmable frequency divider 18 , the first output terminal UP and the second output The terminal DN is connected to the input terminal of the charge pump 11 . The frequency and phase detector 10 is used to compare the frequency and phase of the input reference signal f _ref and the output signal f _div of the programmable frequency divider 18, when the frequency of the reference signal f _ref is greater than the programmable frequency divider 18 When the frequency of the output signal f _div of , the first output terminal UP of the frequency and phase detector 10 generates a positive pulse, and the signal output by the second output terminal DN is low level. When the frequency of the reference signal f _ref is less than the frequency of the output signal f _div of the programmable frequency divider 18, the second output DN of the frequency and phase detector 10 generates a positive pulse, while the signal output by the first output UP is low level. When the frequency of the reference signal f _ref is equal to the frequency of the output signal f _div of the programmable frequency divider 18 and the phase difference is 0, the signals output from the first output terminal UP and the second output terminal DN are both low level.

The input end of the charge pump 11 is connected with the first output end UP and the second output end DN of the frequency and phase detector 10, and the output end is connected with the input end of the loop filter 12; The control of the output signal of the device 10, when the first output terminal UP of the frequency detector 10 generates a positive pulse, the charge pump 11 performs a charging operation, and its output terminal generates a charging current. When the second output terminal DN of the frequency and phase detector 10 generates a positive pulse, the charge pump 11 performs a discharge operation, and its output terminal generates a discharge current. When both the first output terminal UP and the second output terminal DN of the frequency detector 10 are at low level, the charge pump 11 neither charges nor discharges, and its output current is zero.

The input end of the loop filter 12 is connected to the output end of the charge pump 11 , and the output end is connected to the input end of the frequency preset module 13 . The loop filter 12 is used to convert the charging and discharging current of the charge pump 11 into a control voltage Va for controlling the frequency preset module 13. When the charge pump 11 generates a charging current, the control voltage Va at the output end of the loop filter 12 increases . When the charge pump 11 generates a discharge current, the control voltage Va at the output terminal of the loop filter 12 decreases. When the output terminal of the charge pump 11 generates neither charging current nor discharging current, the control voltage Va at the output terminal of the loop filter 12 remains constant. Wherein, the change of the control voltage Va directly affects the change of the output frequency of the twin voltage-controlled oscillator 14, that is, in the phase-locked loop, when the Va increases, the control voltage Vc decreases, and Va When decreased, the Vc increases.

The input terminal of the frequency preset module 13 is connected to the output terminal Va of the loop filter 12 and the first output terminal C[5:0] of the digital processor 20, for receiving the analog control voltage Va output by the loop filter 12 and the first frequency preset control word C[5:0] output by the digital processor 20, its output terminal is connected to the input terminal of the reconfigurable twin voltage-controlled oscillator 14, and the control voltage Vc output by it controls the reconfigurable The frequency of the twin VCO 14 varies. The control voltage Vc at the output terminal of the frequency preset module 13 is jointly determined by the analog control terminal Va and the digital control terminal C[5:0], that is, the output frequency of the reconfigurable twin voltage-controlled oscillator 14 is determined by the analog control terminal Va and the digital control terminal C[5:0]. The first preset digital control word C[5:0] is jointly determined. When the transmitter is powered on and the Va voltage is kept constant, the values of the different first frequency preset control words C[5:0] are sampled to obtain the output frequency corresponding to the reconfigurable twin voltage-controlled oscillator 14 by This results in the corresponding relationship between C[5:0] and the output frequency of the reconfigurable twin voltage-controlled oscillator 14. When the phase-locked loop frequency needs to jump to the target frequency, the digital processor calculates the C corresponding to the target frequency. The value of [5:0] is directly added to the frequency preset module 13, so that the output frequency of the reconfigurable twin voltage-controlled oscillator 14 is set as the target frequency, thereby shortening the locking time of the phase-locked loop.

The input terminal Vc of the reconfigurable twin voltage-controlled oscillator 14 is connected to the output terminal of the frequency preset module 13, the second output terminal P[2:0] of the digital processor 20, the external voltage VB1 and the transmission port TX-DATA, The output is connected to the input of the buffer 15 . The input terminal Vc is used to control the variation of the capacitance value of the varactor in the reconfigurable twin voltage-controlled oscillator 14 , thereby controlling the variation of its oscillation frequency. The second frequency preset control word P[2:0] output by the second output terminal of the digital processor 20 is used to control the change of the capacitor array in the reconfigurable twin voltage-controlled oscillator 14, thereby changing the working condition of the oscillator. frequency. The external voltage VB1 is used to control the working mode of the reconfigurable twin voltage-controlled oscillator 14. When VB1 is at a low level, the reconfigurable twin voltage-controlled oscillator 14 works in the transmitting mode for transmitting digital modulation signals; when When VB1 is at a high level, the reconfigurable twin voltage-controlled oscillator 14 works in a receiving mode, which is equivalent to a quadrature oscillator and outputs a quadrature carrier. The input terminal TX-DATA is used to apply the digital modulation signal to the reconfigurable twin voltage-controlled oscillator 14 in transmit mode.

The buffer 15 comprises two buffers 150 and 151, the input of the first buffer 150 is connected with the output of the q oscillator in the reconfigurable twin voltage-controlled oscillator 14, its output is connected with the power amplifier 16, and the second buffer The input terminal of the device 151 is connected with the output of the i oscillator in the reconfigurable twin voltage-controlled oscillator 14, and its output is connected with the dual-mode frequency divider 19. The buffer 15 is used to isolate the reconfigurable twin VCO 14 from the power amplifier 16 and the dual-mode frequency divider 19 .

The input end of the power amplifier 16 is connected to the output end of the first buffer 150, and the output end is connected to the antenna; The oscillating signal of the q oscillator is transmitted through the antenna;

The redundant module 17 is connected in the middle of the second buffer 151 and the dual-mode frequency divider 19, and its input load capacitance is equal to the input load capacitance of the power amplifier 16, so that the load capacitance seen by the buffer 150 and the buffer 151 is consistent , so that the load capacitance seen by the i-oscillator and q-oscillator in the reconfigurable twin voltage-controlled oscillator 14 is consistent.

The input terminal of the dual-mode frequency divider 19 is connected to the output terminal of the second buffer 151, and is used to perform the oscillation signal of the first oscillator in the reconfigurable twin voltage-controlled oscillator 14 received from the second buffer 151. The initial frequency division, and output to the programmable frequency divider 18;

The input terminal of the programmable frequency divider 18 is connected with the output terminal of the dual-mode frequency divider 19, and is used to further divide the output signal of the dual-mode frequency divider 19, and the signal after the frequency division is output to the frequency and phase detector 10 and digital processor 20. The signal output to the frequency and phase detector 10 is used for frequency and phase comparison with the external reference signal f _ref to form a feedback loop. The signal output to the digital processor 20 is used for the operation clock of the digital processor.

The input end of the digital processor 20 is connected with the output end of the non-volatile memory 21, and receives the programming configuration data of external input, and its output end controls the frequency preset module 13, can reconfigure the twin voltage-controlled oscillator 14, can Program divider 18, non-volatile memory 21. The digital processor 20 samples and calculates the output frequency of the dual-mode frequency divider 19 when the chip is powered on, and obtains the oscillation frequency of the reconfigurable twin voltage-controlled oscillator 14 and the first preset digital control word C[5: 0] and the corresponding relationship between the second frequency preset control word P[2:0], and then the first frequency preset control word C[5:0] and the second frequency preset control word P[ 2:0] are stored in the non-volatile memory 21, and are used to preset the frequency of the frequency preset module 13 during frequency hopping, and can also be paired with C[5:0] and P[2:0 by external input. ] to configure. The frequency preset control word includes a first frequency preset control word for controlling the current source in the frequency preset module 13 and a second frequency preset for controlling the capacitor array in the reconfigurable twin voltage-controlled oscillator 14 Control word, the digital processor 20 also generates a digital signal to control the frequency division ratio of the programmable frequency divider 18; the frequency preset control word is output to the non-volatile memory 21 for storage;

The input and output of the non-volatile memory 21 are connected to the input and output of the digital processor 16; it is used to store the first frequency preset control signal C[5:0] calculated by the digital processor 20 and the second frequency preset control signal P[2:0].

Based on the system block diagram of a high-speed wireless radio frequency transmitter described in FIG. 1 , FIG. 2 shows a circuit diagram of the frequency preset module 13 provided by the present invention. As shown in Figure 2, the frequency preset module 13 is used to preset the frequency of the voltage-controlled oscillator when the phase-locked loop frequency hops, including a resistor R1 and a plurality of MOS transistors M0, M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, M12, M13, M14. The gate of M0 is connected to the preset frequency control voltage Va output by the loop filter 12, the source of M0 is connected to the power supply voltage VDD, the drain of M0 is connected to the gate of M14 and one end of the resistor R1, and the MOS tubes M1, M2, M3 The gates and sources of M4, M5, and M6 are respectively connected to the bias voltage Vb and the power supply voltage VDD, and their drains are respectively connected to the sources of the MOS transistors M7, M8, M9, M10, M11, and M12, and the MOS transistor M7 , M8, M9, M10, M11, and M12 are respectively connected to digital control signals C<0>, C<1>, C<2>, C<3>, C<4>, C<5>, and the The drain is connected to the drain of M0, the gate of M14 and one end of the resistor R1, the drain of M14 is connected to the ground, the source is connected to the drain of M13, the gate and source of M13 are respectively connected to the bias voltage Vb and the power supply voltage VDD connection. MOS tubes M1, M2, M3, M4, M5, M6 form a group of digital control current sources, MOS tubes M7, M8, M9, M10, M11, M12 are switches for controlling whether the current source flows to the resistor R, MOS tubes M1, M2 , M3, M4, M5, and M6 increase in the exponential order of 2, so the current size of this group of digitally controlled current sources increases in the exponential order of 2. The output current of the digital control current source will be converted into a voltage through the resistor R1, and the transistors M13 and M14 form a source follower, which is used to buffer the voltage on the resistor R to Vc, and Vc is used to control the reconfigurable twin voltage-controlled Oscillating frequency of the oscillator 14. When the chip is powered on, the digital processor 20 controls the switch LS<0> to close, LS<1> to open, the frequency preset module 13 controls the voltage Va to be connected to the bias voltage VDD/2, and the digital processor 20 pairs the twin The output frequency of the oscillator 14 is sampled, so that when the control voltage Va is half the power supply voltage (VDD/2), different voltage-controlled oscillator oscillation frequencies and frequency preset module 13 control word C[5:0] and the corresponding relationship between the reconfigurable twin voltage-controlled oscillator 14 control words. It is used to preset the oscillator frequency at a frequency close to the target frequency by directly presetting C[5:0] and P[2:0] during frequency hopping. The corresponding C[5:0] and P[2:0] obtained by sampling at different frequencies are stored in the non-volatile memory 21, and then the digital processor 20 controls the switch LS<0> to open and LS<0> to close , the PLL enters closed-loop mode. , when the phase-locked loop needs to jump from the current oscillation frequency to the target frequency, the digital processor module 20 calculates the values of the control words C[5:0] and P[2:0] corresponding to the target frequency through a linear interpolation algorithm , and then output C[5:0] to the frequency preset module 13, and output P[2:0] to the reconfigurable twin voltage-controlled oscillator 14, so that the frequency of the reconfigurable twin voltage-controlled oscillator 14 Preset to a value close to the target frequency, and then the loop control voltage completes fine locking. This can greatly shorten the locking time of the phase-locked loop.

Based on the system block diagram of a high-speed wireless radio frequency transmitting device described in FIG. 1 , FIG. 3 shows a circuit diagram of the twin voltage-controlled oscillator 14 provided by the present invention. As shown in FIG. 3 , the twin voltage-controlled oscillator 14 specifically includes: two independent and identical voltage-controlled oscillators i-oscillator 410 and q-oscillator 411, and two coupling branches i-coupling branch 412 and q coupling branch 413 . The twin voltage-controlled oscillator 14 has two working modes: receiving mode and transmitting mode. In the receiving mode, the i oscillator 410 and the q oscillator 411 are in a coupled state. At this time, the twin voltage-controlled oscillator can be reconfigured 14 is equivalent to a quadrature oscillator, which can be used to generate the quadrature carrier required by the receiver. In the transmitting mode, the i oscillator 410 and the q oscillator 411 are decoupled and oscillate independently, the i oscillator phase-locked loop is locked, and the q oscillator is not locked, and the digital modulation signal to be sent is added to the q oscillator, using In order to generate a frequency modulation signal, the transmission data rate is free from the limitation of the bandwidth of the phase-locked loop. The oscillation frequency of the i oscillator is locked by the phase-locked loop to keep it stable. Since the control voltage Vc of the i oscillator and the q oscillator is the same, the q The oscillation frequency of the oscillator will be consistent with the oscillation frequency of the i oscillator, so the transmission carrier frequency can be kept stable while transmitting data.

Specifically, the bias voltage VB3, the control word P[2:0] and the control voltage Vc are connected to the input of the i oscillator and the q oscillator, and the output ports I+ and I- of the i oscillator 410 are connected to the i coupling branch 412 and The q coupling branch 413 is connected, and the output ports Q+ and Q− of the q oscillator 411 are connected to the q coupling branch 413 and the i coupling branch 412 . The i-coupling branch 412 is composed of a resistor R11, a capacitor C11, and MOS transistors M11, M12, M13, M14, M15, and M16. M11 source and M12 source are connected to power supply voltage VDD, M11 gate and M12 gate are connected to bias voltage VB1, M11 drain and M12 drain are respectively connected to M13 source and M14 source, resistor R11 and capacitor C11 In parallel, one end is connected to the drain of M11, one end is connected to the drain of M12, the gate of M13 and the gate of M14 are respectively connected to the output terminal Q- and output terminal Q+ of the q oscillator 411, and the drain of M13 and the drain of M14 are respectively connected to the source of M15 The pole is connected to the source of M16, the gate of M15 and the gate of M16 are connected to the bias voltage VB2, the drain of M15 and the drain of M16 are respectively connected to the output terminal I+ and the output terminal I- of the i oscillator 410. The q-coupling branch 413 is composed of a resistor R21, a capacitor C21, and MOS transistors M21, M22, M23, M24, M25, and M26. M21 source and M22 source are connected to power supply voltage VDD, M21 gate and M22 gate are connected to bias voltage VB1, M21 drain and M22 drain are respectively connected to M23 source and M24 source, resistor R21 and capacitor C21 In parallel, one end is connected to the drain of M21, one end is connected to the drain of M22, the gate of M23 and the gate of M24 are respectively connected to the output terminal I+ and output terminal I- of the i oscillator 410, and the drain of M23 and M24 are respectively connected to the source of M25 The pole is connected to the source of M26, the gate of M25 and the gate of M26 are connected to the bias voltage VB2, the drain of M25 and the drain of M26 are respectively connected to the output terminal Q+ and output terminal Q- of the q oscillator 411. The i oscillator and the q oscillator are two cross-coupled negative-resistance LC voltage-controlled oscillators with the same structure, and they are controlled by the same control voltage Vc. The LC voltage-controlled oscillator adopts cross-coupling negative resistance technology, and a 3-bit digitally controlled capacitor array is used to expand the tuning range of the voltage-controlled oscillator. The reconfigurable twin VCO 14 has two working modes: receiving mode and transmitting mode. The switching between these two working modes is realized by switching the bias voltage VB1.

When the reconfigurable twin voltage-controlled oscillator 14 is in the receiving mode, the bias voltage VB1 is connected to a fixed bias voltage, and the coupling branch current sources (M11, M12, M21, M22) are turned on, at this time the i oscillator and the q oscillator The oscillators are coupled to each other by the coupling branch, which can be equivalent to a quadrature oscillator, so the output signal frequency of the i oscillator is the same as that of the q oscillator, but the phase is quadrature. Parallel resistors and capacitors (R11-C11 and R22-C22) on the coupling path are used to avoid dual-mode oscillation effects in the quadrature voltage-controlled oscillator.

When the reconfigurable twin voltage-controlled oscillator 14 is in the transmitting mode, the bias voltage VB1 is connected to the power supply voltage, and the coupling branch current sources (M11, M12, M21, M22) are turned off. At this time, the i oscillator and the q oscillator are not It is equivalent to a quadrature oscillator, that is, the i oscillator and the q oscillator are decoupled, the i oscillator and the q oscillator are in an independent oscillation state, and the output I+ and I- of the i oscillator are connected to the phase lock through the buffer 15 In the ring, the output Q+ and Q- of the q oscillator are connected to the power amplifier 16 after passing through the buffer 15. Since the i oscillator and the q oscillator are controlled by the same oscillation frequency control voltage Vc, the oscillation frequency of the q oscillator will follow The oscillation frequency of the i oscillator is to add the transmitted baseband data to the VB3 port of the q oscillator, so that the transmitted data rate will get rid of the limitation of the bandwidth of the phase-locked loop, and the transmitted carrier frequency will remain stable. There are mainly four implementation methods of the existing phase-locked loop-based transmitters: closed-loop frequency divider modulation transmission, closed-loop voltage-controlled oscillator modulation transmission, two-point modulation transmission and open-loop voltage-controlled oscillator modulation transmission.

The transmission data rate of the closed-loop frequency divider modulation transmission structure is limited by the loop bandwidth of the phase-locked loop, so it is difficult to achieve a relatively high transmission data rate. The disadvantage of the closed-loop voltage-controlled oscillator modulation transmission structure is that the low-frequency components of the transmitted data will be lost and distorted. The two-point modulation structure combines the advantages of closed-loop frequency divider modulation transmission and closed-loop voltage-controlled oscillator modulation transmission, while avoiding their respective shortcomings, but the mismatch of gain and phase will affect the quality of the transmitted signal, the design is complex and consumes power consumption larger. The transmission carrier of the open-loop voltage-controlled oscillator modulation transmission structure is easily affected by leakage current and external noise interference. In addition, this structure is not suitable for continuous modulation transmission, so the amount of transmitted data is limited.

The phase-locked loop transmitter proposed by the present invention adopts a structure based on twin voltage-controlled oscillators, and the transmission carrier can be kept stable during transmission, which avoids the frequency drift problem existing in the modulation and transmission of open-loop voltage-controlled oscillators, and at the same time can achieve relatively high The data transmission rate is high, which avoids the problem that the transmission rate of the closed-loop frequency divider modulation transmission is limited by the loop bandwidth of the phase-locked loop.

Based on the system block diagram of a high-speed wireless radio frequency transmitting device described in FIG. 1 , FIG. 4 shows a circuit diagram of the power amplifier 16 provided by the present invention. As shown in FIG. 4 , the power amplifier 16 is composed of a driver stage circuit 610 and an output stage circuit 611 , which are used to transmit the radio frequency modulation signal generated by the q oscillator. The driving stage 610 is composed of capacitors Cin, Cp, inductor L1, resistor R1, and MOS tubes M1, M2, M3, M4. One end of the capacitor Cin is connected to the radio frequency signal RFin, one end is connected to the gate of the MOS transistor M1, one end of the resistor R1 is connected to the bias voltage VB, the other end is connected to the gate of M1, one end of the capacitor Cp is connected to the gate of M1, and the other end is connected to the drain of the MOS transistor M4 The source of the MOS transistor M1 is connected to the ground, the drain is connected to the source of the MOS transistor M2, the drain of the MOS transistor M2 is connected to the drain of the inductor L1 and the drain of the MOS transistor M3, the gate of M2 is connected to the power supply VDD, and one end of the inductor L1 It is connected to the power supply VDD, one end is connected to the drain of M2, the drain of M3 is connected to the drain of M2, the gate of M3 is connected to the switching signal SW1, the drain of M4 is connected to one end of the capacitor Cp, the source of M4 is connected to the drain of M2, and the The gate is connected to the switching signal SW0. The output stage 611 is composed of capacitors C1, C2 and C3, resistors R2 and R3, and MOS transistors M5 and M6. One end of capacitor C1 is connected to C2, one end is connected to M5 gate, the other end of capacitor C2 is connected to M6 gate, and one end of resistor R2 Connect to the bias voltage VBP, one end to the gate of M5, one end of the resistor R3 to the bias voltage VBN, one end to the gate of M6, the source of M6 to ground, the drain of M6 to the drain of M5, the source of M5 It is connected to the power supply voltage VDD, one end of the capacitor C3 is connected to the drains of M5 and M6, and the other end is connected to the output terminal RFout.

The driving stage circuit 610 of the power amplifier 16 is used to amplify the radio frequency signal initially to provide a high voltage signal swing, and the output stage circuit 611 is used to drive an off-chip 50Ω antenna load. Switches SW0 and SW1 are used to realize three-level gain control (high gain, medium gain and low gain), which can provide a gain control range of 20dB. When SW0 and SW1 are high, the power amplifier 16 is in high gain mode; when SW0 is high and SW1 is low, power amplifier 16 is in medium gain mode; when SW0 is low and SW1 is high , the power amplifier 16 is in a low gain mode. The MOS transistors M5 and M6 of the output stage 611 work at the sub-threshold point by setting the bias voltages VBP and VBN to reduce the static current consumption and improve the efficiency of the power amplifier.

The specific embodiments described above have further described the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above descriptions are only specific embodiments of the present invention, and are not intended to limit the present invention. Within the spirit and principles of the present invention, any modifications, equivalent replacements, improvements, etc., shall be included in the protection scope of the present invention.

Claims (9)

1. A wireless radio frequency transmitting device, which comprises: a frequency and phase detector, a charge pump, a loop filter and twin voltage-controlled oscillators; Wherein, the twin voltage-controlled oscillator includes a first voltage-controlled oscillator and a second voltage-controlled oscillator with the same structure and a first coupling branch and a second coupling branch, and the output of the first voltage-controlled oscillator The terminals are respectively connected to the input terminals of the first coupling branch and the second coupling branch, and the output terminals of the second voltage-controlled oscillator are respectively connected to the input terminals of the first coupling branch and the second coupling branch. connected, wherein, when the twin VCOs are in receive mode, the first VCO and the second VCO are coupled to each other to form a quadrature VCO, the quadrature VCO The oscillator forms a phase-locked loop with the frequency and phase detector, the charge pump, and the loop filter to generate a quadrature carrier wave for receiving information; when the twin voltage-controlled oscillator is in the transmitting mode, the first A voltage-controlled oscillator and a second voltage-controlled oscillator are decoupled and oscillate independently, and the first voltage-controlled oscillator forms a phase-locked loop with the frequency and phase detector, charge pump, and loop filter, and the The second voltage-controlled oscillator is used for frequency modulation of the transmitted data, and the oscillation frequency of the second voltage-controlled oscillator is the same as that of the first voltage-controlled oscillator, and both remain stable. 2. The device according to claim 1, wherein, after the first coupling branch and the second coupling branch apply current, the first voltage-controlled oscillator and the second voltage-controlled oscillator pass through the first A coupling branch and a second coupling branch are coupled to form a quadrature voltage-controlled oscillator, and the twin voltage-controlled oscillator is switched to a receiving mode; After the currents of the first coupling branch and the second coupling branch are disconnected, the first voltage-controlled oscillator and the second voltage-controlled oscillator are decoupled, and the twin voltage-controlled oscillators are switched to a transmission mode. 3. The apparatus of claim 1, wherein the oscillation frequencies of the first voltage controlled oscillator and the second voltage controlled oscillator are controlled by a first frequency control signal. 4. The apparatus of claim 3, wherein the phase frequency detector, charge pump and loop filter adjust the first frequency control based on a feedback value of the output frequency of the twin VCOs Signal. 5. The apparatus of claim 3, further comprising: A frequency preset module is used for the phase-locked loop to preset the frequency of the twin voltage-controlled oscillator during frequency hopping. 6. The apparatus according to claim 5, wherein the frequency preset module changes the first frequency control signal according to a first frequency preset control word. 7. The device according to claim 3, wherein the oscillation frequencies of the first voltage-controlled oscillator and the second voltage-controlled oscillator are further controlled by a second frequency preset control word. 8. The device according to claim 7, wherein the first frequency preset control word and the second frequency preset control word are preset according to the target frequency to which the twin voltage-controlled oscillators will jump. set. 9. The apparatus according to claim 8, further comprising: a digital processor, which samples the output frequency of the twin voltage-controlled oscillator when powered on, to obtain the frequency of the twin voltage-controlled oscillator The corresponding relationship between the output frequency and the first frequency preset control word and the second frequency preset control word.