CN221597875U - Frequency locking loop circuit with strong robustness - Google Patents
Frequency locking loop circuit with strong robustness Download PDFInfo
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- CN221597875U CN221597875U CN202322903704.7U CN202322903704U CN221597875U CN 221597875 U CN221597875 U CN 221597875U CN 202322903704 U CN202322903704 U CN 202322903704U CN 221597875 U CN221597875 U CN 221597875U
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Abstract
The utility model relates to the technical field of clock circuits, in particular to a frequency locking loop circuit with strong robustness, which comprises: the reference voltage generating circuit is used for generating a reference voltage Vref through an externally input reference current IR and a resistor R and is used as an input source at one end of the error amplifier; a voltage controlled oscillator for generating an output frequency signal fin as a frequency input to the error amplifier. The scheme is used for generating the clock, and the circuit integrates digital-analog hybrid modulation, has the advantages of low power consumption, high precision, strong stability, low temperature drift and small area overhead, and has strong robustness and cost advantages.
Description
Technical Field
The utility model relates to the technical field of clock circuits, in particular to a frequency locking loop circuit with strong robustness.
Background
RC oscillators (oscillators) are widely used in many electronic fields and applications, in analog and digital circuits, oscillators are commonly used in clocks and timers, wireless communications, audio applications, sensor and measurement systems, control systems. By synthesizing the frequency sources, a stable clock signal is provided for synchronizing various digital circuitry, signal conditioning, audio synthesis, timing generation, and pulse counting. RC oscillators are widely used as a simple and low-cost oscillator in the fields of electronic device manufacturing, wireless communication, automobile industry, industrial automation, medical equipment, consumer electronics industry, and the like. It should be mentioned that although RC oscillators are widely used in the above-mentioned fields, they are limited in some applications requiring higher stability and higher accuracy.
A conventional RC oscillator is a circuit that generates an oscillating signal using a negative feedback network of capacitors and resistors. It can generate a frequency signal which can be modulated, and the RC oscillator circuit has the advantages of simplicity, economy, self-excitation and relative stability. However, since the conventional RC uses a capacitor and a resistor, its accuracy is limited by the element characteristics themselves and manufacturing errors. Furthermore, the stability of the frequency under temperature changes is greatly affected by the temperature characteristics of the capacitance and the resistance.
Disclosure of Invention
The utility model aims to solve the technical problem that the RC oscillator is limited in application in high-precision electronic devices.
The utility model provides a frequency locking loop circuit with strong robustness for solving the technical problems, which comprises the following components:
The reference voltage generating circuit is used for generating a reference voltage Vref through an externally input reference current IR and a resistor R and is used as an input source at one end of the error amplifier;
A voltage controlled oscillator for generating an output frequency signal fin as a frequency input to the error amplifier.
Preferably, the frequency locked loop circuit further includes a frequency-to-voltage conversion circuit, and the output frequency generating voltage Vfvc is sampled by using a frequency-to-voltage structure formed by the current source Iref and the switch capacitor, and is error amplified with the reference voltage Vref by an error amplifier, so as to generate Vctrl as a control voltage of the voltage-controlled oscillator.
Preferably, the frequency input source of the frequency-voltage conversion circuit is from an output frequency signal fin sent by the voltage-controlled oscillator, the output frequency signal fin generates an F Φ+ frequency signal and an F Φ- frequency signal through a two-phase non-overlapping clock circuit, and the frequency signal fin and the F Φ- frequency signal are respectively connected to two ends of the MOS tube Gated, so that alternating charging and discharging of the capacitor are realized, and full charging and discharging are ensured.
Preferably, the frequency locked loop circuit further comprises a frequency-to-voltage converter for adjusting the linear range of the frequency-to-voltage reference such that the resulting voltage generation range is within the common-mode input range of the error amplifier.
Preferably, the frequency locking loop circuit further comprises a two-phase non-overlapping clock generation module for generating two mutually non-overlapping clock circuits to adjust the stability between the switching of the switch capacitor logic of the frequency-to-voltage converter.
Preferably, the voltage controlled oscillator is a CMOS based ring oscillator.
Preferably, the voltage-controlled oscillator is formed by seven stages of cmos inverters, the output of the seventh stage being connected to the input of the first stage, forming a loop, and the gate voltage of the voltage-controlled oscillator being controlled by the input voltage Vctrl.
The beneficial effects are that:
According to the scheme, the reference voltage and the frequency-voltage conversion result are locked together, the negative feedback control mechanism is utilized, the output oscillation frequency is adjusted after the input control voltage of the voltage-controlled oscillator is continuously adjusted through the error amplifier, and the output frequency participates in the frequency-voltage conversion circuit to form closed-loop control.
The reference signal is generated by multiplying the reference current by the resistor. Based on the frequency-to-voltage architecture, the output clock frequency is sampled such that it generates an appropriate reference voltage signal. The signal generated by the conversion of the reference signal and the frequency voltage is subjected to closed-loop control through an error amplifier, the output control voltage is used for adjusting the voltage-controlled oscillator, and the clock frequency is locked on a working point close to the reference signal by utilizing the characteristic of high gain of the error amplifier.
The problems of low precision and frequency stability of the traditional RC oscillator are improved by utilizing the closed-loop negative feedback modulation characteristic.
The foregoing description is only an overview of the present utility model, and is intended to provide a better understanding of the present utility model, as it is embodied in the following description, with reference to the preferred embodiments of the present utility model and the accompanying drawings. Specific embodiments of the present utility model are given in detail by the following examples and the accompanying drawings.
Drawings
The accompanying drawings, which are included to provide a further understanding of the utility model and are incorporated in and constitute a part of this specification, illustrate embodiments of the utility model and together with the description serve to explain the utility model and do not constitute a limitation on the utility model. In the drawings:
FIG. 1 is a circuit diagram of a strong-robustness frequency-locked loop provided by the present utility model;
FIG. 2 is a schematic diagram of a frequency-to-voltage conversion circuit according to the present utility model;
FIG. 3 is a timing diagram of the switching capacitor operation of the frequency-to-voltage conversion circuit according to the present utility model;
FIG. 4 is a block diagram of a portion of an error amplifier circuit provided by the present utility model;
FIG. 5 is a schematic diagram of a voltage controlled oscillator according to the present utility model;
FIG. 6 is a block diagram of a two-phase non-overlapping clock circuit provided by the present utility model;
fig. 7 is a schematic diagram of three stages of the operation of the frequency locking ring provided by the present utility model.
Detailed Description
The principles and features of the present utility model are described below with reference to the drawings, the examples are illustrated for the purpose of illustrating the utility model and are not to be construed as limiting the scope of the utility model. The utility model is more particularly described by way of example in the following paragraphs with reference to the drawings. Advantages and features of the utility model will become more apparent from the following description and from the claims. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the utility model.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this utility model belongs. The terminology used herein in the description of the utility model is for the purpose of describing particular embodiments only and is not intended to be limiting of the utility model. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.
As shown in fig. 1, the present utility model provides a robust frequency locked loop circuit divided into five parts according to functions:
The first part is a reference voltage generating circuit, which generates a reference voltage Vref through a reference current IR and a resistor R which are externally input, and is used as an input source of one end of an Error Amplifier (Error Amplifier).
The second part is a frequency-voltage conversion circuit, a frequency-voltage conversion structure is formed by using a current source Iref and a switch capacitor, the output frequency is sampled to generate a voltage Vfvc, and error amplification is carried out on the voltage Vfvc and a reference voltage Vref through an error amplifier, so that Vctrl is generated as a control voltage of a voltage-controlled oscillator.
The third part is an error amplifier, providing high DC gain for the system loop.
The fourth part is a Voltage Controlled Oscillator (VCO), based on a CMOS ring oscillator, does not require the use of inductive elements and can have a large amplitude and tuning range, making it easier for the output range of the error amplifier to meet the target frequency output. For generating an output frequency signal fin as a frequency input to the error amplifier.
The fifth part is a two-phase non-overlapping clock circuit, which consists of a plurality of logic gates, and generates a non-overlapping clock signal through reasonable combination and delay, so as to control the switch capacitor, ensure that only one switch is in a conducting state at the same moment, realize the charge and discharge process of the capacitor, avoid the problem of switch short circuit and realize stable frequency-voltage conversion.
The frequency locking circuit provided by the scheme is used for generating a clock, and under the advantage of integrating the RC oscillator, extra power consumption area expenditure is not needed, and higher precision and strong stability are realized.
In a further scheme, as shown in fig. 2, the frequency-voltage conversion circuit is provided, the frequency input source is an output frequency signal fin sent by the VCO, the output frequency signal fin generates an F Φ+、FΦ- frequency signal through a two-phase non-overlapping clock circuit, and the capacitor is alternately controlled to charge and discharge under the control of the switches S1 and S2, so that the capacitor is ensured to be fully charged and discharged.
As shown in fig. 3, in the working timing diagram of the frequency-voltage conversion circuit, fin is an input signal sent by the VCO output frequency through the two-phase non-overlapping clock circuit, and F Φ+、FΦ- is a two-phase non-overlapping clock for controlling the switch S1 and the switch S2. When F Φ+ is high level
When F Φ- is low, ic charges Cin+ and Csw in parallel; when F Φ+ is low and F Φ- is high, csw discharges and Ic charges Cin+ with constant current. The basic principle according to the theory of the switch capacitance can be obtained: reff=1/(fin×csw), and under stable conditions, the frequency-to-voltage conversion circuit has, at low frequencies: iref= Vfvc =vsw=ir×r=vr, vsw and VR together forming the positive and negative inputs of the group difference amplifier. The equivalent resistor Reff and cin+ are connected in parallel to form a time constant τ=reff+cin, and a pole Pfvc =1/reff+cin+ is generated, so that parameters of Reff and cin+ need to be concerned to ensure that Pfvc is far away from the main pole;
As shown in fig. 4, in the error amplifier circuit of the present solution, in the robust frequency locked loop, i.e. FLL system, there are two points in the requirement for the error amplifier, namely, high gain, providing high dc gain for the frequency locked loop, and not introducing a pole affecting the loop stability as much as possible. While the loop main pole of the FLL is usually defined by the main pole of the error amplifier, the internal secondary point needs to be placed far from the output pole of the frequency-to-voltage converter to ensure that the single-pole approximation condition of the error amplifier is approximated.
The error amplifier circuit of the scheme selects a single-stage folding type common-source common-gate amplifier structure, the error amplifier is composed of a differential input stage and an output stage, and externally fed bias circuits Ibp1, ibp2 and Ibn1 provide tail current and bias current of the input and output stages for the circuit, so that the circuit can have correct working points under various temperature, voltage and process deviation. The input stage adopts differential input to better inhibit common mode noise and widen the dynamic range of input voltage, and the output stage adopts a common source and common gate current mirror as an active load, so that the error amplifier has high output impedance, and finally, a Vctrl signal is sent out through differential-to-single-ended diode connection. In addition, the capacitor Cf of the output stage is used as a load capacitor, and jitter of Vctrl is filtered under the condition that the main pole of the loop is not affected, so that jitter of the VCO frequency and ripple voltage of Vsw are reduced. The error amplifier has wide dynamic input range, high gain, high output impedance and characteristics meeting the precision requirement of the frequency locking ring. In addition, the main pole point of the error amplifier determines the main pole point of the loop, and the limitation of the whole loop of the frequency locking loop on the monopole point condition is met.
Referring to fig. 5, the input signal is Vctrl and the output signal is Fvco, which is the voltage-controlled oscillator VCO of the frequency generation circuit of the present embodiment. The VCO adopts a rail-to-rail working mode, has wide frequency range and extremely low power consumption, and meets the application of low power consumption. The output frequency of the VCO is highly sensitive to the input voltage Vctrl. This high sensitivity relaxes the required output operating range of the error amplifier.
The VCO is formed by seven stages of cmos inverters, with the output of the seventh stage being connected to the input of the first stage, forming a loop, and the gate voltage of the VCO being controlled by Vctrl. An NMOS transistor is used as a VCO gate voltage control end, the NMOS transistor works in a subthreshold region with drain current Id and Vgs being in an exponential relationship, and Vctrl and Fvco are in an exponential relationship. Since Fvco is used to control the charge and discharge of Csw after passing through two non-overlapping clocks and is also controlled by 1/rref×csw to form a closed loop feedback, the VCO is not required to have high voltage-to-frequency linearity.
As shown in fig. 6, in the two-phase non-overlapping clock circuit of the present embodiment, fvco is derived from the clock output by the VCO, and the input clock is acted by a series of inverters and nand gates, so as to finally generate a pair of two-phase non-overlapping clocks F Φ+、FΦ-, where the non-overlapping time of the pair of signals is determined by the delays of the inverters and the nand gates. With reference to fig. 2, 3 and 6, signals F Φ+ and F Φ- are control signals generated after two-phase non-overlapping clocks, and high-level non-overlapping signals are designed to ensure that the switch capacitors Cin and Csw are not turned on simultaneously, so as to control charge and discharge of the FVC circuit capacitors.
In combination with fig. 1 and 7, the overall circuit of the frequency locking ring comprises the following working steps: after the power supply voltage is established, the IR and IC generated by the reference current module can be established quickly, and stable bias is realized. In the initialization phase, the error amplifier compares VR and Vsw and amplifies the error, generating Vctrl and controlling VCO start-up. After the VCO oscillates, the output frequency adjusts the Vsw generated by the switched capacitor to generate loop feedback. As shown in FIG. 7, the working state can be divided into three stages, in the first stage, vsw is lower than VR, vcrtl generated by the error amplifier is smaller, F Φ+ and F Φ- signals are generated after the output clock of the VCO is subjected to two-phase non-overlapping clock, F Φ+ and F Φ- signals are fed back to the switch capacitors cin+ and Csw for charging, at the moment, the output frequency of the VCO is lower, the charging time of the switch capacitors is longer, ic continuously charges the capacitors Csw and cin+, the charging charge is more than the discharging point charge, vsw is increased, vctrl is increased, and the clock frequency generated by the VCO is controlled to be continuously increased. In the second stage, when Vsw is continuously increased and then is greater than VR, vctrl generated by the error amplifier is greater, and the output frequency of the switch capacitor is higher, so that the charging time of the switch capacitor is shorter, and at this time, the charging charges of Csw and cin+ are less than the discharging charges, so that Vsw is continuously reduced, vctrl is gradually reduced, and the frequency of the VCO is controlled to be reduced. In the third phase, when Vsw is close to or equal to VR, vsw and VR are kept constant by Vctrl generated by the error amplifier and the VCO output frequency is kept constant. The three stages of the whole work embody the negative feedback characteristic of the loop, and realize the high-precision frequency adjustment of the target frequency, the self-calibration of the clock frequency and the locking function through high loop gain.
The above description is only of the preferred embodiments of the present utility model, and is not intended to limit the present utility model in any way; those skilled in the art will readily appreciate that the present utility model may be implemented as shown in the drawings and described above; however, those skilled in the art will appreciate that many modifications, adaptations, and variations of the present utility model are possible in light of the above teachings without departing from the scope of the utility model; meanwhile, any equivalent changes, modifications and evolution of the above embodiments according to the essential technology of the present utility model still fall within the scope of the present utility model.
Claims (7)
1. A robust frequency locked loop circuit, comprising:
The reference voltage generating circuit is used for generating a reference voltage Vref through an externally input reference current IR and a resistor R and is used as an input source at one end of the error amplifier;
A voltage controlled oscillator for generating an output frequency signal fin as a frequency input to the error amplifier.
2. The robust frequency locked loop circuit of claim 1, further comprising a frequency-to-voltage conversion circuit configured to sample the output frequency to generate a voltage Vfvc by using a current source Iref and a switched capacitor, and to perform error amplification with a reference voltage Vref by an error amplifier to generate Vctrl as a control voltage of the voltage-controlled oscillator.
3. The robust frequency locking loop circuit of claim 1, wherein the frequency input source of the frequency-to-voltage conversion circuit is derived from an output frequency signal fin sent by a voltage-controlled oscillator, the output frequency signal fin generates an F φ+ frequency signal and an F Φ- frequency signal through a two-phase non-overlapping clock circuit, and the signals are respectively connected to Gate ends of two MOS transistors to realize alternate charge and discharge control so as to ensure full charge and discharge of a capacitor.
4. The robust frequency locked loop circuit of claim 1, further comprising a frequency to voltage converter for adjusting a linear range of the frequency to voltage reference such that a resulting voltage generation range is within a common mode input range of the error amplifier.
5. The robust frequency locked loop circuit of claim 1, further comprising a two-phase non-overlapping clock generation module for generating two mutually non-overlapping clock circuits for adjusting stability between switched capacitor logic switching of the frequency to voltage converter.
6. The robust frequency locked loop circuit of claim 1, wherein said voltage controlled oscillator is a CMOS based ring oscillator.
7. The robust frequency locked loop circuit of claim 1, wherein the voltage controlled oscillator is comprised of seven stages of COMS inverters, the output of the seventh stage being coupled to the input of the first stage to form a loop, and the gate voltage of the voltage controlled oscillator being controlled by the input voltage Vctrl.
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CN202322903704.7U CN221597875U (en) | 2023-10-30 | 2023-10-30 | Frequency locking loop circuit with strong robustness |
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CN202322903704.7U CN221597875U (en) | 2023-10-30 | 2023-10-30 | Frequency locking loop circuit with strong robustness |
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