CN104124946B - semi-dynamic trigger - Google Patents

Abstract

The present invention provides a semi-dynamic trigger. A selection circuit selects an input signal from a data signal and a test signal. A charge-discharge circuit charges/discharges an intermediate node according to an input signal, a clock signal and an adjustment signal. A first storage circuit stores the potential of the intermediate node. An adjustment circuit generates an adjustment signal according to the clock signal and the potential of the intermediate node. An output circuit adjusts the potential of an output node according to the clock signal and the potential of the intermediate node. A second storage circuit stores the potential of the output node. A reset circuit is used to reset or set the potential of the output node. A switch is connected between the adjustment circuit and the charge-discharge circuit and is turned on in a normal operation mode.

Description

semi-dynamic trigger

technical field

The invention relates to a logic circuit, in particular to an improved technology of a semi-dynamic flip-flop.

Background technique

A semi-dynamic flip-flop (semi-dynamic flip-flop) is a component commonly used in digital logic circuits, the front-end circuit of which is dynamic, and the back-end circuit is static. FIG. 1 shows a typical semi-dynamic flip-flop circuit implemented in complementary metal oxide semiconductor (CMOS). The flip-flop 100 mainly includes a discharge circuit 111 , a pre-charge circuit 112 , an adjustment circuit 113 , a first storage circuit 114 , an output circuit 115 and a second storage circuit 116 . The function of the flip-flop 100 is to sample the input signal D according to the clock signal CK, and the sampling results are signals Q and QB. The operation of the flip-flop 100 is briefly described below.

When the falling edge of the clock signal CK occurs, the flip-flop 100 enters the pre-charging phase. Through the transistor P1 in the pre-charging circuit 112 , the power supply terminal VDD charges the node X, so that its voltage is pulled up to a high potential. The first storage circuit 114 stores the high potential of the node X. The transistors P2 and N5 in the output circuit 115 are turned off, which is equivalent to cutting off the connection between the intermediate node X and the output node Q, so that the second storage circuit 116 continues to store the previous state of the sampling result QB. After the clock signal CK turns to a low potential, the delayed clock signal CKD in the adjustment circuit 113 will also have a low potential, so that the output node Y of the adjustment circuit 113 must have a high potential, and then the discharge circuit 111 will have a high potential. Transistor N3 is turned on. However, since the transistor N1 is turned off by the clock signal CK, no matter what the input signal D is, it will not affect the potential of the node X.

When the rising edge of the clock signal CK occurs, the flip-flop 100 enters the evaluation phase (ie, the sampling phase of the input signal D). At this time, if the input signal D has a low potential, the potential of the node X will still not be affected and remain at a high potential. If the previous node Q has a low potential, the conduction of the transistor N5 will not affect the sampling result QB. Conversely, if the node Q has a high potential before, the turn-on of the transistor N5 will pull down the voltage of the node Q to a low potential, and then change the sampling result QB to have a high potential. After the rising edge of the clock signal CK occurs, after the delay time contributed by the three logic gates in the adjustment circuit 113 , the node Y will change to a low potential, so that the transistor N3 is turned off. Turning off the transistor N3 can prevent the discharge circuit 111 from discharging the node X when the input signal D subsequently changes from a low potential to a high potential. This design enables the flip-flop 100 to have edge-triggered characteristics.

When the flip-flop 100 enters the evaluation stage, if the input signal D has a high potential, the discharge circuit 111 will discharge the node X to a low potential. The first storage circuit 114 then stores the low potential of the node X. The lowered node X will turn on the transistor P2 in the output circuit 115 , so that the node Y will have a high potential, and then the sampling result QB will have a low potential.

Contents of the invention

The present invention proposes a new semi-dynamic flip-flop architecture, adding a reset function and a test function. By properly configuring the logic elements in the circuit, the half-dynamic flip-flop according to the present invention will not reduce the maximum operating speed of the half-dynamic flip-flop due to the addition of new functions.

A specific embodiment according to the present invention is a semi-dynamic trigger, which includes a selection circuit, a charging and discharging circuit, a first storage circuit, an adjustment circuit, an output circuit, a second storage circuit, a reset Circuit and a switch. The selection circuit is used for selecting an input signal from a data signal and a test signal according to a selection signal. The charging and discharging circuit is connected to an intermediate node, and charges or discharges the intermediate node according to the input signal, a clock signal and an adjustment signal. The first storage circuit is connected to the intermediate node and used for storing the potential of the intermediate node. The adjusting circuit is connected between the intermediate node and the charging and discharging circuit, and is used for generating the adjusting signal according to the clock signal and the potential of the intermediate node. The output circuit is connected between the intermediate node and an output node, and is used for adjusting the potential of the output node according to the clock signal and the potential of the intermediate node. The second storage circuit is connected to the output node and used for storing the potential of the output node. The reset circuit is used for resetting or setting the potential of the output node. The switch is connected between the adjustment circuit and the charging and discharging circuit. When the reset circuit resets or sets the potential of the output node, the switch is set to cut off the connection between the adjustment circuit and the charging and discharging circuit. When the half-dynamic flip-flop is in a normal operation mode, the switch is set to be turned on.

Description of drawings

In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and understandable, the specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings, wherein:

FIG. 1 shows a typical semi-dynamic flip-flop circuit implemented by CMOS.

FIG. 2 is a circuit diagram of a semi-dynamic flip-flop according to an embodiment of the invention.

FIG. 3 is a relative relationship of signals of the control circuit in an embodiment of the present invention.

Explanation of component numbers in the figure:

100, 200: semi-dynamic trigger 111, 211: discharge circuit

112, 212: pre-charging circuit 113, 213: adjusting circuit

114, 214: first storage circuit 115, 215: output circuit

116, 216: second storage circuits N1-N7, P1-P6: transistors

217: selection circuit 218: switch

219: Control circuit

detailed description

An embodiment according to the present invention is a half dynamic flip-flop, the circuit structure of which is shown in FIG. 2 . The semi-dynamic flip-flop 200 includes a charging and discharging circuit (comprising a discharging circuit 211 and a pre-charging circuit 212), an adjusting circuit 213, a first storage circuit 214, an output circuit 215, a second storage circuit 216, and a selection circuit 217 , a reset circuit (including transistors N6 , N7 , P3 ˜ P6 ), a switch 218 and a control circuit 219 . In FIG. 2 , the switch 218 is represented by a transmission gate, that is, a logic gate composed of an NMOS transistor and a PMOS transistor, but the implementation of the switch 218 is not limited thereto. The control circuit 219 is composed of two inverters and a NAND logic gate. In practical applications, the half-dynamic flip-flop 200 can be integrated into an integrated circuit to cooperate with other circuits, or exist independently.

The first storage circuit 214 is used to assist in storing the potential of the intermediate node X. The second storage circuit 216 is used to assist in storing the potentials of the output nodes Q, QB. In this embodiment, each of the first storage circuit 214 and the second storage circuit 216 is composed of two inverters, but it is not limited to this in practice.

The function of the half dynamic flip-flop 200 is to sample the input signal D according to the clock signal CK, and output the sampling result as signals Q and QB. The setting signal SN is used to force the sampling result QB to have a high potential. The reset signal RN is used to force the sampling result QB to have a low potential. In the selection circuit 217 , the selection signals SE and SEB, which are mutually inverse signals, are used to select one signal from the data signal D and the test signal SI as an input signal actually provided to the half dynamic flip-flop 200 . The tester can choose to replace the data signal D with the test signal SI to exclude the influence of the data signal D, and independently test whether the semi-dynamic flip-flop 200 can work normally. The operation of the semi-dynamic flip-flop 200 is described below.

In this embodiment, when both the set signal SN and the reset signal RN have a high potential, the enable signal SR_EN generated by the control circuit 219 has a low potential. In this case, the transmission gate 218 is turned on, connecting the node Y and the adjustment circuit 213 . In addition, because the enable signal SR_EN and the reset signal R (which is the inversion signal of the reset signal RN) are at low potential, the transistors N6, N7, P4-P6 in the reset circuit are all turned off, and the transistor P3 is the conduction signal. Pass. Those of ordinary skill in the technical field of the present invention can understand that the semi-dynamic flip-flop 200 in this case is equivalent to the semi-dynamic flip-flop 100 shown in FIG. 1 , and its operation mode will not be repeated here.

The input signals of the control circuit 219 are the set signal SN and the reset signal RN, and the output signals are the reset signal R, the enable signal SR_EN and its inverted signal SR_ENB. The relative relationship of these signals is shown in Figure 3. It can be seen from FIG. 2 that based on the characteristics of the logic gate in the control circuit 219, when the set signal SN of the control circuit 219 has a low potential or the reset signal RN has a low potential, the enable signal SR_EN generated by the control circuit 219 is both to have a high potential. When the enable signal SR_EN has a high potential, the transmission gate 218 will not be turned on, and the transistor N6 in the reset circuit must be turned on, and the transistor P3 must be turned off. That is to say, when any one of the set signal SN and the reset signal RN has a low potential, the node Y will be discharged to a low potential, and the discharging circuit 211 and the pre-charging circuit 212 will no longer sample the signal Q/ The QB makes an impact.

It should be noted that, in this embodiment, the set signal SN and the reset signal RN are not set to have a low potential at the same time.

When the setting signal SN of the control circuit 219 has a low potential and the reset signal RN has a high potential, the transistors P4 and P5 connected to the voltage source VDD in the reset circuit are turned on, and the transistor N7 is turned off, so that the source connected to the transistor N7 The middle node X of the pole remains at a high potential. The transistor P6 is also turned on, so the sampling signal QB also has a high potential. Since the transistor P2 is turned off and the transistor N4 is turned on, when the clock signal CK has a high potential, the node of the sampling signal Q is pulled to a low potential; when the clock signal CK has a low potential, the node of the sampling signal Q is at the output The other end of the inverter is the high potential QB, so the sampling signal Q is also maintained at low potential. That is to say, no matter whether the clock signal CK has a high potential or a low potential, the output circuit 215 cannot pull the sampling signal Q to a high potential. In other words, the sampling signal Q is forcibly set to have a low potential, and the sampling signal QB is forcibly set to have a high potential.

When the setting signal SN has a high potential and the reset signal RN has a low potential, the transistors P4, P5, and P6 in the reset circuit are turned off, and the transistor N7 is turned on, so that the intermediate node X is set to have a low potential, Further, the transistor P2 is turned on. In this case, the sampling signal Q is forcibly set to have a high potential, and the sampling signal QB is forcibly set to have a low potential.

It can be seen from FIG. 2 that the adjustment signal generated by the adjustment circuit 213 according to the clock signal CK and the potential of the intermediate node X is used to control the transistor N3. The main function of the transmission gate 218 is to selectively eliminate the influence of the intermediate node X and the clock signal CK on the node Y, so that the potential of the node Y is only controlled by the transistor N6, thereby preventing the discharge circuit 211 from being reset in the semi-dynamic flip-flop 200 Affects the potential of the intermediate node X when set or set.

As mentioned above, when the half-dynamic flip-flop 200 enters the evaluation phase, if the input signal D has a high potential, the discharge circuit 211 will discharge the intermediate node X to a low potential. It should be noted that when the transmission gate 218 is turned on, the transmission gate 218 also contributes a delay time in the path of the clock signal CK transmitted to the node Y via the adjustment circuit 213 . The increase of this delay time (compared with the circuit in FIG. 1 ) can delay the time when the transistor N3 is turned off, which is equivalent to prolonging the time for the allowable signal D" to stabilize before the discharge circuit 211 stops discharging the intermediate node X. Therefore, although the selection circuit 217 will cause the time for the data signal D or the test signal SI to enter the discharge circuit 211 to be delayed (that is, the time for the allowable signal D" to stabilize is reduced), the existence of the transmission gate 218 can correspondingly balance This problem, therefore, may reduce the maximum operating speed of the semi-dynamic flip-flop 200 after adding the reset function and the test function.

It should be noted that, in practice, the signal generated by the control circuit 219 can also be provided by an external circuit. In other words, the control circuit 219 is not a necessary element in the half dynamic flip-flop 200 . In addition, those of ordinary skill in the technical field of the present invention can understand that the detailed implementation of each circuit block is not limited to what is shown in FIG. 2 . For example, without changing the logic operation of the half-dynamic flip-flop 200 , the discharge circuit 211 , the pre-charge circuit 212 , and the output circuit 215 may all include more transistors. Alternatively, the logic gates in the adjustment circuit 213 can be replaced by other components with the same operation logic.

As mentioned above, the present invention proposes a new semi-dynamic flip-flop architecture, adding reset function and test function. By properly configuring the logic elements in the circuit, the half-dynamic flip-flop according to the present invention will not reduce the maximum operating speed of the half-dynamic flip-flop due to the addition of new functions.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some modifications and improvements without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection should be defined by the claims.

Claims (2)

1. A semi-dynamic trigger comprising: a selection circuit for selecting an input signal from a data signal and a test signal according to a selection signal; A charging and discharging circuit, connected to an intermediate node, and charging or discharging the intermediate node according to the input signal, a clock signal and an adjustment signal; a first storage circuit, connected to the intermediate node, for storing the potential of the intermediate node; an adjustment circuit, connected between the intermediate node and the charge-discharge circuit, for generating the adjustment signal according to the clock signal and the potential of the intermediate node; an output circuit, connected between the intermediate node and an output node, for adjusting the potential of the output node according to the clock signal and the potential of the intermediate node; a second storage circuit, connected to the output node, for storing the potential of the output node; a reset circuit for resetting or setting the potential of the output node; and a switch connected between the adjustment circuit and the charging and discharging circuit, when the reset circuit resets or sets the potential of the output node, the switch is set to cut off the connection between the adjusting circuit and the charging and discharging circuit, When the half-dynamic flip-flop is in a normal operation mode, the switch is set to be turned on. 2. The semi-dynamic flip-flop as claimed in claim 1, wherein the switch is a transmission gate.