CN101465631A - Delay circuit - Google Patents

Abstract

A delay circuit capable of providing high stable delay time for digital signal processing comprises a pre-stage charging and discharging circuit, a signal processing circuit and an output circuit. The output circuit executes the logic signal processing of the first and second delay signals to generate a logic output signal lagging behind the logic input signal by a delay time which is independent of the power supply voltage, so that even if the power supply voltage is unstable, the delay circuit can execute the signal delay processing of the logic input signal under the influence of the power supply voltage to generate a stable logic output signal.

Description

delay circuit

technical field

The present invention relates to a delay circuit, especially a delay circuit which can provide high stable delay time for digital signal processing without being affected by power supply voltage variation.

Background technique

In many circuits, such as a clock generator (clock generator) or a radio frequency transmission receiver (RF transceiver), the accuracy of the signal phase is very high. When the signal phase deviates, it will have a considerable impact on the entire system. Impact. As for the multi-phase clock signal generator (multi-phase clock generator), the accuracy of the phase difference between each output signal is also very important. When the phase error increases, the clock jitter of the output clock signal also increases. will increase, which may lead to serious errors in subsequent circuits for systems that require precise clock signals, such as sampling point errors in analog-to-digital converters, or increased bit error rates. Therefore, when designing a circuit that requires high phase accuracy, the layout path will be carefully handled. However, when the supply voltage drifts, the known delay circuit technology usually cannot provide accurate phase delay. At this time, additional mechanisms need to be used. Correct for phase shift.

The known delay circuit technology mainly uses the charging and discharging effect of the capacitor to delay the signal to be transmitted to the next stage. Please refer to FIG. 1 . FIG. 1 is a schematic circuit diagram showing a known delay circuit 100 . The delay circuit 100 includes a previous charging and discharging circuit 105 and an inverter 190 . The pre-stage charging and discharging circuit 105 includes a first current source 110 , a second current source 112 , a first control switch 120 , a second control switch 122 , and a capacitor 130 . The inverter 190 includes a P-channel metal oxide half field effect transistor (PMOSFET) 180 and an N channel metal oxide half field effect transistor (NMOSFET) 182 . The delay circuit 100 is coupled between a first supply voltage Vdd and a second supply voltage Vss, and the first control switch 120 and the second control switch 122 are controlled by a logic input signal Sin. According to the switching states of the first control switch 120 and the second control switch 122 , the first current source 110 and the second current source 112 can perform charging and discharging operations on the capacitor 130 to generate the voltage signal Vc. The inverter 190 performs signal inversion processing of the voltage signal Vc of the capacitor 130 to generate a logic output signal Sout lagging behind the logic input signal Sin by a delay time.

However, when the supply voltage of the first supply voltage Vdd or the second supply voltage Vss drifts, the transition voltage from the input to the output of the inverter 190 changes accordingly, so that the voltage range corresponding to the delay time for charging and discharging the capacitor 130 follows Change, the delay time leading to input to output will also change, in other words, when the supply voltage is unstable, the delay time will also be unstable.

Please refer to FIG. 2 . FIG. 2 is a circuit schematic diagram showing another known delay circuit 200 . The delay circuit 200 includes a previous charging and discharging circuit 205 and a comparing circuit 290 . The pre-stage charge-discharge circuit 205 is used to generate the voltage signal Vc according to the logic input signal Sin, and its internal circuit structure is the same as that of the above-mentioned pre-stage charge-discharge circuit 105 , so it will not be described again. The comparison circuit 290 includes a first voltage dividing resistor 291 , a second voltage dividing resistor 292 , and a comparator 295 . The first voltage dividing resistor 291 and a second voltage dividing resistor 292 are coupled between the first supply voltage Vdd and the second supply voltage Vss for providing a comparison reference voltage Vr. The comparator 295 performs a signal comparison process between the voltage signal Vc and the comparison reference voltage Vr to generate a logic output signal Sout.

The delay circuit 200 sets the rising and falling transition voltages of the voltage signal Vc as the comparison reference voltage Vr, but it is still affected by the supply voltage drift. In addition, the extra power consumption of the first and second voltage divider resistors is also a shortcoming of this circuit. If a high voltage divider resistor is used to reduce the extra power consumption, a considerable area of the voltage divider resistor elements will be consumed in the circuit layout design. It is not conducive to circuit density and production cost.

Contents of the invention

The object of the present invention is to provide a delay circuit which is not affected by supply voltage drift. In addition, in the circuit layout design, there is no need to consume a considerable area of the voltage dividing resistor element, which is beneficial to the reduction of circuit density and production cost.

According to an embodiment of the present invention, a delay circuit is disclosed, which includes a pre-stage charging and discharging circuit, a signal processing circuit, and an output circuit. The pre-stage charge-discharge circuit includes an input terminal for receiving a logic input signal and an output terminal for outputting a voltage signal. The pre-stage charge-discharge circuit is used to execute a charge-discharge procedure according to the logic input signal to generate a voltage signal. The signal processing circuit is coupled to the output terminal of the pre-stage charging and discharging circuit to receive the voltage signal, and is used to generate a first delay signal and a second delay signal according to the voltage signal. The signal processing circuit includes a first current source, a first transistor , a second current source, and a second transistor. The first current source includes a first terminal for receiving a first supply voltage, and a second terminal. The first transistor includes a first terminal for receiving a second supply voltage, a second terminal coupled to the second terminal of the first current source, and a control terminal coupled to the output terminal of the pre-stage charging and discharging circuit for receiving the voltage signal , wherein the second terminal of the first transistor is used to output the first delayed signal. The second current source includes a first terminal for receiving the second supply voltage, and a second terminal. The second transistor includes a first terminal for receiving the first supply voltage, a second terminal coupled to the second terminal of the second current source, and a control terminal coupled to the output terminal of the pre-stage charging and discharging circuit for receiving the voltage signal, Wherein the second terminal of the second transistor is used to output the second delayed signal. The output circuit includes a first input terminal coupled to the second terminal of the first transistor for receiving the first delayed signal, a second input terminal coupled to the second terminal of the second transistor for receiving the second delayed signal, and a The third input terminal is used to receive the logic input signal, and the output terminal is used to output a logic output signal. The output circuit generates the logic output signal according to the first delay signal, the second delay signal and the logic input signal.

According to an embodiment of the present invention, it further discloses a delay circuit, which includes a pre-stage charging and discharging circuit, a signal processing circuit, and an output circuit. The pre-stage charge-discharge circuit includes an input terminal for receiving a logic input signal and an output terminal for outputting a voltage signal. The pre-stage charge-discharge circuit is used to execute a charge-discharge procedure according to the logic input signal to generate a voltage signal. The signal processing circuit is coupled to the output terminal of the pre-stage charging and discharging circuit to receive the voltage signal, and is used to generate a first delay signal and a second delay signal according to the voltage signal. The signal processing circuit includes a first current source, a first transistor , a second current source, and a second transistor. The first current source includes a first terminal for receiving a first supply voltage, and a second terminal. The first transistor includes a first terminal for receiving a second supply voltage, a second terminal coupled to the second terminal of the first current source, and a control terminal coupled to the output terminal of the pre-stage charging and discharging circuit for receiving the voltage signal , wherein the second terminal of the first transistor is used to output the first delayed signal. The second current source includes a first terminal for receiving the second supply voltage, and a second terminal. The second transistor includes a first terminal for receiving the first supply voltage, a second terminal coupled to the second terminal of the second current source, and a control terminal coupled to the output terminal of the pre-stage charging and discharging circuit for receiving the voltage signal, Wherein the second terminal of the second transistor is used to output the second delayed signal. The output circuit includes a first input terminal coupled to the second terminal of the first transistor for receiving the first delayed signal, a second input terminal coupled to the second terminal of the second transistor for receiving the second delayed signal, and An output terminal is used to output a logic output signal, and the output circuit generates a logic output signal according to the first delay signal and the second delay signal.

Description of drawings

In order to make the present invention clearer and easier to understand, the delay circuit according to the present invention will be described in detail below with reference to specific embodiments in conjunction with the accompanying drawings, but the provided embodiments are not intended to limit the scope of the present invention, wherein:

FIG. 1 shows a circuit diagram of a known delay circuit.

FIG. 2 shows a schematic circuit diagram of another known delay circuit.

FIG. 3 shows a schematic circuit diagram of a delay circuit according to a first embodiment of the present invention.

FIG. 4 shows a timing diagram of operation-related signals of the delay circuit of FIG. 3 .

FIG. 5 shows a schematic circuit diagram of a delay circuit according to a second embodiment of the present invention.

FIG. 6 shows a schematic circuit diagram of a delay circuit according to a third embodiment of the present invention.

FIG. 7 shows a schematic circuit diagram of a delay circuit according to a fourth embodiment of the present invention.

Detailed ways

Please refer to FIG. 3 . FIG. 3 is a circuit diagram showing a delay circuit 300 according to a first embodiment of the present invention. The delay circuit 300 includes a pre-stage charging and discharging circuit 305 , a signal processing circuit 350 , and an output circuit 380 . The signal processing circuit 350 includes a first current source 370 , a first transistor 360 , a second current source 372 , and a second transistor 362 . The pre-stage charging and discharging circuit 305 includes a third current source 310 , a first control switch 320 , a fourth current source 312 , a second control switch 322 , and a capacitor 330 . The output circuit 380 includes a first NOR gate 381 , a second NOR gate 383 , a third NOR gate 385 , and a fourth NOR gate 388 .

The third current source 310 includes a first terminal and a second terminal, wherein the first terminal is used for receiving a first supply voltage Vdd, and the second terminal is used for supplying a current I3. The first control switch 320 includes a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to the second terminal of the third current source 310 to receive the current I3, and the control terminal is used to receive a logic The input signal Sin, the second terminal is used to output the current I3, and the first control switch 320 is used to control the coupling state of the first terminal and the second terminal according to the logic input signal Sin. The fourth current source 312 includes a first terminal and a second terminal, wherein the first terminal is used to receive a second supply voltage Vss, and the second terminal is used to supply a current I4, and the second supply voltage Vss can be a ground voltage . The second control switch 322 includes a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to the second terminal of the fourth current source 312 to receive the current I4, and the control terminal is used to receive the logic input The second end of the signal Sin is used to output the current I4, and the second control switch 322 is used to control the coupling state of the first end and the second end of the signal Sin according to the logic input signal Sin. The first control switch 320 and the second control switch 322 can be electronic relays (Electronic Relay), metal oxide field effect transistors (MOS Transistor), or bipolar transistors (Bipolar Transistor).

The capacitor 330 includes a first terminal and a second terminal, wherein the first terminal is coupled to the second terminal of the first control switch 320 for outputting a voltage signal Vc, and the second terminal is used for receiving the second supply voltage Vss. When the logic input signal Sin is a low level voltage, the first control switch 320 is turned on and the second control switch 322 is turned off, so the capacitor 330 can be charged by the current I3 provided by the third current source 310 to make the voltage signal Vc rises to the first supply voltage Vdd. When the logic input signal Sin is a high-level voltage, the first control switch 320 is turned off and the second control switch 322 is turned on, so the capacitor 330 can perform a discharge process through the current I4 provided by the fourth current source 312, so that the voltage signal Vc drops to the second supply voltage Vss.

The first current source 370 includes a first terminal and a second terminal, wherein the first terminal is used for receiving the first supply voltage Vdd, and the second terminal is used for supplying a current I1. The first transistor 360 includes a first terminal, a second terminal, and a control terminal, wherein the first terminal is used to receive the second supply voltage Vss, the second terminal is coupled to the second terminal of the first current source 370, and the control terminal Coupled to the first end of the capacitor 330 for receiving the voltage signal Vc, the second end of the first transistor 360 is used for outputting a first delay signal Sd1, the first transistor 360 is an N-channel Metal Oxide Half Field Effect Transistor (NMOS Field Effect Transistor) or an N-channel Junction Field Effect Transistor (N-channel Junction Field Effect Transistor).

The second current source 372 includes a first terminal and a second terminal, wherein the first terminal is used for receiving the second supply voltage Vss, and the second terminal is used for supplying a current I2. The second transistor 362 includes a first terminal, a second terminal, and a control terminal, wherein the first terminal is used to receive the first supply voltage Vdd, the second terminal is coupled to the second terminal of the second current source 372, and the control terminal Coupled to the first terminal of the capacitor 330 for receiving the voltage signal Vc, the second terminal of the second transistor 362 is used for outputting a second delay signal Sd2, and the second transistor 362 is a P-channel Metal Oxide Half Field Effect Transistor (PMOS Field Effect Transistor) or a P-channel Junction Field Effect Transistor (P-channel Junction Field Effect Transistor).

The first NOR gate 381 includes a first input end, a second input end, and an output end, wherein the first input end is used to receive the logic input signal Sin, and the second input end is coupled to the second end of the second transistor 362. The terminal is used for receiving the second delayed signal Sd2, and the output terminal is used for outputting a first signal generated by performing logical inverse OR processing of the logical input signal Sin and the second delayed signal Sd2. The second NOR gate 383 includes a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal is coupled to the second terminal of the second transistor 362 for receiving the second delay signal Sd2, the second The two input ends are coupled to the second end of the first transistor 360 for receiving the first delay signal Sd1, and the output end is used for outputting a first delay signal Sd1 and the second delay signal Sd2 which are generated by logical inverse OR processing. Two signals. The third NOR gate 385 includes a first input end, a second input end, and an output end, wherein the first input end is used to receive the logic input signal Sin, and the second input end is coupled to the second end of the first transistor 360. The terminal is used for receiving the first delayed signal Sd1, and the output terminal is used for outputting a third signal generated by performing logical inverse OR processing of the logic input signal Sin and the first delayed signal Sd1.

The fourth NOR gate 388 includes a first input terminal, a second input terminal, a third input terminal, and an output terminal, wherein the first input terminal is coupled to the output terminal of the first NOR gate 381 for receiving The first signal, the second input terminal is coupled to the output terminal of the second NOR gate 383 for receiving the second signal, the third input terminal is coupled to the output terminal of the third NOR gate 385 for receiving the third signal, The output terminal is used for outputting a logic output signal Sout generated by performing logical inverse OR processing of the first signal, the second signal, and the third signal.

Please refer to FIG. 4 . FIG. 4 is a timing diagram showing operation-related signals of the delay circuit 300 in FIG. 3 , and the horizontal axis is the time axis. The work-related signals shown in FIG. 4 are, from top to bottom, the logic input signal Sin, the voltage signal Vc, the first delay signal Sd1, the second delay signal Sd2, and the logic output signal Sout. The logic input signal Sin changes from a low-level voltage to a high-level voltage at time T1, the first control switch 320 turns from on to off, the second control switch 322 turns from off to on, and the capacitor 330 passes the fourth current The current I4 provided by the source 312 executes a discharge procedure, so that the voltage of the voltage signal Vc decreases gradually from the first supply voltage Vdd. At time T2, the voltage of the voltage signal Vc decreases to be equal to a second transition voltage Vt2, and a voltage difference between the control terminal and the first terminal of the second transistor 362 is equal to a voltage corresponding to the second transistor 362. The second threshold voltage Vth2 turns the second transistor 362 from off to on, so the second delay signal Sd2 turns from a low level voltage to a high level voltage. At time T3, the voltage of the voltage signal Vc decreases to be equal to a first transition voltage Vt1, and a voltage difference between the control terminal and the first terminal of the first transistor 361 is equal to a voltage corresponding to the first transistor 361. The first threshold voltage Vth1 turns the first transistor 361 from on to off, so the first delay signal Sd1 turns from a low level voltage to a high level voltage.

The logic input signal Sin changes from a high-level voltage to a low-level voltage at time T4, the first control switch 320 turns from off to on, the second control switch 322 turns from on to off, and the capacitor 330 passes the third current The current I3 provided by the source 310 executes the charging process, so that the voltage of the voltage signal Vc increases from the second supply voltage Vss. At time T5, the voltage of the voltage signal Vc is increased to be equal to the first transition voltage Vt1, and the voltage difference between the control terminal and the first terminal of the first transistor 361 is equal to the first threshold voltage Vth1, so that the first transistor 361 is controlled by Turning off turns on, so the first delay signal Sd1 turns from a high level voltage to a low level voltage. At time T6, the voltage of the voltage signal Vc is increased to be equal to the second transition voltage Vt2, and the voltage difference between the control terminal and the first terminal of the second transistor 362 is equal to the second threshold voltage Vth2, so that the second transistor 362 is turned on. turns off, so the second delay signal Sd2 turns from the high level voltage to the low level voltage.

The first delay signal Sd1 , the second delay signal Sd2 , and the logic input signal Sin are processed by the logic signal of the output circuit 380 to generate the logic output signal Sout as shown in FIG. 4 . The leading edge of the pulse wave of the logic output signal Sout lags behind the leading edge of the pulse wave of the logic input signal Sin by a rising edge delay time DT1, and the trailing edge of the pulse wave of the logic output signal Sout lags behind the pulse wave leading edge of the logic output signal Sout by a falling edge delay time (falling edge delay time) DT2 lags behind the pulse trailing edge of the logic input signal Sin. The rising edge delay time DT1 and the falling edge delay time DT2 can be calculated according to the following formulas (1) and (2).

$\mathrm{<figure-callout\; id="1"\; label="DT"\; filenames="A200710162170E00331.png,A200710162170E00341.png"\; state="\{\{state\}\}">DT</figure-callout>}1=\frac{C\&times;\mathrm{Vth}2}{\mathrm{IC}4}$ ……Formula 1)

$\mathrm{DT}2=\frac{C\&times;\mathrm{<figure-callout\; id="1"\; label="Vth"\; filenames="A200710162170E00331.png,A200710162170E00341.png"\; state="\{\{state\}\}">Vth</figure-callout>}1}{\mathrm{IC}3}$ ...Formula (2)

Wherein, the parameter C is the capacitance value of the capacitor 330 , the parameter Ic3 is the current value of the current I3 , and the parameter Ic4 is the current value of the current I4 . According to the above formulas (1) and (2), it can be seen that the rising edge delay time DT1 is determined by the current value Ic4, the second threshold voltage Vth2, and the capacitance value C, while the falling edge delay time DT2 is determined by the current value Ic3, the second threshold voltage Vth2, and the capacitance value C. A threshold voltage Vth1 and a capacitance value C are determined. Therefore, all parameters of formulas (1) and (2) are not affected by the first supply voltage Vdd and the second supply voltage Vss. In other words, when the first supply voltage When the voltage drift of Vdd or the second supply voltage Vss occurs, neither the rising-edge delay time DT1 nor the falling-edge delay time DT2 is affected, and the delay circuit 300 can still generate a stable logic output signal Sout according to the logic input signal Sin.

Please refer to FIG. 5 . FIG. 5 is a circuit diagram showing a delay circuit 500 according to a second embodiment of the present invention. The delay circuit 500 includes a pre-stage charging and discharging circuit 505 , a signal processing circuit 550 , and an output circuit 580 . The signal processing circuit 550 includes a first current source 570 , a first transistor 560 , a second current source 572 , and a second transistor 562 . The pre-stage charging and discharging circuit 505 includes a third current source 510 , a first control switch 520 , a fourth current source 512 , a second control switch 522 , and a capacitor 530 . The output circuit 580 includes a first OR gate 581 , a second OR gate 583 , a third OR gate 585 , and an AND gate 588 .

The internal circuit structure of the pre-stage charge-discharge circuit 505 is the same as that of the pre-stage charge-discharge circuit 305 , so the circuit connection of its related components will not be repeated here. The first current source 570 includes a first terminal and a second terminal, wherein the first terminal is used for receiving the first supply voltage Vdd, and the second terminal is used for supplying a current I1. The first transistor 560 includes a first terminal, a second terminal, and a control terminal, wherein the first terminal is used to receive the second supply voltage Vss, the second terminal is coupled to the second terminal of the first current source 570, and the control terminal Coupled to the capacitor 530 for receiving a voltage signal Vc, the second terminal of the first transistor 560 is used for outputting a first delay signal Sd1, and the first transistor 560 is an NPN bipolar transistor.

The second current source 572 includes a first terminal and a second terminal, wherein the first terminal is used for receiving the second supply voltage Vss, and the second terminal is used for supplying a current I2. The second transistor 562 includes a first terminal, a second terminal, and a control terminal, wherein the first terminal is used to receive the first supply voltage Vdd, the second terminal is coupled to the second terminal of the second current source 572, and the control terminal Coupled to the capacitor 530 for receiving the voltage signal Vc, the second terminal of the second transistor 562 is used for outputting a second delay signal Sd2, and the second transistor 562 is a PNP bipolar transistor.

The first OR gate 581 includes a first input end, a second input end, and an output end, wherein the first input end is used to receive a logic input signal Sin, and the second input end is coupled to the second end of the second transistor 562. The terminal is used for receiving the second delayed signal Sd2, and the output terminal is used for outputting a first signal generated by logical OR processing of the input logic signal Sin and the second delayed signal Sd2. The second OR gate 583 includes a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal is coupled to the second terminal of the second transistor 562 for receiving the second delay signal Sd2, and the second The input end is coupled to the second end of the first transistor 560 for receiving the first delayed signal Sd1, and the output end is used for outputting a second signal generated by logical OR processing of the first delayed signal Sd1 and the second delayed signal Sd2. . The third OR gate 585 includes a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal is used to receive the logic input signal Sin, and the second input terminal is coupled to the second terminal of the first transistor 560 , for receiving the first delayed signal Sd1 , and the output end is used for outputting a third signal generated by logical OR processing of the logic input signal Sin and the first delayed signal Sd1 .

The AND gate 588 includes a first input terminal, a second input terminal, a third input terminal, and an output terminal, wherein the first input terminal is coupled to the output terminal of the first OR gate 581 for receiving the first signal, The second input end is coupled to the output end of the second OR gate 583 to receive the second signal, the third input end is coupled to the output end of the third OR gate 585 to receive the third signal, and the output end is used to output the execution A logic output signal Sout is generated by logic sum processing of the first signal, the second signal, and the third signal.

The timing diagram corresponding to the operation of the logic input signal Sin, the voltage signal Vc, the first delay signal Sd1, the second delay signal Sd2, and the logic output signal Sout of the delay circuit 500 is the same as that of the delay circuit 300 shown in FIG. 4 The working timing diagram of related signals, so its working principle will not be described in detail.

Please refer to FIG. 6 . FIG. 6 is a circuit diagram showing a delay circuit 600 according to a third embodiment of the present invention. The delay circuit 600 includes a pre-stage charging and discharging circuit 605 , a signal processing circuit 650 , and an output circuit 680 . The signal processing circuit 650 includes a first current source 670 , a first transistor 660 , a second current source 672 , and a second transistor 662 . The pre-stage charging and discharging circuit 605 includes a third current source 610 , a first control switch 620 , a fourth current source 612 , a second control switch 622 , and a capacitor 630 . The output circuit 680 includes an inverter 681 , a first NAND gate 683 , a second NAND gate 685 , an AND gate 687 , and an OR gate 689 .

The internal circuit structure of the pre-stage charging and discharging circuit 605 and the signal processing circuit 650 is the same as the internal circuit structure of the pre-stage charging and discharging circuit 305 and the signal processing circuit 350, so the circuit connection of the related components will not be repeated. The inverter 681 includes an input terminal and an output terminal, wherein the input terminal is coupled to the first transistor 660 for receiving a first delayed signal Sd1, and the output terminal is used for outputting the logical inversion processing of the first delayed signal Sd1 A first signal is generated. The first NAND gate 683 includes a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal is coupled to the output terminal of the inverter 681 for receiving the first signal. The second NAND gate 685 includes a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal is coupled to the second transistor 662 for receiving a second delay signal Sd2, and the second input terminal coupled to the output terminal of the first NAND gate 683 , and the output terminal is coupled to the second input terminal of the first NAND gate 683 . The first NAND gate 683 and the second NAND gate 685 are combined into an RS flip-flop (RS Flip-Flop), which is used to generate a second signal according to the second delay signal Sd2 and the first signal, and from the second and The output terminal of the NOT gate 685 outputs the second signal. The AND gate 687 includes a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal is coupled to the second transistor 662 for receiving the second delay signal Sd2, and the second input terminal is coupled to the second transistor 662. The output terminal of the NAND gate 685 is used for receiving the second signal, and the output terminal is used for outputting a third signal generated by performing logic AND processing on the second delayed signal Sd2 and the second signal. The OR gate 689 includes a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal is coupled to the output terminal of the AND gate 687 for receiving the third signal, and the second input terminal is coupled to the first The transistor 660 is used for receiving the first delayed signal Sd1 , and the output terminal is used for outputting a logic output signal Sout generated by performing logical OR processing of the first delayed signal Sd1 and the third signal.

Please note that the output circuit 680 only generates the logic output signal Sout according to the first delay signal Sd1 and the second delay signal Sd2 , and does not need to input the logic input signal Sin to the output circuit 680 . The working timing diagram corresponding to the logic input signal Sin, the voltage signal Vc, the first delay signal Sd1, the second delay signal Sd2, and the logic output signal Sout of the delay circuit 600 is still the same as that of the delay circuit 300 shown in FIG. The working timing diagram of related signals, so its working principle will not be described in detail.

Please refer to FIG. 7 . FIG. 7 is a circuit diagram showing a delay circuit 700 according to a fourth embodiment of the present invention. The delay circuit 700 includes a pre-stage charging and discharging circuit 705 , a signal processing circuit 750 , and an output circuit 780 . The signal processing circuit 750 includes a first current source 770 , a first transistor 760 , a second current source 772 , and a second transistor 762 . The pre-stage charging and discharging circuit 705 includes a third current source 710 , a first control switch 720 , a fourth current source 712 , a second control switch 722 , and a capacitor 730 . The output circuit 780 includes an inverter 781, a first NAND gate 783, a second NAND gate 785, an AND gate 787, an OR gate 789, and a plurality of buffers 791-794.

The internal circuit structures of the pre-stage charge-discharge circuit 705 and the signal processing circuit 750 are the same as those of the pre-stage charge-discharge circuit 505 and the signal processing circuit 550 , so the circuit connections of related components will not be repeated here. The buffer 791 is coupled between the second transistor 762 and an input terminal of the AND gate 787, the buffers 792-794 are coupled between the first transistor 760 and an input terminal of the OR gate 789, and the rest of the internal circuit structure of the output circuit 780 It is the same as the output circuit 680, so it will not be repeated here. The working timing diagram corresponding to the logic input signal Sin, the voltage signal Vc, the first delay signal Sd1, the second delay signal Sd2, and the logic output signal Sout of the delay circuit 700 is still the same as that of the delay circuit 300 shown in FIG. The working timing diagram of related signals, so its working principle will not be described in detail.

From the above, it can be known that the delay circuit according to the present invention determines the signal delay time according to the critical voltage of the transistor, the capacitance value of the capacitive element, and the current value of the current source, that is, the signal delay time is not affected by the drift of the supply voltage, so when the supply voltage When the voltage is unstable, the delay circuit according to the present invention can still generate a stable logic output signal according to the logic input signal, so that the logic output signal will not cause clock jitter due to the unstable supply voltage.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the claims of the present invention shall fall within the scope of the present invention.

Claims (9)

1. a delay circuit is characterized in that, comprises:

One prime charge-discharge circuit, it comprises an input in order to receive a logic input signal, reaches an output in order to export a voltage signal, and this prime charge-discharge circuit is to produce this voltage signal in order to carry out the program of discharging and recharging according to this logic input signal;

One signal processing circuit, this output that is coupled in this prime charge-discharge circuit is to receive this voltage signal, and in order to produce one first inhibit signal and one second inhibit signal according to this voltage signal, this signal processing circuit comprises:

One first current source, it comprises one first end in order to receive one first supply voltage, reaches one second end;

One the first transistor, it comprises one first end in order to receive one second supply voltage, one second end is coupled in this second end of this first current source, and a control end is coupled in this output of this prime charge-discharge circuit, in order to receive this voltage signal, wherein this of this first transistor second end is in order to export this first inhibit signal;

One second current source, it comprises one first end in order to receive this second supply voltage, reaches one second end; And

One transistor seconds, it comprises one first end in order to receive this first supply voltage, one second end is coupled in this second end of this second current source, and a control end is coupled in this output of this prime charge-discharge circuit, in order to receive this voltage signal, wherein this of this transistor seconds second end is in order to export this second inhibit signal; And

One output circuit, it comprises this second end that a first input end is coupled in this first transistor, in order to receive this first inhibit signal, one second input is coupled in this second end of this transistor seconds, in order to receive this second inhibit signal, one the 3rd input is in order to receiving this logic input signal, and an output is in order to export a logic output signal, wherein this output circuit according to this first inhibit signal, this second inhibit signal, and this logic input signal produce this logic output signal.

2. delay circuit as claimed in claim 1 is characterized in that, wherein this prime charge-discharge circuit comprises:

One the 3rd current source, it comprises one first end in order to receive this first supply voltage, reaches one second end;

One first control switch, it comprises this second end that one first end is coupled in the 3rd current source, and a control end reaches one second end in order to receive this logic input signal;

One the 4th current source, it comprises one first end in order to receive this second supply voltage, reaches one second end;

One second control switch, it comprises this second end that one first end is coupled in the 4th current source, and a control end reaches this second end that one second end is coupled in this first control switch in order to receive this logic input signal; And

One electric capacity, it comprises this second end that one first end is coupled in this first control switch, in order to export this voltage signal, reaches one second end in order to receive this second supply voltage.

3. delay circuit as claimed in claim 1 is characterized in that, wherein this output circuit comprises:

One first NOR gate, it comprises a first input end in order to receive this logic input signal, and one second input is coupled in this second end of this transistor seconds, in order to receive this second inhibit signal, reaches an output;

One second NOR gate, it comprises this second end that a first input end is coupled in this transistor seconds, and in order to receive this second inhibit signal, one second input is coupled in this second end of this first transistor, in order to receive this first inhibit signal, reaches an output;

One the 3rd NOR gate, it comprises a first input end in order to receive this logic input signal, and one second input is coupled in this second end of this first transistor, in order to receive this first inhibit signal, reaches an output; And

One four nor gate, it comprises this output that a first input end is coupled in this first NOR gate, one second input is coupled in this output of this second NOR gate, and one the 3rd input is coupled in this output of the 3rd NOR gate, and an output is in order to export this logic output signal.

4. delay circuit as claimed in claim 1 is characterized in that, wherein this output circuit comprises:

One first or door, it comprises a first input end in order to receive this logic input signal, and one second input is coupled in this second end of this transistor seconds, in order to receiving this second inhibit signal, and an output;

One second or door, it comprises this second end that a first input end is coupled in this transistor seconds, and in order to receive this second inhibit signal, one second input is coupled in this second end of this first transistor, in order to receiving this first inhibit signal, and an output;

One the 3rd or door, it comprises a first input end in order to receive this logic input signal, and one second input is coupled in this second end of this first transistor, in order to receiving this first inhibit signal, and an output; And

One with the door, its comprise a first input end be coupled in this first or the door this output, one second input be coupled in this second or this output of door, one the 3rd input is coupled in the 3rd or this output of door, and an output is in order to export this logic output signal.

5. a delay circuit is characterized in that, comprises:

One prime charge-discharge circuit, it comprises an input in order to receive a logic input signal, reaches an output in order to export a voltage signal, and this prime charge-discharge circuit is to produce this voltage signal in order to carry out the program of discharging and recharging according to this logic input signal;

One signal processing circuit, this output that is coupled in this prime charge-discharge circuit is to receive this voltage signal, and in order to produce one first inhibit signal and one second inhibit signal according to this voltage signal, this signal processing circuit comprises:

One first current source, it comprises one first end in order to receive one first supply voltage, reaches one second end;

One the first transistor, it comprises one first end in order to receive one second supply voltage, one second end is coupled in this second end of this first current source, and a control end is coupled in this output of this prime charge-discharge circuit, to receive this voltage signal, wherein this of this first transistor second end is in order to export this first inhibit signal;

One second current source, it comprises one first end in order to receive this second supply voltage, reaches one second end; And

One transistor seconds, it comprises one first end in order to receive this first supply voltage, one second end is coupled in this second end of this second current source, and a control end is coupled in this output of this prime charge-discharge circuit, to receive this voltage signal, wherein this of this transistor seconds second end is in order to export this second inhibit signal; And

One output circuit, it comprises this second end that a first input end is coupled in this first transistor, in order to receive this first inhibit signal, one second input is coupled in this second end of this transistor seconds, in order to receive this second inhibit signal, reach an output in order to export a logic output signal, wherein this output circuit produces this logic output signal according to this first inhibit signal and this second inhibit signal.

6. delay circuit as claimed in claim 5 is characterized in that, wherein this prime charge-discharge circuit comprises:

One the 3rd current source, it comprises one first end in order to receive this first supply voltage, reaches one second end;

One first control switch, it comprises this second end that one first end is coupled in the 3rd current source, and a control end reaches one second end in order to receive this logic input signal;

One the 4th current source, it comprises one first end in order to receive this second supply voltage, reaches one second end;

One second control switch, it comprises this second end that one first end is coupled in the 4th current source, and a control end reaches this second end that one second end is coupled in this first control switch in order to receive this logic input signal; And

One electric capacity, it comprises this second end that one first end is coupled in this first control switch, in order to export this voltage signal, reaches one second end, in order to receive this second supply voltage.

7. delay circuit as claimed in claim 5 is characterized in that, wherein this output circuit comprises:

One inverter, it comprises this second end that an input is coupled in this first transistor receiving this first inhibit signal, and an output;

One first NAND gate, it comprises a first input end, one second input, reaches an output, and this first input end is coupled in this output of this inverter;

One second NAND gate, it comprises a first input end and is coupled in this second end of this transistor seconds to receive this second inhibit signal, one second input is coupled in this output of this first NAND gate, and an output is coupled in this second input of this first NAND gate;

One with door, it contains this second end that a first input end is coupled in this transistor seconds to receive this second inhibit signal, one second input is coupled in this output of this second NAND gate, and an output; And

One or door, it comprises a first input end and is coupled in this and this output of door, and this second end that one second input is coupled in this first transistor is receiving this first inhibit signal, and an output is in order to export this logic output signal.

8. delay circuit as claimed in claim 7 is characterized in that, wherein this output circuit comprises in addition:

At least one buffer, be coupled in this first transistor this second end and should or the door this second input between.

9. delay circuit as claimed in claim 7 is characterized in that, wherein this output circuit comprises in addition:

At least one buffer, be coupled in this transistor seconds this second end and should and this first input end of door between.

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