CN104124200A - TSV manufacturing method - Google Patents

Abstract

The invention relates to a method for manufacturing a through silicon via, which comprises the following steps. A substrate is provided. A through hole is formed in the substrate, the through hole having a diameter of at least one micron and a depth of at least 5 microns. A first chemical vapor deposition process is performed using a first etch/deposition ratio to form a dielectric layer on the bottom and sidewalls of the via and on the upper surface of the substrate. A shape correction process is performed using the second etch/deposition ratio to change the profile of the dielectric layer. Repeating the first chemical vapor deposition process and the shape correction process at least once until the thickness of the dielectric layer reaches a predetermined value.

Description

TSV manufacturing method

technical field

The invention relates to a method for manufacturing through-silicon holes.

Background technique

In order to save valuable layout space or increase the efficiency of interconnection, multiple integrated circuit (IC) chips can be stacked together to form an IC package structure. To achieve this, a three-dimensional (3D) stack packaging technique may be used to package multiple integrated circuit chips together. This three-dimensional (3D) stack packaging technology is widely used in through-silicon vias (TSVs). Through-silicon via (TSV) is a vertical conductive via that can completely penetrate a silicon wafer, silicon plate, substrate or chip made of any material. Nowadays, 3D integrated circuits (3DICs) are widely used in many fields such as memory stacks, image sensor chips, and so on.

Whether a single transistor or a single interconnect, TSVs are a hundred times larger or larger. Due to this size difference, it is not difficult to imagine that the manufacturing methods designed to manufacture traditional integrated circuits may not be able to meet the manufacturing needs of TSVs. Therefore, it is necessary to modify the manufacturing method of traditional integrated circuits for TSVs, so as to safely manufacture TSVs and traditional integrated circuits.

Contents of the invention

The present invention relates to a method for manufacturing through-silicon holes and the following steps. A substrate is provided. A through hole is formed in the substrate, the through hole having a diameter of at least 1 μm and a depth of at least 5 μm. A first chemical vapor deposition process is performed using a first etch/deposition ratio to form a dielectric layer on the bottom and sidewalls of the via hole and the upper surface of the substrate. A shape modification process is performed using a second etch/deposition ratio to change the profile of the dielectric layer. The first chemical vapor deposition process and the shape modification process are repeated at least once until the thickness of the dielectric layer reaches a predetermined value.

Description of drawings

1-6 show a method for manufacturing a through silicon via (TSV) according to an embodiment of the present invention.

Detailed ways

The preferred embodiments of the present invention will be described in detail below. For example, all components, component sub-parts, structures, materials, configurations, etc. described herein can be arbitrarily matched into new embodiments without following the order of description or the embodiments to which they belong. , these embodiments should belong to the category of the present invention. After reading the present invention, those who are familiar with this technology should be able to make some changes and modifications to the above-mentioned components, sub-components, structures, materials, configurations, etc. without departing from the spirit and scope of the present invention. The scope of patent protection of the invention shall be defined by the appended claims of the present claims, and these changes and modifications shall fall within the claims of the present invention.

There are many embodiments and illustrations of the present invention, in order to avoid confusion, similar components are indicated by the same or similar symbols. The diagrams are intended to convey the concept and spirit of the present invention, so the distances, sizes, proportions, shapes, connections, etc. shown in the diagrams are all schematic rather than actual, and all distances that can achieve the same function or result in the same way , size, proportion, shape, connection relationship, etc. can be regarded as equivalents and adopted.

Referring now to FIGS. 1-6 , a method for fabricating a through silicon via (TSV) according to an embodiment of the present invention is shown. In FIG. 1 , a substrate 100 is provided and a via hole 150 is formed in the substrate 100 from the front side of the substrate without penetrating the integrated substrate. The substrate 100 may be a silicon base or a silicon-on-insulator substrate, or the substrate may include shallow trench isolation structures, passive components such as resistors, various doped regions, redundant patterns, and selective active components (if the general Hole intermediate manufacturing process). The via hole 150 can be formed by lithography and etching. Vias 150 are used to form through-silicon vias (TSVs). TSVs (after completion) penetrate the substrate 100 and physically and electrically connect the front and back sides of the substrate 100 . Through-silicon vias (TSVs) are used to transfer operating voltages VSS, VDD or operating signals to integrated circuits (not shown) formed on the substrate 100 , or to transfer signals and/or voltages between different chips. Compared with common active components such as transistors, through-silicon vias (TSVs) have ultra-large dimensions on the micron scale. In one embodiment, the TSV has a diameter of 30 μm and a depth of 100 μm. In another embodiment, the TSV has a diameter of 10 μm and a depth of 30 μm. In yet another embodiment, the TSV has a diameter of at least 1 μm, such as 6 μm, and a depth equal to or greater than 5 μm, such as 10 μm.

Referring next to FIG. 2 , a dielectric layer 10 is formed on the sidewalls and bottoms of the via holes 150 and the front surface of the substrate 100 . Dielectric layer 10 may be formed to a first thickness by a high density plasma chemical vapor deposition (HDPCVD) process using a first etch/deposition ratio. The dielectric layer 10 may include common dielectric materials silicon dioxide and/or silicon nitride. The step coverage of a film formed by a chemical vapor deposition process depends on the angle of arrival and the surface mobility of the precursors used in the process. Basically, a larger angle of arrival results in poorer step coverage and thus poorer thickness uniformity and conformability. Since the corner of the via 150 (the junction of the substrate and the vertical sidewall) has the largest angle of arrival, the dielectric layer 10 forms an overhang at the corner of the via 150 .

Referring next to FIG. 3 , a shape modification process 500 is performed on the dielectric layer 10 . The shape modification process 500 may be a high density plasma chemical vapor deposition (HDPCVD) process with a second etch/deposition ratio, wherein the first etch/deposition ratio is less than the second etch/deposition ratio. Alternatively, the shape modification process 500 can be a physical sputtering process or etching process. If the shape modification process 500 is an HDPCVD process, the thickness of the dielectric layer 10 will increase slightly after the process, and the process can be performed in situ in the same chamber as the HDPCVD described with respect to FIG. 2 . If the shape modification process 500 is a physical sputtering process or etching process, the thickness of the dielectric layer 10 will be slightly reduced after this process, and this process can be in a different process chamber than the HDPCVD described with respect to FIG. 2 One or two processes are carried out in the same mainframe structure without breaking the vacuum. It is worth mentioning that during the physical sputtering process or etching process, oxygen-free substances can be used to generate plasma or ions, so that the surface of the dielectric layer 10 exposed to the plasma or ions is modified or changed. Contains certain atoms from plasma or ions. In one embodiment, fluorine- or nitrogen-containing species may be used to generate plasma or ions during the physical sputtering process or etching process, and the surface of the dielectric layer 10 exposed to such plasmas or ions tends to contain nitrogen. or fluorine atoms. For example, the nitrogen-containing substance can be selected from N ₂ O, NO, N ₂ , NH ₃ , NF ₃ and any combination thereof, and the fluorine-containing substance can be selected from CF ₄ , CHF ₃ , SF ₆ , CH ₂ F ₂ and any combination thereof. In addition to nitrogen-containing species and/or fluorine-containing species, inert gases such as argon and helium may also be used during the shape modification process 500 to increase the effect of physical bombardment. After the shape trimming process 500, it should be possible to improve or completely eliminate the overhang of the dielectric layer at the corners of the via 150, thereby obtaining a predetermined flat profile of the dielectric layer 10'.

If the overhang is not completely eliminated, the processes described in FIG. 2 and FIG. 3 (i.e., the dielectric layer formation process and shape modification process) can be regarded as a cycle and this cycle is repeated until the thickness of the dielectric layer 10' Until a predetermined target value of at least 100 nm to hundreds of nm is reached or the overhang is completely eliminated. By repeating this cycle (i.e. the dielectric layer formation process and shape modification process) several times, the obtained dielectric layer 10' has nitrogen or fluorine distribution interfaces in its thickness direction. Compared with the via hole 150, the overhang may seem small, but the overhang at the corner of the via hole 150 may cause a void problem in the subsequent material filling process. Voids in through-silicon vias (TSVs) can become reliability weaknesses and cause electrical failures.

Referring now to FIG. 4, a barrier/adhesion/seed layer is formed on the dielectric layer 10' and a low resistivity material filled via 150 is formed on the barrier/adhesion/seed layer. Next, perform a planarization process such as one or more chemical mechanical polishing processes to remove excess dielectric layer 10', barrier/adhesion/seed layer and low resistivity material to form a globally flat surface and form a planar A planarized dielectric layer 10", a planarized barrier/adhesion/seed layer 20, and a planarized low-resistivity material 30. The process used to form the barrier/adhesion/seed layer is similar to that used to form the dielectric electrical layer 10, but using a Physical Vapor Deposition (PVD) process rather than a Chemical Vapor Deposition (CVD) process. That is, the barrier/adhesion/seed layer is formed by first using no bias a first physical vapor deposition process to form a first layer of barrier/adhesion/seed layer; and then a biased second physical vapor deposition process to remove the overhang formed at the corner of the via hole 150, The thickness of the barrier/adhesion/seed layer is slightly increased after this step; and the first and second PVD processes are repeated alternately until the barrier/adhesion/seed layer reaches its predetermined thickness or is completely removed It should be understood that the barrier/adhesion/seed layer can consist of several different materials. Therefore, each material may require a different target material and a separate PVD cycle (i.e., to form the barrier First Physical Vapor Deposition Process Used to Form Barrier Layer Second Physical Vapor Deposition Process Used to Form Barrier Layer First Physical Vapor Deposition Process Used to Form Barrier Layer Second Physical Vapor Deposition Process Used to Form Barrier Layer First Physical Vapor Deposition Process for Barrier Layer; First Physical Vapor Deposition Process for Adhesion Layer Second Physical Vapor Deposition Process for Adhesion Layer First Physical Vapor Deposition Process for Adhesion Layer Second Physical Vapor Deposition Process First Physical Vapor Deposition Process for Adhesion Layer; First Physical Vapor Deposition Process for Seed Layer Second Physical Vapor Deposition Process for Seed Layer First Physical Vapor Deposition Process for Seed Layer The second physical vapor deposition process used in the physical vapor deposition process seed layer). The low resistivity material can be formed by chemical vapor deposition process, electroplating process or spin coating process. The barrier/adhesion/seed layer can be Contains tantalum, tantalum nitride, titanium, titanium nitride, tungsten, tungsten nitride, molybdenum, manganese, manganese and any combination thereof. The low resistivity material may comprise tungsten, copper or aluminum. In a preferred embodiment, the resistive The barrier layer is titanium nitride and/or titanium, the seed layer is copper and the low resistivity material is also copper.

Referring now to FIG. 5 , a device/interconnect layer 300 is formed on the substrate 100 , the planarized dielectric layer 10 ″, the planarized barrier/adhesion/seed layer 20 and the planarized low-resistivity material 30 . Device/interconnect layer 300 represents all optional active components, interconnect dielectric layers and contact plugs (if via front-end processing is used), IMD layers, and all interconnect structures embedded therein.

Referring now to FIG. 6, a backside grinding/grinding/thinning process is performed to expose the low resistivity material and barrier/adhesion/seed layer and complete the dielectric layer 10"', barrier/adhesion/seed layer 20. Through-silicon vias (TSVs) 1000 'with conductive material 30 '.

The TSV 1000 manufactured by the method of the present invention does not suffer from the void problem caused by the overhang, so its reliability can be improved.

The above-mentioned embodiments are only examples for the convenience of description, and even if they are arbitrarily modified by those skilled in the art, they will not depart from the scope of protection as claimed in the claims.

Claims (10)

1. A method for manufacturing TSVs, comprising the following steps: providing a substrate; forming a through hole in the substrate, the through hole has a diameter of at least 1 μm and a depth of at least 5 μm; performing a first chemical vapor deposition process using a first etch/deposition ratio to form a dielectric layer on the bottom and sidewalls of the via hole and on the upper surface of the substrate; performing a shape modification process using a second etch/deposition ratio to change the profile of the dielectric layer; and The first chemical vapor deposition process and the shape modification process are repeated at least once until the thickness of the dielectric layer reaches a predetermined value. 2 . The method for manufacturing TSVs according to claim 1 , wherein the first chemical vapor deposition process is a high plasma density chemical vapor deposition process. 3 . 3. The manufacturing method of the TSV according to claim 2. It is characterized in that the shape correction treatment is a high plasma density chemical vapor deposition treatment. 4. The manufacturing method of TSVs according to claim 3, wherein the first chemical vapor deposition process and the shape modification process are performed in-situ. 5 . The method for manufacturing TSVs according to claim 2 , wherein the shape modification process is sputtering or etching. 6 . 6 . The method for manufacturing TSVs according to claim 5 , wherein the first chemical vapor deposition process and the shape modification process are performed ex-situ. 7. The manufacturing method of the TSV according to claim 5. It is characterized in that the first chemical vapor deposition process and the shape modification process are performed without breaking vacuum. 8. The manufacturing method of TSV as claimed in claim 1, further comprising: After repeating the first chemical vapor deposition process and the shape correction process at least once, the dielectric is formed by a first physical vapor deposition process without using a bias voltage and a second physical vapor deposition process using a bias voltage. A barrier layer is formed on the layer. 9. The manufacturing method of TSV as claimed in claim 1, further comprising: After repeating the first chemical vapor deposition process and the shape correction process at least once, a seed layer is formed by a first physical vapor deposition process without using a bias voltage and a second physical vapor deposition process using a bias voltage . 10. The method for manufacturing TSVs as claimed in claim 1, further comprising: After repeating the first chemical vapor deposition process and the shape modification process at least once, a low-resistivity material is formed to fill the via hole.