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CN102683308B - Through silicon via structure and forming method thereof - Google Patents

Through silicon via structure and forming method thereof Download PDF

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CN102683308B
CN102683308B CN201110059582.7A CN201110059582A CN102683308B CN 102683308 B CN102683308 B CN 102683308B CN 201110059582 A CN201110059582 A CN 201110059582A CN 102683308 B CN102683308 B CN 102683308B
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connecting nail
semiconductor substrate
conductive material
forming
via structure
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CN102683308A (en
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赵超
陈大鹏
欧文
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Institute of Microelectronics of CAS
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Abstract

A through silicon via structure and a forming method thereof are provided, wherein the forming method comprises the following steps: providing a semiconductor substrate, wherein the semiconductor substrate comprises an upper surface and a lower surface which are opposite; etching the upper surface of the semiconductor substrate to form an opening; filling a conductive material in the opening to form a first connecting nail; etching the lower surface of the semiconductor substrate to form a groove, wherein the bottom of the groove is exposed out of the first connecting nail; filling an etchable conductive material in the groove, and etching the etchable conductive material to form a second connecting nail, wherein the second connecting nail is vertically connected with the first connecting nail; and filling dielectric layers in the gaps between the second connecting pins and the semiconductor substrate and the gaps between the adjacent second connecting pins. The invention is beneficial to improving the reliability of the through silicon via structure and avoiding the defect of a cavity.

Description

穿硅通孔结构及其形成方法Through-silicon via structure and method for forming the same

技术领域 technical field

本发明涉及半导体技术领域,特别涉及一种穿硅通孔结构及其形成方法。The invention relates to the technical field of semiconductors, in particular to a through-silicon via structure and a forming method thereof.

背景技术 Background technique

3D封装将两片或更多的集成电路垂直堆叠封装在同一芯片中,从而可以减少占用的空间,3D封装中常用的承载集成电路的衬底往往具有穿硅通孔结构(TSV,Through-Silicon-Vias)。通过采用穿硅通孔结构来取代传统的边缘连线来进行3D封装,可以在一个小的器件封装(footprint)中集成更多的逻辑功能。此外,采用穿硅通孔结构可以有效的缩短关键路径(critical path),减小延迟,提高器件速度。3D packaging vertically stacks and packages two or more integrated circuits in the same chip, thereby reducing the occupied space. The substrates commonly used in 3D packaging to carry integrated circuits often have a through-silicon via structure (TSV, Through-Silicon -Vias). By using TSV structure instead of traditional edge wiring for 3D packaging, more logic functions can be integrated in a small device package (footprint). In addition, the adoption of the TSV structure can effectively shorten the critical path, reduce the delay, and increase the speed of the device.

穿硅通孔结构主要是在半导体衬底上形成贯穿的通孔,并在其中填充形成连接钉(nail),之后通过连接钉与另一晶圆或另一芯片上的互连结构相连来实现3D封装,其形成方法有多种,包括:穿硅通孔结构优先法,在形成电路之前首先形成穿硅通孔结构;中期形成穿硅通孔结构法,在完成前道工艺之后(形成器件之后)、进行后道工艺之前(形成互连结构之前)形成穿硅通孔结构;后形成穿硅通孔结构法,在形成电路之后,即形成器件和互连结构之后形成穿硅通孔结构;键合后形成穿硅通孔结构法,在将两个晶圆或将一个晶圆和一块芯片键合后形成穿硅通孔结构法。The through-silicon via structure is mainly realized by forming a through-hole on the semiconductor substrate and filling it to form a nail, and then connecting the nail to another wafer or an interconnection structure on another chip. There are many ways to form 3D packaging, including: through-silicon via structure priority method, which first forms a through-silicon via structure before forming a circuit; mid-term formation of a through-silicon via structure method, after the completion of the previous process (forming the device After) and before the subsequent process (before the formation of the interconnection structure), the through-silicon via structure is formed; after the formation of the through-silicon via structure method, the through-silicon via structure is formed after the circuit is formed, that is, after the device and the interconnection structure are formed ; Bonding to form a through-silicon via structure method, after bonding two wafers or a wafer and a chip to form a through-silicon via structure method.

现有技术的穿硅通孔结构主要是基于铜互连工艺形成的,图1至图5示出了现有技术的一种穿硅通孔结构的形成方法的中间结构的剖面图。The TSV structure in the prior art is mainly formed based on a copper interconnection process. FIG. 1 to FIG. 5 show cross-sectional views of an intermediate structure of a method for forming a TSV structure in the prior art.

参考图1,提供半导体衬底10,所述半导体衬底10上可以形成有半导体器件,如MOS晶体管,也可以形成有半导体器件和互连结构,或者也可以并不包括半导体器件和互连结构。Referring to FIG. 1 , a semiconductor substrate 10 is provided, on which semiconductor devices, such as MOS transistors, may be formed, or semiconductor devices and interconnection structures may be formed, or may not include semiconductor devices and interconnection structures .

参考图2,对所述半导体衬底10的上表面进行刻蚀,形成开口11。Referring to FIG. 2 , the upper surface of the semiconductor substrate 10 is etched to form an opening 11 .

参考图3,形成阻挡层12,覆盖所述开口的底部、侧壁和所述半导体衬底10的上表面,之后在所述阻挡层12上通过电镀法形成金属铜13,填充所述开口,在形成金属铜13之前还包括在所述阻挡层12的表面上形成籽晶层(seedlayer)。Referring to FIG. 3, a barrier layer 12 is formed to cover the bottom, sidewalls and upper surface of the semiconductor substrate 10 of the opening, and then metal copper 13 is formed on the barrier layer 12 by electroplating to fill the opening, Forming a seed layer on the surface of the barrier layer 12 is also included before forming the copper metal 13 .

参考图4,对覆盖在半导体衬底10上的金属铜和阻挡层12进行平坦化,至暴露出所述半导体衬底10的上表面,形成连接钉13a。Referring to FIG. 4 , the metal copper covering the semiconductor substrate 10 and the barrier layer 12 are planarized until the upper surface of the semiconductor substrate 10 is exposed to form connecting nails 13 a.

参考图5,从所述半导体衬底10的下表面对其进行减薄,至暴露出所述连接钉13a,使得所述开口成为贯穿整个半导体衬底10的通孔,完成穿硅通孔结构的形成过程。Referring to FIG. 5 , the semiconductor substrate 10 is thinned from the lower surface until the connecting nail 13a is exposed, so that the opening becomes a through hole penetrating the entire semiconductor substrate 10, and the TSV structure is completed. the formation process.

不管是采用穿硅通孔结构优先法、中期形成穿硅通孔结构法、后形成穿硅通孔结构法还是键合后形成穿硅通孔结构法,基于铜互连工艺的穿硅通孔结构的形成过程中的一个较大的挑战是金属铜的填充问题。例如,在诸如微机电系统(MEMS,Micro-electromechanical System)等应用中,传感器需要与控制电路相连,可以将所述传感器和控制电路分别生产于不同的半导体衬底,并采用穿硅通孔结构将传感器中的每个子单元和控制单元中的每个子单元对应相连,从而简化设计和生产过程,提高良率。Regardless of whether the TSV structure is adopted first, the TSV structure is formed in the middle period, the TSV structure is formed later, or the TSV structure is formed after bonding, the TSV based on the copper interconnection process One of the bigger challenges in the formation of the structure is the filling of copper metal. For example, in applications such as micro-electromechanical systems (MEMS, Micro-electromechanical System), the sensor needs to be connected to the control circuit, the sensor and the control circuit can be produced on different semiconductor substrates, and the through-silicon via structure can be used Each subunit in the sensor is correspondingly connected with each subunit in the control unit, thereby simplifying the design and production process and improving the yield rate.

但是,这类应用往往需要在半导体衬底上形成高密度的穿硅通孔结构,即在单位面积中形成更多数量的穿硅通孔结构。为了满足密度的需求,穿硅通孔结构的直径必须变得很小,但同时为了保证半导体衬底本身的机械强度,半导体衬底的厚度需要足够大,这就造成穿硅通孔的深宽比(aspect ratio)变得很大。随着穿硅通孔结构中通孔的深宽比的不断增大,特别是深宽比大于10∶1时,形成连续的阻挡层和籽晶层变得非常困难,阻挡层和籽晶层的不连续会导致电镀填充后形成的连接钉中出现空洞缺陷(void),使得可靠性下降,甚至有可能造成断路问题。However, such applications often require forming a high-density TSV structure on a semiconductor substrate, that is, forming a greater number of TSV structures per unit area. In order to meet the density requirement, the diameter of the TSV structure must become small, but at the same time, in order to ensure the mechanical strength of the semiconductor substrate itself, the thickness of the semiconductor substrate needs to be large enough, which results in the depth and width of the TSV than (aspect ratio) becomes very large. With the continuous increase of the aspect ratio of the through hole in the through silicon via structure, especially when the aspect ratio is greater than 10:1, it becomes very difficult to form a continuous barrier layer and seed layer. The discontinuity of the electroplating will lead to voids in the connecting nails formed after the electroplating and filling, which will reduce the reliability and may even cause open circuit problems.

关于穿硅通孔结构的更多详细描述,请参考专利号为7,683,459和7,633,165的美国专利。For a more detailed description of the TSV structure, please refer to US Patent Nos. 7,683,459 and 7,633,165.

发明内容 Contents of the invention

本发明解决的问题是现有技术中随着深宽比增大,基于铜互连工艺的穿硅通孔结构可靠性下降的问题。The problem solved by the invention is the problem in the prior art that the reliability of the through-silicon via structure based on the copper interconnection process decreases with the increase of the aspect ratio.

为解决上述问题,本发明提供了一种穿硅通孔结构,包括:To solve the above problems, the present invention provides a through-silicon via structure, including:

半导体衬底,所述半导体衬底上形成有凹槽,所述凹槽中填充有介质层;a semiconductor substrate, a groove is formed on the semiconductor substrate, and a dielectric layer is filled in the groove;

贯穿所述半导体衬底和所述介质层的连接钉,所述连接钉包括上下相接的第一连接钉和第二连接钉,所述第一连接钉内嵌于所述半导体衬底中,所述第二连接钉内嵌于所述介质层中,所述第二连接钉的材料为可刻蚀的导电材料。A connecting nail that penetrates the semiconductor substrate and the dielectric layer, the connecting nail includes a first connecting nail and a second connecting nail connected up and down, and the first connecting nail is embedded in the semiconductor substrate, The second connecting nail is embedded in the dielectric layer, and the material of the second connecting nail is an etchable conductive material.

可选地,所述可刻蚀的导电材料选自铝、掺杂的多晶硅或掺杂的多晶硅锗。Optionally, the etchable conductive material is selected from aluminum, doped polysilicon or doped polysilicon germanium.

可选地,所述介质层的材料选自氧化硅、氮氧化硅或低k介质材料。Optionally, the material of the dielectric layer is selected from silicon oxide, silicon oxynitride or low-k dielectric material.

可选地,所述第一连接钉的材料选自铜、钨、铝或掺杂的多晶硅。Optionally, the material of the first connecting pin is selected from copper, tungsten, aluminum or doped polysilicon.

本发明还提供了一种穿硅通孔结构的形成方法,包括:The present invention also provides a method for forming a through-silicon via structure, including:

提供半导体衬底,所述半导体衬底包括相对的上表面和下表面;providing a semiconductor substrate comprising opposing upper and lower surfaces;

对所述半导体衬底的上表面进行刻蚀,形成开口;Etching the upper surface of the semiconductor substrate to form an opening;

在所述开口中填充导电材料,形成第一连接钉;filling the opening with a conductive material to form a first connecting nail;

对所述半导体衬底的下表面进行刻蚀,形成凹槽,所述凹槽底部暴露出所述第一连接钉;Etching the lower surface of the semiconductor substrate to form a groove, the bottom of which exposes the first connecting pin;

在所述凹槽中填充可刻蚀的导电材料,并对所述可刻蚀的导电材料进行刻蚀,形成第二连接钉,所述第二连接钉与所述第一连接钉上下相接;filling the groove with an etchable conductive material, and etching the etchable conductive material to form a second connecting nail, the second connecting nail is connected up and down with the first connecting nail ;

在所述第二连接钉与所述半导体衬底之间的空隙以及相邻的第二连接钉之间的空隙中填充介质层。A dielectric layer is filled in the space between the second connecting nail and the semiconductor substrate and the space between adjacent second connecting nails.

可选地,所述可刻蚀的导电材料选自铝、掺杂的多晶硅或掺杂的多晶硅锗。Optionally, the etchable conductive material is selected from aluminum, doped polysilicon or doped polysilicon germanium.

可选地,所述可刻蚀的导电材料为铝,使用物理气相沉积或化学气相沉积在所述凹槽中填充可刻蚀的导电材料。Optionally, the etchable conductive material is aluminum, and the etchable conductive material is filled in the groove by using physical vapor deposition or chemical vapor deposition.

可选地,所述介质层的材料选自氧化硅、氮氧化硅或低k介质材料。Optionally, the material of the dielectric layer is selected from silicon oxide, silicon oxynitride or low-k dielectric material.

可选地,在形成所述第一连接钉之后,形成所述凹槽之前,所述形成方法还包括:Optionally, after forming the first connecting nail and before forming the groove, the forming method further includes:

将所述半导体衬底的上表面固定在承载基板上;fixing the upper surface of the semiconductor substrate on the carrier substrate;

对所述半导体衬底的下表面进行减薄。The lower surface of the semiconductor substrate is thinned.

可选地,在将所述半导体衬底的上表面固定在承载基板上之前,所述形成方法还包括:在所述半导体衬底的上表面形成光刻对准标记(lithographyalignment mark),所述光刻对准标记的深度大于所述第一连接钉的深度。Optionally, before fixing the upper surface of the semiconductor substrate on the carrier substrate, the forming method further includes: forming a lithography alignment mark on the upper surface of the semiconductor substrate, the The depth of the photolithography alignment mark is greater than the depth of the first connection nail.

可选地,所述对所述半导体衬底的下表面进行减薄之后,暴露出所述光刻对准标记。Optionally, after the thinning of the lower surface of the semiconductor substrate, the photolithographic alignment marks are exposed.

可选地,所述承载基板为硅基板或玻璃基板。Optionally, the carrier substrate is a silicon substrate or a glass substrate.

可选地,所述导电材料为铜,所述在所述开口中填充导电材料,形成第一连接钉包括:Optionally, the conductive material is copper, and filling the opening with the conductive material to form the first connecting nail includes:

在所述开口的底部和侧壁依次形成阻挡层和铜籽晶层;sequentially forming a barrier layer and a copper seed layer on the bottom and sidewalls of the opening;

在所述开口中填充金属铜,所述金属铜覆盖所述铜籽晶层;filling the opening with metallic copper, the metallic copper covering the copper seed layer;

对所述金属铜的表面进行平坦化,至暴露出所述半导体衬底的上表面。The surface of the metal copper is planarized until the upper surface of the semiconductor substrate is exposed.

可选地,所述导电材料为钨或铝,使用物理气相沉积(PVD)或化学气相沉积(CVD)在所述开口中填充导电材料。Optionally, the conductive material is tungsten or aluminum, and the opening is filled with the conductive material by using physical vapor deposition (PVD) or chemical vapor deposition (CVD).

可选地,所述导电材料为掺杂的多晶硅,使用化学气相沉积在所述开口中填充导电材料。Optionally, the conductive material is doped polysilicon, and chemical vapor deposition is used to fill the conductive material in the opening.

可选地,在形成所述介质层之后,所述形成方法还包括:对所述介质层的表面进行平坦化,至暴露出所述第二连接钉。Optionally, after forming the dielectric layer, the forming method further includes: planarizing the surface of the dielectric layer until the second connecting nails are exposed.

与现有技术相比,本发明的实施例有如下优点:Compared with the prior art, the embodiments of the present invention have the following advantages:

本发明实施例的穿硅通孔结构的形成方法中,首先在半导体衬底的上表面形成深宽比适度的开口,并在其中填充形成第一连接钉,一般地,所述开口的深宽比选择较为适中的数值,以改善所述第一连接钉的填充效果,避免其中出现空洞缺陷等问题;之后在所述半导体衬底的下表面形成凹槽,在所述凹槽中填充可刻蚀的导电材料并对其进行刻蚀后形成第二连接钉,一般地,可以形成宽度较大的凹槽,即所述凹槽具有较小的深宽比,以改善所述可刻蚀的导电材料的填充效果,从而避免通过刻蚀形成的第二连接钉中的空洞缺陷问题。因此,本实施例形成的穿硅通孔结构能够在具有大深宽比的同时还具有较高的可靠性。In the method for forming the through-silicon via structure according to the embodiment of the present invention, an opening with a moderate aspect ratio is firstly formed on the upper surface of the semiconductor substrate, and the first connecting nail is filled therein. Generally, the depth and width of the opening are Choose a relatively moderate value to improve the filling effect of the first connecting nails and avoid problems such as void defects; then form grooves on the lower surface of the semiconductor substrate, fill the grooves with engraved The etched conductive material is etched to form the second connecting nail. Generally, a groove with a larger width can be formed, that is, the groove has a smaller aspect ratio to improve the etchable The filling effect of the conductive material, thereby avoiding the problem of void defects in the second connecting nails formed by etching. Therefore, the TSV structure formed in this embodiment can have high reliability while having a large aspect ratio.

附图说明 Description of drawings

图1至图5是现有技术的一种穿硅通孔结构的形成方法的剖面结构示意图;1 to 5 are schematic cross-sectional structural views of a method for forming a through-silicon via structure in the prior art;

图6是本发明穿硅通孔结构的形成方法的实施例的流程示意图;6 is a schematic flowchart of an embodiment of a method for forming a through-silicon via structure according to the present invention;

图7至图19是本发明穿硅通孔结构的形成方法的实施例的剖面结构示意图。7 to 19 are schematic cross-sectional structure diagrams of an embodiment of a method for forming a TSV structure according to the present invention.

具体实施方式 Detailed ways

现有技术中形成穿硅通孔结构的方法主要基于铜互连工艺,随着穿硅通孔结构密度的增大,其深宽比也相应的增大,导致铜扩散阻挡层和铜籽晶层可能无法完全覆盖通孔的内表面,从而使得电镀填充后形成的连接钉中产生空洞缺陷,导致穿硅通孔结构的可靠性下降,甚至出现断路问题。The method of forming the TSV structure in the prior art is mainly based on the copper interconnection process. As the density of the TSV structure increases, the aspect ratio also increases accordingly, resulting in the copper diffusion barrier layer and the copper seed crystal The layer may not completely cover the inner surface of the via hole, resulting in void defects in the connection nails formed after plating and filling, resulting in a decrease in the reliability of the TSV structure, and even an open circuit problem.

本发明实施例的穿硅通孔结构的形成方法中,首先在半导体衬底的上表面形成深宽比适度的开口,并在其中填充形成第一连接钉,一般地,所述开口的深宽比选择较为适中的数值,以改善所述第一连接钉的填充效果,避免其中出现空洞缺陷等问题;之后在所述半导体衬底的下表面形成凹槽,在所述凹槽中填充可刻蚀的导电材料并对其进行刻蚀后形成第二连接钉,一般地,可以形成宽度较大的凹槽,即所述凹槽具有较小的深宽比,以改善所述可刻蚀的导电材料的填充效果,从而避免通过刻蚀形成的第二连接钉中的空洞缺陷问题。因此,本实施例形成的穿硅通孔结构能够在具有大深宽比的同时还具有较高的可靠性。In the method for forming the through-silicon via structure according to the embodiment of the present invention, an opening with a moderate aspect ratio is firstly formed on the upper surface of the semiconductor substrate, and the first connecting nail is filled therein. Generally, the depth and width of the opening are Choose a relatively moderate value to improve the filling effect of the first connecting nails and avoid problems such as void defects; then form grooves on the lower surface of the semiconductor substrate, fill the grooves with engraved The etched conductive material is etched to form the second connecting nail. Generally, a groove with a larger width can be formed, that is, the groove has a smaller aspect ratio to improve the etchable The filling effect of the conductive material, thereby avoiding the problem of void defects in the second connecting nails formed by etching. Therefore, the TSV structure formed in this embodiment can have high reliability while having a large aspect ratio.

为使本发明的上述目的、特征和优点能够更为明显易懂,下面结合附图对本发明的具体实施方式做详细的说明。In order to make the above objects, features and advantages of the present invention more comprehensible, specific implementations of the present invention will be described in detail below in conjunction with the accompanying drawings.

在以下描述中阐述了具体细节以便于充分理解本发明。但是本发明能够以多种不同于在此描述的其它方式来实施,本领域技术人员可以在不违背本发明内涵的情况下做类似推广。因此本发明不受下面公开的具体实施方式的限制。In the following description, specific details are set forth in order to provide a thorough understanding of the present invention. However, the present invention can be implemented in many other ways than those described here, and those skilled in the art can make similar extensions without departing from the connotation of the present invention. Accordingly, the present invention is not limited to the specific embodiments disclosed below.

图6示出了本发明的穿硅通孔结构的形成方法的实施例的流程示意图,包括:FIG. 6 shows a schematic flowchart of an embodiment of a method for forming a TSV structure of the present invention, including:

步骤S21,提供半导体衬底,所述半导体衬底包括相对的上表面和下表面;Step S21, providing a semiconductor substrate, the semiconductor substrate comprising opposite upper and lower surfaces;

步骤S22,对所述半导体衬底的上表面进行刻蚀,形成开口;Step S22, etching the upper surface of the semiconductor substrate to form an opening;

步骤S23,在所述开口中填充导电材料,形成第一连接钉;Step S23, filling the opening with a conductive material to form a first connecting nail;

步骤S24,对所述半导体衬底的下表面进行刻蚀,形成凹槽,所述凹槽底部暴露出所述第一连接钉;Step S24, etching the lower surface of the semiconductor substrate to form a groove, the bottom of which exposes the first connecting pin;

步骤S25,在所述凹槽中填充可刻蚀的导电材料,并对所述可刻蚀的导电材料进行刻蚀,形成第二连接钉,所述第二连接钉与所述第一连接钉上下相接;Step S25, filling the groove with an etchable conductive material, and etching the etchable conductive material to form a second connecting nail, the second connecting nail and the first connecting nail connected up and down;

步骤S26,在所述第二连接钉与所述半导体衬底之间的空隙以及相邻的第二连接钉之间的空隙中填充介质层。Step S26 , filling the gap between the second connecting nail and the semiconductor substrate and the gap between adjacent second connecting nails with a dielectric layer.

图7至图19示出了本发明的穿硅通孔结构的形成方法的实施例的剖面示意图,下面结合图6和图7至图19对第一实施例进行详细说明。7 to 19 show schematic cross-sectional views of an embodiment of a method for forming a through-silicon via structure according to the present invention. The first embodiment will be described in detail below with reference to FIGS. 6 and 7 to 19 .

结合图6和图7,执行步骤S21,提供半导体衬底20,所述半导体衬底20包括相对的上表面20a和下表面20b。具体地,所述半导体衬底20可以是硅衬底、锗硅衬底、III-V族元素化合物衬底、碳化硅衬底或其叠层结构,或绝缘体上硅结构,或本领域技术人员公知的其他半导体材料衬底。本实施例中,所述半导体衬底20为硅衬底,其中可以形成有传感器或控制电路等,也可以是空白的硅衬底。With reference to FIG. 6 and FIG. 7 , step S21 is performed to provide a semiconductor substrate 20 including an upper surface 20 a and a lower surface 20 b opposite to each other. Specifically, the semiconductor substrate 20 may be a silicon substrate, a silicon germanium substrate, a III-V group element compound substrate, a silicon carbide substrate or a stacked structure thereof, or a silicon-on-insulator structure, or a person skilled in the art may Other known semiconductor material substrates. In this embodiment, the semiconductor substrate 20 is a silicon substrate, in which sensors or control circuits, etc. may be formed, or may be a blank silicon substrate.

结合图6和图8,执行步骤S22,对所述半导体衬底20的上表面20a进行刻蚀,形成开口20c。作为示例,图8中形成的开口20c的个数为3个。所述开口20c的形成过程可以包括:在所述半导体衬底20的上表面20a上形成光刻胶层并图形化,定义出所述开口20c的图形;以所述图形化后的光刻胶层为掩膜对所述半导体衬底20的上表面20a进行刻蚀,形成所述开口20c;去除所述图形化后的光刻胶层。Referring to FIG. 6 and FIG. 8 , step S22 is performed to etch the upper surface 20 a of the semiconductor substrate 20 to form an opening 20 c. As an example, the number of openings 20c formed in FIG. 8 is three. The forming process of the opening 20c may include: forming and patterning a photoresist layer on the upper surface 20a of the semiconductor substrate 20 to define the pattern of the opening 20c; layer is used as a mask to etch the upper surface 20a of the semiconductor substrate 20 to form the opening 20c; and remove the patterned photoresist layer.

需要说明的是,所述开口20c并没有穿透所述半导体衬底20,其宽度等于预期形成的穿硅通孔结构中的链接钉的宽度,所述开口20c的深度由后续填充形成的第一连接钉的材料和工艺决定,也就是说所述开口20c的深宽比需要保证后续采用常规的CVD、电镀等工艺形成的第一连接钉的填充效果,防止其中出现空洞缺陷。It should be noted that the opening 20c does not penetrate the semiconductor substrate 20, and its width is equal to the width of the link nail in the TSV structure expected to be formed, and the depth of the opening 20c is formed by the subsequent filling. The first connecting nail is determined by the material and process, that is to say, the aspect ratio of the opening 20c needs to ensure the filling effect of the first connecting nail formed by subsequent conventional CVD, electroplating and other processes, and prevent void defects therein.

结合图6和图10,执行步骤S23,在所述开口中填充导电材料23,形成第一连接钉。所述导电材料23选自铜、钨、铝或掺杂的多晶硅。本实施例中,所述导电材料23为铜,所述第一连接钉包括依次形成于所述开口侧壁和底部的阻挡层21和铜籽晶层22。下面参考图9和图10具体说明所述第一连接钉的形成过程。Referring to FIG. 6 and FIG. 10 , step S23 is performed to fill the opening with conductive material 23 to form a first connecting nail. The conductive material 23 is selected from copper, tungsten, aluminum or doped polysilicon. In this embodiment, the conductive material 23 is copper, and the first connecting nail includes a barrier layer 21 and a copper seed layer 22 sequentially formed on the sidewall and bottom of the opening. Referring to FIG. 9 and FIG. 10 , the process of forming the first connecting nail will be described in detail below.

首先参考图9,在所述开口的底部和侧壁依次形成阻挡层21和铜籽晶层22,本实施例中所述阻挡层21和铜籽晶层22还覆盖所述半导体衬底20的上表面20a。所述阻挡层21的材料可以是Ta,TaN等,所述阻挡层21和铜籽晶层22的形成方法可以是PVD。Referring first to FIG. 9, a barrier layer 21 and a copper seed layer 22 are sequentially formed on the bottom and sidewalls of the opening. In this embodiment, the barrier layer 21 and the copper seed layer 22 also cover the semiconductor substrate 20. upper surface 20a. The material of the barrier layer 21 may be Ta, TaN, etc., and the formation method of the barrier layer 21 and the copper seed layer 22 may be PVD.

之后参考图10,在所述开口中填充导电材料23,具体为金属铜,所述金属铜覆盖所述铜籽晶层22;在填充后对所述金属铜的表面进行平坦化,如化学机械抛光(CMP),至暴露出所述半导体衬底20的上表面20a。Referring to FIG. 10, the opening is filled with a conductive material 23, specifically copper metal, which covers the copper seed layer 22; after filling, the surface of the copper metal is planarized, such as chemical mechanical Polishing (CMP) until the upper surface 20a of the semiconductor substrate 20 is exposed.

在其他具体实施例中,所述导电材料23也可以是钨或者铝,其填充方法为PVD或CVD;所述导电材料23还可以是掺杂的多晶硅,其填充方法为CVD,可以使用原位(in-situ)掺杂的方法在多晶硅中引入掺杂离子。In other specific embodiments, the conductive material 23 can also be tungsten or aluminum, and the filling method is PVD or CVD; the conductive material 23 can also be doped polysilicon, and the filling method is CVD, and the in-situ The (in-situ) doping method introduces dopant ions into polysilicon.

结合图6和图14,执行步骤S24,对所述半导体衬底20的下表面20b进行刻蚀,形成凹槽25,所述凹槽25底部暴露出所述第一连接钉。下面参考图11至图14详细说明。Referring to FIG. 6 and FIG. 14 , step S24 is performed to etch the lower surface 20 b of the semiconductor substrate 20 to form a groove 25 , and the bottom of the groove 25 exposes the first connecting pin. The details will be described below with reference to FIGS. 11 to 14 .

首先参考图11,在所述半导体衬底20的上表面20a形成光刻对准标记24,所述光刻对准标记24的深度大于所述第一连接钉的深度,即大于所述开口的深度,更具体的,所述光刻对准标记24的深度大于或等于预期形成的穿硅通孔结构中的连接钉的深度。所述光刻对准标记24可以是形成在所述上表面20a的一个沟槽,也可以是形成沟槽后在其中填充的介质或金属材料。Referring first to FIG. 11, a photolithographic alignment mark 24 is formed on the upper surface 20a of the semiconductor substrate 20, and the depth of the photolithographic alignment mark 24 is greater than the depth of the first connecting pin, that is, greater than the depth of the opening. Depth, more specifically, the depth of the photolithographic alignment mark 24 is greater than or equal to the depth of the connecting nail in the TSV structure to be formed. The photolithographic alignment mark 24 may be a groove formed on the upper surface 20a, or may be a dielectric or metal material filled in the groove after the groove is formed.

之后参考图12,将所述半导体衬底20的上表面20a固定在承载基板30上。所述承载基板30可以是硅基板、玻璃基板等。固定的方法可以是粘合、键合等。Then referring to FIG. 12 , the upper surface 20 a of the semiconductor substrate 20 is fixed on the carrier substrate 30 . The carrier substrate 30 may be a silicon substrate, a glass substrate or the like. The fixing method may be adhesive, bonding, or the like.

之后参考图13,对所述半导体衬底20的下表面20b进行减薄,减薄至剩余的半导体衬底20的厚度能够满足实际应用中对机械强度的要求。减薄后,所述半导体衬底20的下表面20b暴露出所述光刻对准标记24。Referring to FIG. 13 , the lower surface 20b of the semiconductor substrate 20 is thinned until the thickness of the remaining semiconductor substrate 20 can meet the requirements for mechanical strength in practical applications. After thinning, the lower surface 20 b of the semiconductor substrate 20 exposes the photolithographic alignment marks 24 .

之后参考图14,将所述半导体衬底20和所述承载基板30翻转,对所述半导体衬底20的下表面20b进行刻蚀,形成凹槽25。所述凹槽25的底部暴露出所述第一连接钉,本实施例中具体为暴露出所述阻挡层21。所述凹槽25的宽度需足够宽,以保证后续可刻蚀的导电材料的填充效果。本实施例中,所述凹槽25的宽度范围覆盖之前形成在上表面20a的全部第一连接钉的范围。所述凹槽25的形成过程可以包括光刻、刻蚀等。Then referring to FIG. 14 , the semiconductor substrate 20 and the carrier substrate 30 are turned over, and the lower surface 20 b of the semiconductor substrate 20 is etched to form a groove 25 . The bottom of the groove 25 exposes the first connecting nail, specifically the barrier layer 21 in this embodiment. The width of the groove 25 needs to be wide enough to ensure the filling effect of the subsequently etched conductive material. In this embodiment, the width range of the groove 25 covers the range of all the first connecting nails previously formed on the upper surface 20a. The forming process of the groove 25 may include photolithography, etching and the like.

结合图6、图15和图16,执行步骤S25,在所述凹槽中填充可刻蚀的导电材料26,并对所述可刻蚀的导电材料26进行刻蚀,形成第二连接钉26a,所述第二连接钉26a与所述第一连接钉上下相接。具体的,本实施例中,所述第二连接钉26a与所述阻挡层21相接。6, FIG. 15 and FIG. 16, perform step S25, fill the etchable conductive material 26 in the groove, and etch the etchable conductive material 26 to form the second connecting nail 26a , the second connecting nail 26a is in contact with the first connecting nail up and down. Specifically, in this embodiment, the second connecting nail 26a is in contact with the barrier layer 21 .

所述可刻蚀的导电材料26选自铝、掺杂的多晶硅或掺杂的多晶硅锗。本实施例中,所述可刻蚀的导电材料26优选为铝,其填充方法为PVD或CVD。The etchable conductive material 26 is selected from aluminum, doped polysilicon or doped polysilicon germanium. In this embodiment, the etchable conductive material 26 is preferably aluminum, and its filling method is PVD or CVD.

可以通过光刻、刻蚀等工艺对所述可刻蚀的导电材料26进行图形化,从而形成第二连接钉26a,各第二连接钉26a分别与一个位置相对应的第一连接钉上下相接。所述图形化的过程中可以通过所述光刻对准标记24进行对准,以使得刻蚀形成的第二连接钉26a的位置能够与形成于上表面20a的第一连接钉的位置对应。The etchable conductive material 26 can be patterned by photolithography, etching and other processes, so as to form the second connecting nails 26a, and each second connecting nail 26a is vertically connected with a corresponding first connecting nail. catch. During the patterning process, the photolithography alignment mark 24 can be used to align, so that the position of the second connecting pin 26a formed by etching can correspond to the position of the first connecting pin formed on the upper surface 20a.

需要说明的是,在对所述可刻蚀的导电材料26进行刻蚀时,需要将所述可刻蚀的导电材料26刻穿,即刻蚀后形成的空隙的底部暴露出所述半导体衬底20,以保证刻蚀形成的各第二连接钉26a之间彼此绝缘。It should be noted that when the etchable conductive material 26 is etched, the etchable conductive material 26 needs to be etched through, that is, the bottom of the gap formed after etching exposes the semiconductor substrate. 20, so as to ensure that the second connecting nails 26a formed by etching are insulated from each other.

结合图6和图17,执行步骤S26,在所述第二连接钉26a与所述半导体衬底20之间的空隙以及相邻的第二连接钉26a之间的空隙填充介质层27。所述介质层27的材料选自氧化硅、氮氧化硅或低k介质材料,其形成方法可以是CVD。在填充形成所述介质层27的过程中,形成的介质层27会覆盖所述第二连接钉26a的表面,因此之后还可以对所述介质层27的表面进行平坦化,至暴露出所述第二连接钉26a。对所述介质层27的平坦化方法可以是化学机械抛光或选择性刻蚀等。Referring to FIG. 6 and FIG. 17 , step S26 is executed to fill the gap between the second connecting nail 26 a and the semiconductor substrate 20 and the gap between adjacent second connecting nails 26 a with the dielectric layer 27 . The material of the dielectric layer 27 is selected from silicon oxide, silicon oxynitride or low-k dielectric material, and its formation method may be CVD. In the process of filling and forming the dielectric layer 27, the formed dielectric layer 27 will cover the surface of the second connecting nail 26a, so the surface of the dielectric layer 27 can also be planarized afterwards, until the exposed The second connecting nail 26a. The planarization method for the dielectric layer 27 may be chemical mechanical polishing or selective etching.

至此,本实施例形成的穿硅通孔结构可以参考图17,包括:半导体衬底20,所述半导体衬底20上形成有凹槽,所述凹槽中填充有介质层27;贯穿所述半导体衬底20和所述介质层27的连接钉,所述连接钉包括上下相接的第一连接钉(本实施例中具体包括阻挡层21、铜籽晶层22和金属铜23)和第二连接钉26a,其中,第一连接钉内嵌于所述半导体衬底20中,所述第二连接钉内嵌于所述介质层27中,所述第二连接钉的材料为可刻蚀的导电材料。So far, the TSV structure formed in this embodiment can refer to FIG. 17 , including: a semiconductor substrate 20, a groove is formed on the semiconductor substrate 20, and a dielectric layer 27 is filled in the groove; The connecting nails between the semiconductor substrate 20 and the dielectric layer 27, the connecting nails include the first connecting nails connected up and down (in this embodiment, specifically including the barrier layer 21, the copper seed layer 22 and the metal copper 23) and the second connecting nails. Two connecting nails 26a, wherein the first connecting nail is embedded in the semiconductor substrate 20, the second connecting nail is embedded in the dielectric layer 27, and the material of the second connecting nail is etchable conductive material.

本实施例中的穿硅通孔结构由分别形成在上表面的第一连接钉和形成在下表面的第二连接钉组成。由于第一连接钉填充的开口的深宽比适中,因而保证了第一连接钉的填充效果,避免了其中的空洞缺陷;另外,所述第二连接钉是通过填充可刻蚀的导电材料后刻蚀形成的,由于所述凹槽的宽度较大,保证了可刻蚀的导电材料的填充效果,因此也避免了第二连接钉中的空洞缺陷。The TSV structure in this embodiment is composed of first connecting nails formed on the upper surface and second connecting nails formed on the lower surface respectively. Since the aspect ratio of the opening filled by the first connecting nail is moderate, the filling effect of the first connecting nail is guaranteed, and the void defect in it is avoided; in addition, the second connecting nail is filled with an etchable conductive material. Formed by etching, because the width of the groove is relatively large, the filling effect of the etchable conductive material is ensured, so the void defect in the second connecting nail is also avoided.

之后,参考图18,通过所述连接钉,将所述半导体衬底20和基板40对接。在一具体实施例中,所述半导体衬底20的上表面20a上形成有传感器,所述基板40上形成有控制电路,所述控制电路包括多个子单元41,对接后传感器中的各子单元通过连接钉与控制电路中对应的子单元41相连接。Afterwards, referring to FIG. 18 , the semiconductor substrate 20 and the base plate 40 are butted together through the connecting nails. In a specific embodiment, a sensor is formed on the upper surface 20a of the semiconductor substrate 20, a control circuit is formed on the substrate 40, the control circuit includes a plurality of subunits 41, each subunit in the sensor is connected It is connected with the corresponding subunit 41 in the control circuit through the connecting nail.

继续参考图19,将所述承载基板剥离,暴露出所述半导体衬底20的上表面20a。剥离之后,还可以对所述上表面20a进行清洗。此后,还可以对所述半导体衬底20和所述基板40进行划片,将其切割拆分成多个独立的裸片(die)。Continuing to refer to FIG. 19 , the carrier substrate is peeled off to expose the upper surface 20 a of the semiconductor substrate 20 . After peeling off, the upper surface 20a may also be cleaned. Thereafter, the semiconductor substrate 20 and the substrate 40 may also be diced to be divided into a plurality of independent dies.

本发明虽然已以较佳实施例公开如上,但其并不是用来限定本发明,任何本领域技术人员在不脱离本发明的精神和范围内,都可以利用上述揭示的方法和技术内容对本发明技术方案做出可能的变动和修改,因此,凡是未脱离本发明技术方案的内容,依据本发明的技术实质对以上实施例所作的任何简单修改、等同变化及修饰,均属于本发明技术方案的保护范围。Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention, and any person skilled in the art can use the methods disclosed above and technical content to analyze the present invention without departing from the spirit and scope of the present invention. Possible changes and modifications are made in the technical solution. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention, which do not depart from the content of the technical solution of the present invention, all belong to the technical solution of the present invention. protected range.

Claims (16)

1.一种穿硅通孔结构,其特征在于,包括:1. A through-silicon via structure, characterized in that, comprising: 半导体衬底,所述半导体衬底上形成有凹槽,所述凹槽中填充有介质层;a semiconductor substrate, a groove is formed on the semiconductor substrate, and a dielectric layer is filled in the groove; 贯穿所述半导体衬底和所述介质层的连接钉,所述连接钉包括上下相接的第一连接钉和第二连接钉,所述第一连接钉内嵌于所述半导体衬底中,所述第二连接钉内嵌于所述介质层中,所述第二连接钉的材料为可刻蚀的导电材料;所述第一连接钉和所述第二连接钉上下对准,第二连接钉的宽度与第一连接钉的宽度相等。A connecting nail that penetrates the semiconductor substrate and the dielectric layer, the connecting nail includes a first connecting nail and a second connecting nail connected up and down, and the first connecting nail is embedded in the semiconductor substrate, The second connecting nail is embedded in the dielectric layer, and the material of the second connecting nail is an etchable conductive material; the first connecting nail and the second connecting nail are aligned up and down, and the second connecting nail is aligned up and down. The width of the connecting nail is equal to the width of the first connecting nail. 2.根据权利要求1所述的穿硅通孔结构,其特征在于,所述可刻蚀的导电材料选自铝、掺杂的多晶硅或掺杂的多晶硅锗。2 . The through silicon via structure according to claim 1 , wherein the etchable conductive material is selected from aluminum, doped polysilicon or doped polysilicon germanium. 3.根据权利要求1所述的穿硅通孔结构,其特征在于,所述介质层的材料选自氧化硅、氮氧化硅或低k介质材料。3. The through-silicon via structure according to claim 1, wherein the material of the dielectric layer is selected from silicon oxide, silicon oxynitride or low-k dielectric material. 4.根据权利要求1所述的穿硅通孔结构,其特征在于,所述第一连接钉的材料选自铜、钨、铝或掺杂的多晶硅。4. The through-silicon via structure according to claim 1, wherein the material of the first connecting pin is selected from copper, tungsten, aluminum or doped polysilicon. 5.一种穿硅通孔结构的形成方法,其特征在于,包括:5. A method for forming a through-silicon via structure, comprising: 提供半导体衬底,所述半导体衬底包括相对的上表面和下表面;providing a semiconductor substrate comprising opposing upper and lower surfaces; 对所述半导体衬底的上表面进行刻蚀,形成开口;Etching the upper surface of the semiconductor substrate to form an opening; 在所述开口中填充导电材料,形成第一连接钉;filling the opening with a conductive material to form a first connecting nail; 对所述半导体衬底的下表面进行刻蚀,形成凹槽,所述凹槽底部暴露出所述第一连接钉;Etching the lower surface of the semiconductor substrate to form a groove, the bottom of which exposes the first connecting pin; 在所述凹槽中填充可刻蚀的导电材料,并对所述可刻蚀的导电材料进行刻蚀,形成第二连接钉,所述第二连接钉与所述第一连接钉上下相接;所述第一连接钉和所述第二连接钉上下对准,第二连接钉的宽度与第一连接钉的宽度相等;filling the groove with an etchable conductive material, and etching the etchable conductive material to form a second connecting nail, the second connecting nail is connected up and down with the first connecting nail ; The first connecting nail and the second connecting nail are aligned up and down, and the width of the second connecting nail is equal to the width of the first connecting nail; 在所述第二连接钉与所述半导体衬底之间的空隙以及相邻的第二连接钉之间的空隙中填充介质层。A dielectric layer is filled in the space between the second connecting nail and the semiconductor substrate and the space between adjacent second connecting nails. 6.根据权利要求5所述的穿硅通孔结构的形成方法,其特征在于,所述可刻蚀的导电材料选自铝、掺杂的多晶硅或掺杂的多晶硅锗。6 . The method for forming a through-silicon via structure according to claim 5 , wherein the etchable conductive material is selected from aluminum, doped polysilicon or doped polysilicon germanium. 7.根据权利要求5所述的穿硅通孔结构的形成方法,其特征在于,所述可刻蚀的导电材料为铝,使用物理气相沉积或化学气相沉积在所述凹槽中填充可刻蚀的导电材料。7. The method for forming a through-silicon via structure according to claim 5, wherein the etchable conductive material is aluminum, and physical vapor deposition or chemical vapor deposition is used to fill the etchable conductive material in the groove. etched conductive material. 8.根据权利要求5所述的穿硅通孔结构的形成方法,其特征在于,所述介质层的材料选自氧化硅、氮氧化硅或低k介质材料。8 . The method for forming a through-silicon via structure according to claim 5 , wherein the material of the dielectric layer is selected from silicon oxide, silicon oxynitride or low-k dielectric material. 9.根据权利要求5所述的穿硅通孔结构的形成方法,其特征在于,在形成所述第一连接钉之后,形成所述凹槽之前,还包括:9 . The method for forming a TSV structure according to claim 5 , further comprising: after forming the first connecting nail and before forming the groove: 将所述半导体衬底的上表面固定在承载基板上;fixing the upper surface of the semiconductor substrate on the carrier substrate; 对所述半导体衬底的下表面进行减薄。The lower surface of the semiconductor substrate is thinned. 10.根据权利要求9所述的穿硅通孔结构的形成方法,其特征在于,在将所述半导体衬底的上表面固定在承载基板上之前,还包括:在所述半导体衬底的上表面形成光刻对准标记,所述光刻对准标记的深度大于所述第一连接钉的深度。10. The method for forming a through-silicon via structure according to claim 9, further comprising: before fixing the upper surface of the semiconductor substrate on the carrier substrate: Photolithographic alignment marks are formed on the surface, and the depth of the photolithographic alignment marks is greater than the depth of the first connecting nails. 11.根据权利要求10所述的穿硅通孔结构的形成方法,其特征在于,所述对所述半导体衬底的下表面进行减薄之后,暴露出所述光刻对准标记。11 . The method for forming a through-silicon via structure according to claim 10 , wherein the photolithography alignment mark is exposed after the lower surface of the semiconductor substrate is thinned. 12.根据权利要求9所述的穿硅通孔结构的形成方法,其特征在于,所述承载基板为硅基板或玻璃基板。12 . The method for forming a through-silicon via structure according to claim 9 , wherein the carrier substrate is a silicon substrate or a glass substrate. 13 . 13.根据权利要求5所述的穿硅通孔结构的形成方法,其特征在于,所述导电材料为铜,所述在所述开口中填充导电材料,形成第一连接钉包括:13. The method for forming a through-silicon via structure according to claim 5, wherein the conductive material is copper, and filling the opening with a conductive material to form a first connecting nail comprises: 在所述开口的底部和侧壁依次形成阻挡层和铜籽晶层;sequentially forming a barrier layer and a copper seed layer on the bottom and sidewalls of the opening; 在所述开口中填充金属铜,所述金属铜覆盖所述铜籽晶层;filling the opening with metallic copper, the metallic copper covering the copper seed layer; 对所述金属铜的表面进行平坦化,至暴露出所述半导体衬底的上表面。The surface of the metal copper is planarized until the upper surface of the semiconductor substrate is exposed. 14.根据权利要求5所述的穿硅通孔结构的形成方法,其特征在于,所述导电材料为钨或铝,使用物理气相沉积或化学气相沉积在所述开口中填充导电材料。14 . The method for forming a through-silicon via structure according to claim 5 , wherein the conductive material is tungsten or aluminum, and the conductive material is filled in the opening by physical vapor deposition or chemical vapor deposition. 15.根据权利要求5所述的穿硅通孔结构的形成方法,其特征在于,所述导电材料为掺杂的多晶硅,使用化学气相沉积在所述开口中填充导电材料。15 . The method for forming a through-silicon via structure according to claim 5 , wherein the conductive material is doped polysilicon, and the conductive material is filled in the opening by chemical vapor deposition. 16.根据权利要求5所述的穿硅通孔结构的形成方法,其特征在于,在形成所述介质层之后,还包括:对所述介质层的表面进行平坦化,至暴露出所述第二连接钉。16. The method for forming a through-silicon via structure according to claim 5, further comprising: after forming the dielectric layer, planarizing the surface of the dielectric layer until the first Two connecting nails.
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