CN104112747A - Memory device, method of manufacturing the same, and method of accessing the same - Google Patents

Abstract

The application discloses a memory device, a manufacturing method and an access method thereof. An example storage device may include: a substrate; the transistor comprises a gate stack, a source region and a drain region, wherein the source region and the drain region are arranged on two sides of the gate stack; a capacitor structure formed in the substrate, at least a portion of the capacitor structure extending below a channel region of the transistor, wherein the memory device further comprises a tunneling channel between the capacitor structure and a drain region of the transistor, the tunneling channel being configured to allow carriers in the channel region of the transistor to enter the capacitor structure or to release carriers stored in the capacitor structure by a tunneling effect when the transistor is turned on and a certain voltage difference exists between a source region of the transistor and the capacitor structure.

Description

Memory device, manufacturing method and access method thereof

technical field

The present disclosure relates to the field of semiconductors, and more particularly, to a storage device, a manufacturing method and an access method thereof.

Background technique

A floating-gate transistor structure is a common implementation of flash memory devices. However, as devices continue to be miniaturized, less and less charge can be stored in the floating gate. This causes the threshold voltage of the device to fluctuate and thus lead to errors. In addition, since the floating gate transistor structure requires two gate dielectric layers, it is difficult to further miniaturize because the total gate dielectric thickness is relatively large.

Contents of the invention

An object of the present disclosure is at least in part to provide a memory device, a method of manufacturing the same, and an access method thereof.

According to one aspect of the present disclosure, there is provided a memory device, including: a substrate; a transistor formed on the substrate, including a gate stack and source and drain regions on both sides of the gate stack; a capacitor structure formed in the substrate , at least a portion of the capacitor structure extends below the channel region of the transistor, wherein the memory device further includes a tunneling channel between the capacitor structure and the drain region of the transistor, the tunneling channel is configured to be configured when the transistor is turned on and the transistor When there is a certain voltage difference between the source region of the transistor and the capacitor structure, the carriers in the channel region of the transistor are allowed to enter the capacitor structure or the carriers stored in the capacitor structure are released through the tunneling effect.

According to another aspect of the present disclosure, there is provided a method of manufacturing a memory device, including: forming a trench in a substrate; forming a capacitor structure and a tunneling channel in the trench; forming a transistor on the substrate, the transistor comprising the gate stack and the source and drain regions on both sides of the gate stack, so that the channel region of the transistor is at least partially above the capacitor structure, and the drain region is adjacent to the tunneling channel; wherein the tunneling channel is configured to be turned on when the transistor And when there is a certain voltage difference between the source region of the transistor and the capacitor structure, through the tunneling effect, the carriers in the channel region are allowed to enter into the capacitor structure or the carriers stored in the capacitor structure are released.

According to yet another aspect of the present disclosure, there is provided a method for accessing the above storage device, including: applying a turn-on voltage through a word line to turn on the transistor, and applying a first bias to the source through the bit line, enabling charge carriers to enter and store in the capacitor structure, thereby storing a first state in the memory device; and applying a turn-on voltage through the word line to turn on the transistor, and applying a second bias to the source through the bit line , enabling carriers to be released from the capacitor structure to store a second state in the memory device, wherein the threshold voltage of the transistor in the first state is different from the threshold voltage of the transistor in the second state.

According to an exemplary embodiment of the present invention, a memory device includes a capacitor structure formed under a channel region of a transistor. This capacitor structure can act as the back gate of the transistor and thus can control the threshold voltage of the transistor. This arrangement of memory devices helps to increase the space (in the capacitor structure) for storing charges and thus reduces fluctuations in threshold voltage. Furthermore, by optimizing the back gate capacitance and the dielectric leakage current between the drain region and the back gate capacitance, the memory device disclosed herein can be used as a dynamic random access memory (DRAM).

Description of drawings

The above and other objects, features and advantages of the present disclosure will be more clearly described through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

1( a ) is a cross-sectional view showing a memory device according to one embodiment of the present disclosure, and FIG. 1( b ) is a cross-sectional view showing an example connection of the memory device;

2-15 are schematic diagrams illustrating various stages in the process of manufacturing a memory device according to another embodiment of the present disclosure;

FIG. 16 is a schematic diagram illustrating an access principle of a memory device according to another embodiment of the present disclosure.

Detailed ways

Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. It should be understood, however, that these descriptions are exemplary only, and are not intended to limit the scope of the present disclosure. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concepts of the present disclosure.

Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. The figures are not drawn to scale, with certain details exaggerated and possibly omitted for clarity of presentation. The shapes of the various regions and layers shown in the figure, as well as their relative sizes and positional relationships are only exemplary, and may deviate due to manufacturing tolerances or technical limitations in practice, and those skilled in the art will Regions/layers with different shapes, sizes, and relative positions can be additionally designed as needed.

In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, the layer/element may be directly on the other layer/element, or there may be intervening layers/elements in between. element. Additionally, if a layer/element is "on" another layer/element in one orientation, the layer/element can be located "below" the other layer/element when the orientation is reversed.

According to an embodiment of the present disclosure, there is provided a storage device (eg, flash memory). The memory device may include transistors formed on a substrate and capacitor structures formed in the substrate (thus, a 1T1C memory configuration may be formed). At least a portion of the capacitor structure may extend below the channel region of the transistor and thus be able to act as the back gate of the transistor.

The memory device may also include a tunneling channel between the capacitor structure and the transistor (eg, its drain). The tunneling channel allows charge exchange between the transistor and the capacitor structure through the tunneling effect (eg majority carriers of the transistor, such as electrons for n-type devices and holes for p-type devices). For example, such a tunneling channel may include a tunneling dielectric layer adjacent to the capacitor structure and a conductive channel between the tunneling dielectric layer and a transistor (eg, its drain region). The thickness of the tunneling dielectric may be set to enable tunneling to occur. Specifically, the thickness of the tunneling dielectric layer can be set such that the carriers flowing due to the conduction of the transistor can tunnel through the dielectric layer when there is a certain voltage difference between the source region of the transistor and the capacitor structure, for example, about 0.3-15nm. For example, when a transistor is turned on and carriers (e.g., electrons) flow from the source region to the drain region, the carriers can pass through the tunneling channel and tunnel through the tunneling dielectric layer to enter and thus be stored in the capacitor structure ; on the other hand, when the transistor is turned on, the carriers stored in the capacitor structure (if present) can be made to tunnel through the tunneling dielectric layer by applying an appropriate bias on the source and/or drain regions, and released through conductive channels. In this way, the memory device can exhibit (at least) two states: the capacitor structure has charge stored in it, and the capacitor structure has no charge stored in it (e.g., the state with charge stored in the capacitor structure can be considered a logic "1", while the A state where there is no stored charge in the capacitor structure is considered a logic "0"; and vice versa).

On the other hand, since the capacitor structure can act as the back gate of the transistor, the charge in the back gate affects the threshold voltage of the transistor. Thus, depending on whether or not charge is stored in the back gate capacitor, the transistor can exhibit different threshold voltages and thus different electrical characteristics. Thus, the state (or, "data") of the memory device can be read out based on the electrical characteristics of the transistors.

According to an example, the capacitor structure and the tunneling channel may be formed in trenches extending from the surface of the substrate into the interior of the substrate. In order to form a back gate without affecting the arrangement of the transistor, the opening of the trench at the substrate surface may be located on one side of the transistor (for example, its drain region), and the trench may extend from this side in the substrate to below at least a portion of the channel region. In this way, the trench may have a first portion extending substantially vertically from the opening into the substrate, and a second portion extending substantially laterally from the first portion downwards of the channel region. That is, the trench extends from the opening on the transistor side into the substrate and detours around the region where the transistor is formed. On the other hand, in order to realize charge storage/release, the trench (eg, its first portion) may be adjacent to the transistor (eg, its drain region), so that the tunneling channel formed in the trench can exchange charges with the transistor.

In this case, the capacitor structure can be realized as a trench type capacitor. For example, the capacitor structure may include a capacitor dielectric layer on a portion of the inner wall of the trench and a capacitor plate layer formed in the trench adjacent to the capacitor dielectric layer, and may also include a capacitor plate layer formed in the substrate adjacent to the capacitor dielectric layer. The conductive region of the capacitor (acting as the other plate of the capacitor). The thickness of the capacitor dielectric layer may be thicker than that of the tunneling dielectric layer, for example about 1-45 nm.

According to an advantageous example of the present disclosure, the transistor is implemented as n-type (so that its source and drain regions are n-type doped). In this case, when the transistor is turned on, the carriers flowing in the channel region are mainly electrons. It is easier for electrons to tunnel through the tunneling dielectric layer, enabling charge storage/release. At this time, a transistor may be formed in a p-type well region in the substrate.

Additionally, in case the transistor is an n-type transistor, the other plate of the capacitor can be implemented as an n-type well region in the substrate. At this time, in order to facilitate the manufacture of the contact portion with the plate of the capacitor, an n-type doped region (isolated from the transistor) extending from the substrate surface to the n-type well region may be formed in the substrate. In this way, only the contact portion to the n-type doped region can realize the electrical contact to the plate of the capacitor.

According to some examples of the present disclosure, memory devices may be fabricated as follows. For example, trenches may be formed in the substrate to form capacitor structures and tunneling channels in the trenches. The capacitor structure and the tunneling channel can be formed by sequentially filling the trench with a dielectric layer and a conductive layer, and performing proper etching. Next, transistors may be formed on the substrate. For example, gate stacks can be formed on a substrate and appropriate source/drain implants can be performed to form transistors. The location at which the gate stack is formed (which determines the location of the channel region) can be controlled such that the channel region is at least partially over the capacitor structure formed in the trench so that the capacitor structure can act as a back gate. In addition, during the source/drain implantation, one of the source region and the drain region (for example, the drain region) may be adjacent to the tunneling channel formed in the trench, so as to realize effective charge exchange.

A trench may, for example, be formed to include a first portion extending generally vertically and a second portion extending generally laterally, as described above. Such grooves can be formed, for example, as follows. Specifically, a substantially laterally extending modified region may be formed in the substrate by ion implantation. Here, the so-called "modified region" refers to a part that can have etching selectivity relative to the unmodified region in the substrate. An opening may then be formed extending generally vertically from the substrate surface to the modified region. The transverse dimension of the opening may be smaller than the transverse dimension of the modified region. Through the opening, the modified region is selectively etched to remove it. In this way, a trench is formed (the opening approximately corresponds to the "first part", and the space formed after removal of the modified region approximately corresponds to the "second part").

According to an advantageous example, the opening is located approximately in the middle of the modification zone. In this way, after the capacitor structure and the tunneling channel are formed in the trench, an isolation region can be formed approximately in the middle of the opening, and thus the capacitor structure and the tunneling channel can be divided into two electrically isolated parts, which can be respectively used for Two different storage units. This facilitates device integration.

The disclosure can be presented in various forms, some examples of which are described below.

FIG. 1( a ) is a cross-sectional view illustrating a memory device according to one embodiment of the present disclosure. As shown in FIG. 1( a ), the memory device includes a substrate 100 . The substrate 100 may include a bulk semiconductor substrate such as Si, Ge, a compound semiconductor substrate such as SiGe, GaAs, GaSb, AlAs, InAs, InP, GaN, SiC, InGaAs, InSb, InGaSb, a semiconductor-on-insulator substrate (SO1), etc. . For convenience of description, a bulk silicon substrate and a silicon-based material are used as examples for description below.

The memory device may also include transistors formed on the substrate 100 . The transistor includes a gate stack formed on the substrate 100 , including a gate dielectric layer 128 and a gate conductor layer 130 . In addition, gate spacers 132 are formed on both sides of the gate stack. For example, the gate dielectric layer 128 may include various suitable dielectric materials, preferably a high-K dielectric material, such as HfO ₂ , and its thickness is, for example, about 2-10 nm. The gate conductor layer 130 may include polysilicon, metals such as Ti, Co, Ni, Al, W or alloys thereof, and its thickness is, for example, about 50-150 nm. In the case that the gate dielectric layer 128 includes a high-K dielectric material and the gate conductor layer 130 includes metal, a work function adjustment layer (not shown) may also be sandwiched between them. The gate spacer 132 may include nitride (eg, silicon nitride), and its thickness is, for example, about 40-100 nm. In addition, the transistor also includes source/drain regions 134 formed in the substrate on both sides of the gate stack, for example by ion implantation. For example, source/drain regions 134 include n-type dopants such that the transistor is an n-type device. The channel region of the transistor is below the gate stack, between the source and drain regions.

It should be pointed out here that FIG. 1 only shows an example implementation of transistors. Those skilled in the art know of numerous other transistor implementations that are suitable. In the following examples, an n-type transistor is used as an example for description. However, it should be noted that the present disclosure is not limited thereto. Those skilled in the art can apply the technology of the present disclosure to p-type devices by appropriately changing various doping polarities.

The memory device may further include a capacitor structure formed in the substrate 100 , including a capacitor dielectric layer 114 , a first plate 116 made of a conductive material, and a second plate formed by a conductive region 126 in the substrate 100 . The capacitor dielectric layer 114 may include various suitable dielectric materials, such as oxides (such as silicon oxide), high-K dielectric materials such as HfO ₂ , or combinations thereof, and have a thickness of, for example, about 1-45 nm. The first plate 116 may include various suitable conductive materials, such as doped polysilicon or metallic materials such as TiN, W or combinations thereof. The second plate 126 may include a well region (eg, n-type) formed in the substrate 100, eg, by ion implantation. Preferably, the capacitor structure faces the transistor (in particular its channel region) with its dielectric layer 114 . That is, the second plate 126 is formed substantially adjacent to the lower surface of the capacitor dielectric layer 114 . In this way, the capacitor structure can serve as the back gate of the transistor, and the capacitor dielectric layer 114 can serve as the back gate dielectric, for example.

In addition, the memory device may further include a tunneling channel between the capacitor structure and the drain region of the transistor, including the tunneling dielectric layer 118 and the conductive channel 120 . The tunneling dielectric layer 118 adjoins the capacitor structure and on the one hand enables the storage/release of charge into/from the capacitor structure (eg, through tunneling) and on the other hand electrically isolates the capacitor structure from the transistor. The tunneling dielectric layer 118 may include various suitable dielectric materials, such as oxides (such as silicon oxide), low-K dielectric materials such as SiOF, SiCOH, SiO, SiCO, SiCON, or combinations thereof, and its thickness is, for example, about 0.3-15 nm. . The conductive channel 120 may comprise various suitable conductive materials, such as doped polysilicon or metallic materials such as TiN, W or combinations thereof. The conductive channel 120 may be in electrical contact with one of the source/drain regions 134 (eg, the drain region). Thus, charge from the transistor can pass through the conductive channel 120 and tunnel through the tunneling dielectric layer 118 into the capacitor structure; And release.

According to an advantageous example, the capacitor structure and the tunneling channel are formed such that the capacitor structure, in particular its first plate 116 , does not come into electrical contact with the source/drain region 134 of the transistor. For example, in the example of FIG. 1( a ), where the entirety of the capacitor structure is located substantially below the transistor, tunneling dielectric layer 118 may cover the entire surface of first plate 116 on the opposite side of capacitor dielectric layer 114 (first plate 116 on the side of the capacitor dielectric layer 114 is covered by the capacitor dielectric layer 114 ), so as to effectively ensure the electrical isolation between the capacitor structure and the source/drain region 134 .

In the example of FIG. 1( a ), transistors (as well as capacitor structures and tunneling channels) are shown formed in active regions isolated by shallow trench isolation (STI) 124 . In this case, the substrate 100 may include a well region 142 (eg, a p-type well region for an n-type transistor) therein, and the well region 142 may serve as a body of the transistor. Additionally, in the example of FIG. 1( a ), the second plate 126 (well region) of the capacitor structure is formed to extend outside the active region. In this way, a contact to the second plate 126 can be easily made outside the active area.

FIG. 1( b ) shows a cross-sectional view of an example connection of the memory device shown in FIG. 1( a ). As shown in FIG. 1( b ), an interlayer dielectric layer 136 may be formed, for example, by deposition, on the surface of the structure shown in FIG. 1( a ). The interlayer dielectric layer 136 may include various suitable dielectric materials such as oxides. In the interlayer dielectric layer 136, at positions corresponding to the gate stack and the source/drain region of the transistor, a contact portion with them can be formed; in addition, a contact portion 138 with the second plate 126 of the capacitor structure can also be formed . In order to avoid forming a contact extending into the semiconductor to directly contact the second plate 126 (too long to be easily fabricated), a conductive region 144 may be formed in the substrate 100, for example, doped with a polarity (in this example, n-type) the same doped region as the second plate 126 . In this way, the contact portion 138 can be electrically connected to the second electrode plate 126 through the conductive region 144 .

2-15 are schematic diagrams illustrating various stages in the process of manufacturing a memory device according to another embodiment of the present disclosure.

As shown in FIG. 2, a substrate 1000, such as a bulk silicon substrate, is provided. On the substrate 1000, a thin (eg, about 3-20 nm in thickness) pad oxide layer 1002 may be formed, for example, by deposition. In order to form a trench with a certain lateral extension in the substrate 1000, the process can be performed as follows.

Specifically, a photoresist 1004 may be formed on the pad oxide layer 1002 and patterned to form openings therein. The lateral dimensions of the opening approximately determine the lateral extension of the trenches subsequently formed in the substrate, for example about 60-460 nm. Subsequently, ion implantation (n-type impurity implantation in this example) is performed to form a buried modification region 1006 in the substrate 1000 . The energy of the ion implantation is controlled such that the modified region 1006 is located a distance below the surface of the substrate 1000 . The photoresist 1004 can then be removed.

Next, as shown in FIG. 3 , a mask layer 1008 may be formed on the pad oxide layer 1002 , eg, by deposition. For example, masking layer 1008 includes nitride and has a thickness of about 50-200 nm. On the mask layer 1008, a photoresist 1010 is formed and patterned to form openings therein. The lateral dimension of the opening may be smaller than that of the modified region 1006 , for example, about 20-100 nm, and may be located approximately in the middle of the modified region 1006 .

Subsequently, as shown in FIG. 4 , using the patterned photoresist 1010 as a mask, the mask layer 1008 , the pad oxide layer 1002 and the substrate 1000 are sequentially etched, such as reactive ion etching (RIE). Etching may proceed until modification region 1006 is reached to expose it. Afterwards, the photoresist 1010 may be removed.

Since the modified region 1006 is exposed, the modified region 1006 can be selectively etched relative to the unmodified portion of the substrate 1000 as shown in FIG. 5 , thereby forming a trench 1012 in the substrate 1000 . The groove 1012 may include a first portion 1012-1 extending generally vertically and a second portion 1012-2 extending generally laterally.

Here, in order to remove residual impurities around the modified region 1006 more effectively, the substrate 1000 may be etched a little further. In this way, the groove 1012 expands slightly toward its outer periphery. Preferably, as shown in FIG. 6, the distance D between the top wall of the second portion 1012-2 of the trench 1012 and the substrate surface may be about 10-50 nm, so as to ensure that a transistor can be formed thereon on the one hand, Another aspect ensures that the capacitor formed in the trench 1012 can act as a back gate to the transistor (eg, control the threshold voltage of the transistor).

Next, capacitor structures and tunneling channels may be formed in the trenches 1012 formed as described above.

Specifically, as shown in FIG. 6 , for example, a thin (for example, about 1-45 nm in thickness) capacitor dielectric layer 1014 may be formed by deposition. The capacitor dielectric layer 1014 may include an oxide, a high-K dielectric, or a combination thereof. The trenches may then be filled with a conductive material such as doped polysilicon or metal to form the capacitor plate layer 1016 . This can be done, for example, by depositing a conductive material to fill the trench and then etching back. According to an advantageous example, the conductive material is etched back into its second portion 1012-2 substantially only in the trench. This advantageously ensures isolation between the capacitor structure and subsequently formed transistors. According to another advantageous example, after the conductive material is etched back, the conductive material can be further isotropically etched, so that the capacitor plate layer 1016 is recessed laterally relative to the first portion 1012-1 of the trench, as shown in FIG. 7. This lateral indentation helps to improve ohmic contact problems due to possible dislocations if isolation is subsequently formed in the trench.

Then, as shown in FIG. 8 , the tunneling dielectric layer 1018 and the conductive material 1020 may be sequentially formed, for example, by deposition. For example, tunneling dielectric layer 1018 includes an oxide, a low-K dielectric, or a combination thereof, and has a thickness of about 0.3-15 nm. Conductive material 1020 may include doped polysilicon or metal, which fills trench 1012 .

Next, as shown in FIG. 9 , the conductive material 1020 may be etched back. According to an advantageous example, the conductive material is etched back into its second portion 1012-2 substantially only in the trench. According to another advantageous example, after the conductive material 1020 is etched back, the conductive material 1020 may also be further isotropically etched to be laterally recessed relative to the first portion 1012 - 1 of the trench. The degree of indentation is relatively small so as not to disrupt the encapsulation of the capacitor plate layer 1016 by the tunneling dielectric layer 1018 .

Then, the portion of the tunneling dielectric layer and the portion of the capacitor dielectric layer exposed by the conductive material 1020 after etching back may be sequentially selectively etched. Since the conductive material 1020 is located substantially only in the second portion 1012-2 of the trench and can be laterally recessed relative to the first portion 1012-1 of the trench, removal of the first portion 1012-1 side of the trench can be ensured. Dielectric layers 1014 and 1018 on the walls (through which the subsequently fabricated conductive vias make electrical contact with the transistor).

Next, as shown in FIG. 10 , the trenches may be further filled (eg, by deposition and then etch back) with a conductive material such as doped polysilicon or metal. The conductive material may be the same as or different from the conductive material 1020, which together form the conductive pathway. In the following description, no distinction will be made between the two, and they are collectively shown as 1020 . According to an advantageous example, the top surface of the conductive channel 1020 is not lower than the surface of the substrate 1000 . In this way, a good ohmic contact can be formed between the conductive channel 1020 and the transistor formed later.

In the case of fabricating a plurality of memory devices (for example, fabricating a memory cell array), isolation between memory devices, such as STI, may also be formed. Specifically, as shown in FIG. 11 , a photoresist 1022 may be formed on the structure shown in FIG. 10 , and patterned to have openings where STIs need to be formed. One of the openings may be located approximately in the middle of the first portion 1012-1 of the trench. Finally, etching such as RIE is performed using the patterned photoresist 1022 as a mask to form the trench T. STI 1024 is formed by filling trench T with a dielectric such as oxide, as shown in FIG. 12 . With STI1024, the capacitor structure and the tunneling channel are separated into two parts, which can be used for two different memory devices respectively. Afterwards, the masking layer 1008 can be removed, for example by hot phosphoric acid.

In this way, effectively combining the STI process into the process of the present technology helps to improve manufacturing efficiency. However, the present disclosure is not limited thereto. For example, an STI may be formed in the substrate first to isolate active regions of each device, and then corresponding storage devices may be formed in each active region. In this case, the capacitor structure and the tunneling channel fabricated as described above can be formed in a separate active region and thus used only for a single memory device (equivalent to the case in FIG. 12 where there is no intermediate STI). Also, in this case, the first portion 1012-1 of the groove may be aligned with one end of the second portion 1012-2. That is, "└" or "┘" type grooves are formed instead of the aforementioned "⊥" type grooves.

Then, as shown in FIG. 13 , a conductive well region 1026 may be formed in the substrate 1000 by ion implantation (in this example, implanting n-type impurities) to serve as another plate of the capacitor structure. After ion implantation, annealing may be performed to activate the implanted impurities. Here, the energy of the ion implantation can be controlled so that the conductive well region 1026 is substantially only adjacent to the lower surface of the capacitor dielectric layer 1014 . According to an advantageous example, the conductive well region 1026 may be formed with its underside beyond the STI 1024 so that the plates of the respective capacitors are connected together. In this way, a shared contact can be provided for all capacitors to be electrically connected to their plates.

Although the conductive well region 1026 is formed after the filling is formed in the trench in this example, the present disclosure is not limited thereto. For example, the conductive well region 1026 may be formed after the trench 1012 is formed as shown in FIG. 5 .

In this way, the capacitor structure and the tunneling channel are completed. Subsequently, transistors may be formed on the substrate 1000 (especially in the isolated active region of the STI 1024 ) according to various suitable processes. For example, as shown in FIG. 14, pad oxide layer 1002 may be removed. Then, a gate dielectric layer 1028 and a gate conductor layer 1030 are sequentially formed on the substrate 1000 and patterned to form a gate stack. Then, the gate stack can be used as a mask for halo implantation and extension implantation. Next, gate spacers 1032 are formed on both sides of the gate stack, and source/drain (S/D) implantation is performed using the gate stack and the gate spacers as a mask. Annealing may be performed to activate the implanted impurities and thus form source/drain regions 1034 . According to an advantageous example, after removing the pad oxide layer 1002, ion implantation may be performed to form a p-type well region (not shown) in the substrate 1000, serving as the body region of the transistor.

Thus, the memory device according to this embodiment was obtained. As shown in FIG. 14, the memory device may include transistor and capacitor structures formed on a substrate 1000 (thus forming a 1T1C configuration). The capacitor structure extends below the channel region of the transistor (under the gate stack, sandwiched between the source and drain regions) and can act as the back gate of the transistor. Specifically, the capacitor structure may have its capacitor dielectric layer 1014 facing the channel region. The conductive channel 1020 is in electrical contact with one of the source/drain regions (eg, the drain region) 1034 . Additionally, a tunneling dielectric layer 1018 is sandwiched between the conductive via 1020 and the capacitor structure (specifically, the capacitor plate layer 1016). In this way, on the one hand, there is no conductive connection between the capacitor structure and the transistor; on the other hand, charges can tunnel through the tunneling dielectric layer 1018, so that charges can be stored/released from the capacitor structure.

After forming the memory device as described above, various electrical contacts may also be formed. As shown in FIG. 15 , an interlayer dielectric (ILD) layer 1036 may be deposited on the surface of the structure shown in FIG. 14 . The ILD layer 1036 may include oxide, for example. A planarization process such as CMP may be performed on the ILD layer 1036 to make its surface substantially flat. Then, for example, a contact hole can be formed by photolithography, and a conductive material such as metal (for example, W or Cu, etc.) can be filled in the contact hole to form a contact portion 1038, such as a contact portion with the gate stack, and a source/drain region. contacts and contacts with the capacitor structure (especially the conductive well region 1026). According to an advantageous example, the contact to the gate stack may be connected to a word line of the memory device, and the contact to the source region may be connected to a bit line of the memory device.

In addition, in order to reduce the contact resistance, silicide treatment may be performed before forming the ILD layer 1036 to form the metal silicide 1040 .

Next, the working principle of the memory device according to the embodiment of the present disclosure will be described with reference to FIG. 16 (corresponding to the memory device shown in FIG. 1( b )).

For example, the conductive well region 126 can be grounded through the contact portion 138, the drain region of the transistor can be electrically floated, and the source region of the transistor can be negatively biased through the bit line. In this case, when the transistor is turned on by applying a turn-on voltage to the gate 130 through the word line, there may be a flow of carriers (in this example, electrons) from the source region to the drain region. These carriers may pass through the conductive channel 120 and tunnel through the tunneling dielectric layer 118 to enter and thus be stored in the capacitor structure, as indicated by the solid arrows in FIG. 16 .

On the other hand, the conductive well region 126 can be grounded through the contact portion 138 to electrically float the drain region of the transistor, and positively bias the source region of the transistor through the bit line. In this case, when the transistor is turned on by applying a turn-on voltage to the gate 130 through the word line, the charge stored in the capacitor structure (if any) can be pulled out of the capacitor structure, as shown by the dashed arrow in FIG. 16 shown. In this way, the capacitor structure can be discharged.

Therefore, the memory device can store at least two states: a state in which charge is stored in the capacitor structure (e.g., can be considered as a logic "1"), and a state in which there is no charge stored in the capacitor structure (e.g., can be considered as a logic "0"). "). The presence or absence of charge in the capacitor structure affects the threshold voltage of the transistor (for example, for an n-type device, the threshold voltage Vt1 of the transistor when there are electrons stored in the capacitor structure can be higher than the threshold voltage Vt2 of the transistor when there is no electron stored in the capacitor structure), As a result, transistors can exhibit different electrical characteristics to the outside. The storage state of the storage device can be detected according to the difference in electrical characteristics of the transistor.

For example, when the storage device needs to be read, the conductive well region 126 can be grounded through the contact portion 138 , the drain region can be grounded through the contact portion, and the bit line can be precharged to a predetermined voltage. At this time, a certain bias can be applied to the gate through the word line. The bias can be between Vt1 and Vt2, for example. At this time, the voltage on the bit line will vary according to the state of the memory device. For example, when the memory device is in the "0" state (threshold voltage Vt2, lower), a bias applied on the word line can turn the transistor on. At this time, the voltage on the bit line will change due to the current flow between the source and drain regions of the transistor. And when the memory device is in "1" state (threshold voltage Vt1, higher), the bias applied on the word line is not enough to turn on the transistor. At this time, the voltage on the bit line will not change. Thus, the state (or, "data") stored in the memory device can be read based on the bit line voltage.

In addition, the erasing operation on the storage device may be similar to the operation of writing "0", for example.

In the above description, technical details such as patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design a method that is not exactly the same as the method described above. In addition, although the various embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be advantageously used in combination.

The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of the present disclosure, and these substitutions and modifications should all fall within the scope of the present disclosure.

Claims (18)

1. a memory device, comprising:

Substrate;

The transistor forming on substrate, comprises source region and the drain region of the stacking and stacking both sides of grid of grid;

The capacitor arrangement forming in substrate, at least a portion of this capacitor arrangement extends to below, transistorized channel region,

Wherein, this memory device also comprises the tunnelling passage between capacitor arrangement and transistorized drain region, when this tunnelling passage is configured to have certain voltage difference between transistor turns and transistorized source region and capacitor arrangement, by tunneling effect, allow charge carrier in transistor channel region to enter in capacitor arrangement or releasing capacitor structure in the charge carrier stored.

2. memory device according to claim 1, wherein, tunnelling passage comprises:

The tunnel dielectric layer adjacent with capacitor arrangement; And

Conductive channel between this tunnel dielectric layer and drain region,

Wherein, the thickness of described tunnel dielectric layer is arranged so that described tunneling effect can occur.

3. memory device according to claim 2, wherein, the thickness of tunnel dielectric layer is about 0.3-15nm.

4. memory device according to claim 1, wherein,

Capacitor arrangement and tunnelling tunnel-shaped are formed in from substrate surface and extend to the groove of substrate interior, and wherein this groove is positioned at drain region one side at the opening at substrate surface place, and this groove extends to below at least a portion of channel region from drain region one side in substrate.

5. memory device according to claim 4, wherein, this groove is about 10-50nm in the roof of transistor below apart from the distance of substrate surface.

6. memory device according to claim 4, wherein,

Capacitor arrangement comprise capacitor dielectric on a part of inwall that is positioned at groove and at groove the capacitor pole flaggy with the adjacent formation of capacitor dielectric, and be included in that in substrate, form and conductive region capacitor dielectric adjacency.

7. memory device according to claim 6, wherein, the thickness of capacitor dielectric is about 1-45nm.

8. memory device according to claim 6, wherein, transistor is N-shaped transistor, and conductive region is the N-shaped well region in substrate.

9. memory device according to claim 8, also comprises the p-type well region being formed in substrate, and wherein transistorized source region and drain region are formed in this p-type well region.

10. memory device according to claim 8, also comprises the N-shaped doped region that extends to N-shaped well region from substrate surface, and wherein N-shaped well region can be connected to outside by this N-shaped doped region.

Manufacture the method for memory device, comprising for 11. 1 kinds:

In substrate, form groove;

In groove, form capacitor arrangement and tunnelling passage;

On substrate, form transistor, this transistor comprises source region and the drain region of the stacking and stacking both sides of grid of grid, makes this transistorized channel region be positioned at least in part capacitor arrangement top, and drain region and tunnelling channels abut;

Wherein, when tunnelling passage is configured to have certain voltage difference between transistor turns and transistorized source region and capacitor arrangement, by tunneling effect, allow charge carrier in channel region to enter in capacitor arrangement or releasing capacitor structure in the charge carrier stored.

12. methods according to claim 11, wherein, form groove and comprise:

By Implantation, in substrate, form modified zone;

Form the opening that extends to modified zone from substrate surface;

Via opening, selective etch modified zone.

13. methods according to claim 12, also comprise:

Via opening, further a certain amount of substrate of selective etch.

14. methods according to claim 11, wherein, form capacitor arrangement and tunnelling passage and comprise:

On the fluted substrate of formation, form capacitor dielectric;

In groove, fill the first electric conducting material and eat-back, to form capacitor pole flaggy;

Form tunnel dielectric layer;

In groove, fill the second electric conducting material and eat-back;

Selective etch is exposed by the second electric conducting material after eat-backing successively tunnel dielectric layer part and capacitor dielectric part;

Further in groove, fill the 3rd electric conducting material; And

By Implantation, in substrate, form the conduction well region that serves as another pole plate of capacitor arrangement.

15. methods according to claim 14, wherein, the end face of the 3rd electric conducting material is not less than the surface of substrate.

16. methods according to claim 11, also comprise:

Form isolated area, this isolated area is divided into the capacitor arrangement forming in groove and tunnelling passage two parts of electricity isolation.

17. 1 kinds are carried out the method for access, comprising to memory device according to claim 1:

Apply conducting voltage so that transistor turns by word line, and apply the first biasing by bit line to source electrode, charge carrier can be entered and be stored in capacitor arrangement, thereby store the first state in this memory device; And

Apply conducting voltage so that transistor turns by word line, and apply the second biasing by bit line to source electrode, charge carrier can be discharged from capacitor arrangement, thereby store the second state in this memory device,

Wherein, the threshold voltage of transistor under the first state is different from the threshold voltage of transistor under the second state.

18. methods according to claim 17, also comprise:

Pairs of bit line is precharged to a voltage;

On word line, apply a bias voltage; And

Whether change according to the voltage on bit line, determine and in memory device, store the first state or the second state,

Wherein, between the threshold voltage under threshold voltage and second state of described bias voltage under the first state.